Quatech QSC(LP)-100 Manual de usuario
QSCLP-100
Four Channel Low Profile RS-232
Asynchronous Communications Adapter
for PCI bus
User's Manual
QUATECH, INC. TEL: (330) 434-3154
662 Wolf Ledges Parkway FAX: (330) 434-1409
Akron, Ohio 44311 http://www.quatech.com
1General Information
The Quatech, Inc. QSCLP-100 provides four RS-232 asynchronous serial
communication interfaces for Low Profile IBM-compatible personal computer systems
using the PCI expansion bus. The QSCLP-100 uses Quatech's new Enhanced Serial
Adapter design. Legacy serial port data rates are limited to a maximum of 115,200 bits
per second. Quatech Enhanced Serial Adapters can achieve data rates as high as
921,600 bits per second.
As a PCI device, the QSCLP-100 requires no hardware configuration. The
card is automatically configured by the computer's BIOS or operating system. The four
serial ports share a single interrupt line and are addressed in a contiguous block of 32
bytes. Aspecial interrupt status register is provided to help software to manage the
shared interrupt.
The QSCLP-100's serial ports are implemented using 16550 Universal
Asynchronous Receiver/Transmitters (UARTs). These UARTs contain hardware
buffers (FIFOs) which reduce processing overhead and allow higher data rates to be
achieved.
The QSCLP-100 is supported under several popular operating systems and
environments. Contact the sales department for details on current software offerings.
Most device drivers are available for download from the Quatech world wide web site
at http://www.quatech.com.
QSCLP-100 User's Manual 1
2Hardware Configuration
The QSCLP-100 is automatically configured at boot time by the computer's
BIOS or operating system. There are no required switches or jumpers to set for
installation.
This chapter lists a number of optional jumper settings that control various
hardware features. Jumpers J2-J5are grouped together at the end of the board
opposite the HD-44 connector. Any changes from the factory default should be made
before installing the QSCLP-100 in the computer.
2.1Factory Default Configuration
Figure 2 shows the jumper configuration as shipped from the factory, with two
spare jumpers applied in neutral positions. Remove one or both and apply as shown in
following sections to set optional features.
SPAD
X2
X4
X8
J2
J3
J4
J5
Figure 2--- Factory default jumper configuration
2.2Enable Scratchpad Register (SPAD, J2)
In the default configuration, an Interrupt Status Register and an Options Register
(see page 0) replace the scratchpad (base address + 7) of each UART. If the SPAD
jumper is applied as in Figure 3, the UART scratchpad registers are enabled, and the
Interrupt Status Register and the Options Register are not available.
SPAD
X2
X4
X8
J2
J3
J4
J5
Figure 3--- Enable scratchpad registers
2.3Force High-Speed UART Clock (X2, X4, or X8, J3-J5)
2QSCLP-100 User's Manual
These jumpers force an increase of the UART input clock frequency by a factor
of two, four, or eight. This feature can allow legacy software to use baud rates above
115,200 bits per second. It is also useful if the serial port device driver does not
directly support setting the higher baud rates through the Options Register (see page 0).
If one of these jumpers is applied, it overrides any value written to the Options
Register to set the clock multiplier by software. The effective baud rate will be either
two, four, or eight times the value for which the UART itself is programmed.
The factory default is none of these jumpers applied, which allows for software
control of the clock multiplier via the Options Register. The Options Register powerup
default is for a standard times-1 clock of 1.8432 MHz for compatibility with standard
serial ports.
Figure 4--- Clock multiplier jumper options
SPAD
X2
X4
X8
J2
J3
J4
J5
Force times-eight clock
Baud rates up to 921.6 kbps
SPAD
X2
X4
X8
J2
J3
J4
J5
Force times-two clock
Baud rates up to 230.4 kbps
SPAD
X2
X4
X8
J2
J3
J4
J5
Factory default
software control
SPAD
X2
X4
X8
J2
J3
J4
J5
Force times-four clock
Baud rates up to 460.8 kbps
QSCLP-100 User's Manual 3
3Hardware Installation
1. Turn off the power of the computer system in which the QSCLP-100 is to be
installed.
2. Remove the system cover according to the instructions provided by the
computer manufacturer.
3. Make any desired optional jumper setting changes.
4. Install the QSCLP-100 in any empty PCI expansion slot. The board should be
secured by installing the Option Retaining Bracket (ORB) screw.
5. Replace the system cover according to the instructions provided by the
computer manufacturer.
6. Attach and secure the cable connectors to the desired equipment.
7. Turn on the power of the computer system.
The output of the QSCLP-100 is a 44-pin D-connector. A cable is provided
to convert the D-44 into four standard male D-9connectors with all control signals
provided to each port (RTS, DTR, CTS, DSR, DCD, and RI).
J3
J4
J5
J6
X2
X4
X8
SPAD
Clock multiplier/
scratchpad select
Figure 5--- Jumper/connector locations
4QSCLP-100 User's Manual
(This page intentionally blank.)
QSCLP-100 User's Manual 5
4Address Map and Special Registers
This chapter explains how the four UARTs and special registers are addressed,
as well as the layout of those registers. This material will be of interest to programmers
writing driver software for the QSCLP-100.
4.1Base Address and Interrupt Level (IRQ)
The base address and IRQ used by the QSCLP-100 are determined by the
BIOS or operating system. Each serial port uses 8 consecutive I/O locations. The four
ports reside in a single block of I/O space in eight byte increments, for a total of 32
contiguous bytes, as shown in Figure 5.
Base Address + 24 to Base Address + 31Serial 4
Base Address + 16 to Base Address + 23Serial 3
Base Address + 8 to Base Address + 15Serial 2
Base Address + 0 to Base Address + 7Serial 1
I/O Address RangePort
Figure 6--- Port Address Map
All four serial ports share the same IRQ. The QSCLP-100 signals a hardware
interrupt when any port requires service. The interrupt signal is maintained until no port
requires service. Interrupts are level-sensitive on the PCI bus.
The base address and IRQ are automatically detected by the device drivers
Quatech supplies for various operating systems. For cases where no device driver is
available, such as for operation under DOS, Quatech supplies the "QTPCI" DOS
software utility for manually determining the resources used. See page 0for details.
6QSCLP-100 User's Manual
4.2Enabling the Special Registers
The QSCLP-100 contains two unique registers, an Interrupt Status Register
and an Options Register. These registers are enabled when the SPAD jumper (J6) is
removed (factory default). They replace the UART Scratchpad Register on accesses to
register address 7.
The Interrupt Status Register and Options Register are accessed through the
scratchpad location of any UART. The DLAB bit of the UART (Line Control Register,
bit 7) is used to select between the two registers. The most recent write of a DLAB bit
in any UART selects between the two registers as shown in Figure 6.
Scratchpad RegistersappliedXOptions Registerremoved1Interrupt Status Registerremoved0
Register selected for
address 7 accesses
SPAD JumperDLAB Bit
Figure 7--- DLAB bit selects between special registers
4.3Interrupt Status Register
The read-only Interrupt Status Register can be used to quickly identify which
serial ports require servicing after an interrupt. Reading the Interrupt Status Register will
return the interrupt status of the entire QSCLP-100, as shown in Figure 7. The
individual bits are cleared as the interrupting ports are serviced. The interrupt service
routine should ensure that the interrupt status register reads zero before exiting.
Port 1 --- 1 if interrupt pending0
Port 2 --- 1 if interrupt pending1
Port 3 --- 1 if interrupt pending2
Port 4 --- 1 if interrupt pending3
0 (not used)4
0 (not used)5
0 (not used)6
0 (not used)7 (MSB)
DescriptionBit
Figure 8--- Interrupt Status Register
QSCLP-100 User's Manual 7
4.4Options Register
The Options Register allows software to identify the QSCLP-100 as a Quatech
Enhanced Serial Adapter. It also allows software to set the UART clock rate multiplier.
Figure 8 shows the structure of the Options Register.
The powerup default of the Options Register is all bits zero.
Clock rate multiplier bit 0RR00
Clock rate multiplier bit 1RR11
(reserved, 0)-2
(reserved, 0)-3
(reserved, 0)-4
(reserved, 0)-5
ID bit 0ID06
ID bit 1ID17 (MSB)
DescriptionNameBit
Figure 9--- Options Register bit definitions
4.4.1Enhanced Serial Adapter Identification
The ID bits are used to identify the QSCLP-100 as a Quatech Enhanced Serial
Adapter. Logic operations are performed such that the values read back from these
bits will not necessarily be the values that were written to them. Bit ID1 will return the
logical-AND of the values written to ID[1:0], while bit ID0 will return their
exclusive-OR.
Software can thus identify a Quatech Enhanced Serial Adapter by writing the
ID bits with the patterns shown in the "write" column of Figure 9, then reading the bits
and comparing the result with the patterns in the "read" column. Matching read patterns
verify the presence of the Options Register.
0111 1001 1010 0000 ID0ID1ID0ID1 ReadWrite
Figure 10 --- ID bit write/read table
8QSCLP-100 User's Manual
4.4.2Clock Rate Multiplier
A standard RS-232 serial port operates at a clock speed of 1.8432 MHz. In
order to achieve higher data rates, Quatech Enhanced Serial Adapters can operate at
two times, four times or even eight times this standard clock speed. This is controlled
by the clock rate multiplier bits in the Options Register.
Software can determine the UART clock frequency by reading the clock rate
multiplier bits RR1 and RR0 in the Options Register as shown in Figure 10. RR1 and
RR0 can be set by writing to the Options Register if the X2, X4, and X8 jumpers
(J3-J5) are all removed. If one of these jumpers is applied, the RR1 and RR0 bits are
forced to the appropriate value. Reading the Options Register will always return the
clock rate multiplier at which the board is operating.
* 16750 UART only
921.6 kbaud *14.7456 MHzX811 460.8 kbaud *7.3728 MHzX401 230.4 kbaud3.6864 MHzX210
115.2 kbaud1.8432 MHz
X1
(default)
00
Maximum Data
Rate
UART Clock
Frequency
Clock Rate
Multiplier
RR0RR1
Figure 11 --- Rate Register bit definition
At powerup and reset, the Options Register is initialized to 0. The
QSCLP-100 will thus powerup in the x1 mode with software control of the clock rate
multiplier enabled as long as the X2, X4, and X8 jumpers are not installed.
Software can control high baud rates through a combination of changing the
clock rate multiplier and the UART baud rate divisor. For example, a baud rate of
230.4 kbps could be achieved by setting the clock rate multiplier to X2 mode (or by
applying the X2 jumper) and setting a software application for 115.2 kbps.
QSCLP-100 User's Manual 9
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