PLX Technology PEX8603 Guía rápida de usuario

PEX8603 TQFP-AIC RDK

PLX Technology

Hardware Reference Manual

PEX8603 TQFP-AIC Rapid Development Kit

PEX8603 TQFP-AIC RDK

Preface

Notice

This document contains PLX Confidential and Proprietary information. The contents of this document may not be copied

nor duplicated in any form, in whole or in part, without prior written consent from PLX Technology, Inc.

PLX provides the information and data included in this document for your benefit, but it is not possible to entirely verify

and test all the information, in all circumstances, particularly information relating to non-PLX manufactured products.

PLX makes neither warranty nor representation relating to the quality, content, or adequacy of this information. The

information in this document is subject to change without notice. Although every effort has been made to ensure the

accuracy of this manual, PLX shall not be liable for any errors, incidental, or consequential damages in connection with

the furnishing, performance, or use of this manual or examples herein. PLX assumes no responsibility for damage or

loss resulting from the use of this manual, for loss or claims by third parties, which may arise through the use of the

RDK, or for any damage or loss caused by deletion of data as a result of malfunction or repair.

About This Manual

This document describes the PLX PEX8603 TQFP-AIC RDK, a Rapid Development Kit, from a hardware perspective. It

contains a description of all major functional circuit blocks on the board and also is a reference for the creation of

software for this product. This manual also includes complete schematics and bill of materials.

Revision History

Date

Version

Comments

March

2013

1.0

Initial Release

PEX8603 TQFP-AIC RDK

Table of Contents

1GENERAL INFORMATION..........................................................................................................5

1.1 PEX8603 Features ...................................................................................................................................................7

1.2 PEX8603 AIC RDK Features.................................................................................................................................8

1.3 Getting Started.........................................................................................................................................................9

2PEX8603 RDK HARDWARE ARCHITECTURE ........................................................................10

2.1 Architecture Block Diagram.................................................................................................................................10

2.2 Board Components................................................................................................................................................11

2.3 PEX8603 PCI Express Switch ..............................................................................................................................13

2.4 PCI Express Upstream Port Connection.............................................................................................................13

2.5 PCI Express Downstream Port Connections.......................................................................................................13

2.6 Hardware Strap Pin Dipswitches.........................................................................................................................13

2.7 Dipswitch Setting Tables.......................................................................................................................................14

2.8 Power Circuitry .....................................................................................................................................................16

2.9 Serial EEPROM Interface....................................................................................................................................16

2.10 JTAG Interface ..................................................................................................................................................16

2.11 I2C/SMBUS Interface........................................................................................................................................17

2.12 FATAL_ERR#, and INTA#..............................................................................................................................18

2.13 Reference Clock Circuitry.................................................................................................................................18

2.14 Reset Circuitry ...................................................................................................................................................18

2.15 Port Good Indicator LEDs................................................................................................................................19

2.16 PCIe Protocol Debug .........................................................................................................................................20

2.17 WAKE# and Vaux Support...............................................................................................................................20

3RDK CONFIGURATIONS ..........................................................................................................21

PEX8603 TQFP-AIC RDK

3.1 Default Strap Pin Settings Diagram.....................................................................................................................21

3.2 Hardware Strap Pins.............................................................................................................................................22

3.3 Configuration Modules .........................................................................................................................................22

3.4 Hardware Jumpers................................................................................................................................................23

Figures

Figure 1. PEX8603 RDK Front View ___________________________________________________________________________6

Figure 2. Getting Started ______________________________________________________________________________________9

Figure 3. RDK Architecture ____________________________________________________________________________________10

Figure 4. RDK Component Locations ____________________________________________________________________________12

Figure 5. Configuration Dipswitches ____________________________________________________________________________13

Figure 6. EEPROM in Socket ___________________________________________________________________________________16

Figure 7. Pin Assignment of JTAG Port Header, JP1 ________________________________________________________________17

Figure 8. I2C Plug Orientation _________________________________________________________________________________17

Figure 9. Pin Assignment of I2C Connector JP2 ___________________________________________________________________18

Figure 10. Fatal Error and INTA# LEDs___________________________________________________________________________18

Figure 11. Manual PERST# button ______________________________________________________________________________19

Figure 12 Lane Good LEDs ____________________________________________________________________________________19

Figure 13: Midbus 2.0 Probe Footprint __________________________________________________________________________20

Figure 14. Default Dipswitch Settings ___________________________________________________________________________21

Tables

Table 1. PEX8603 Port Configurations____________________________________________________________________________5

Table 2 Component Table ____________________________________________________________________________________11

Table 3. SW1 Functions ______________________________________________________________________________________14

Table 4. SW2 Functions ______________________________________________________________________________________15

Table 5. SW3 Functions ______________________________________________________________________________________15

Table 6. SW4 Functions ______________________________________________________________________________________15

Table 7. Port Indicator Blink Pattern ____________________________________________________________________________19

Table 8. PEX8603 StrapPortCfg Settings _________________________________________________________________________22

Table 9. Configuration Module Description_______________________________________________________________________22

Table 10. PEX8603 Jumper Settings_____________________________________________________________________________23

PEX8603 TQFP-AIC RDK

1General Information

The PEX8603 TQFP RDK is a PLX Rapid Development Kit intended primarily for use by PLX customers for silicon

evaluation and design reference. The form factor is based on the PCI Express Card Electromechanical specification.

The board is designed to work by plugging internally into a PCI Express compliant motherboard. Figure 1 shows the

board outline and component placement.

The PEX8603 TQFP RDK has 1 x4 upstream port connector and 2 x16 PCIe connectors. The upstream edge connector

has 1 or 2 PCIe Gen2 lanes electrically connected to it, and the downstream PCIe connectors have 1 PCIe Gen2 lane

each electrically connected to it depending on the installed configuration module.

The PEX8603 TQFP RDK supports the use of one configuration module slot to provide flexibility in the routing of PCIe

lane 1 to either the x4 PCIe edge connector or to one of the PCIe slots. The Configuration Module enables the RDK to

support the following port configurations:

Table 1. PEX8603 Port Configurations

PEX 8603

Port Configuration

x1, x1, x1

x2, x1

The PEX8603 TQFP RDK meets the ROHS guidelines for electronic components, and hardware.

PEX8603 TQFP-AIC RDK

JP11

JP8

JP9

JP7

712

6596

97128

D8 4

I J

A B

C D E F G

JP1

10 9

B82

B12

B11

PCB Edge

712

1924

U7 5

B32

B17

JP10

10 11

U12

U13 20

TP48

TP21

TP32

TP29

TP28

TP27

TP26

TP25

TP24

TP23

TP22

TP20

TP19

TP18

TP31

TP30

TP17

TP16

TP15

TP37

TP36

TP35

TP34

TP33

TP3

TP47

TP46

TP1

TP2

TP4

C138

C24

C22

C132

C120

C18

C113

C126

C36

C43

C56

C57

C68

C69

C70

C71

C59

C58

RN2

RN1

RN3

RN4

RN5

RN6

SW2

ON 16

SW3

SW4

A70 A82

B70 B82

A60A50

A40

B60

B40 B50

A30A20A12

B12 B20 B30

A10A2

B2 B10

A70 A82

B82

B70

A60A50

A40

B60

B40 B50

A30A20A12

B12 B20 B30

A10A2

B2 B10

SW1

U10

U11

C15

C11

C10

D10

D11

R37

R36

R35

R34

C35

C34

C32

C31

C30

C29

C128

C124

C127

JP4

JP2

JP6

JP5

JP3

R110

C60

C137

R109

R108

R107

R106

R105

R104

R31

R44

R43

C33

R40

R46

R41

R33

R32

R29

R27

R26

C26

C65

C112

C125

C52

C53

C64

C66C67

C46

C47

R77

R81

C55

C54

R48

R49

C51

C49

R19

R20

R23

R22

R21

R18

R17

R16

R15

R14

R13

C16

C14 C13

C12

C44

C45

R58

R59R63

R67 R68

R71

R85

R84

R83

R82

R80

R79R78

R76R75

R74

R53

SLOT_PERST#

DBGMODE

SMBUS_EN#

PORTCFG0

UPCFG_TIMER_EN#

I2C_ADDR2

I2C_ADDR1

I2C_ADDR0

GPIO1

GPIO2

TESTMODE3

TESTMODE2

TESTMODE1

PROBE_MODE#

SERDES_MODE_EN#

PLL_BYPASS#

FAST_BRINGUP#

DEBUG_SEL#

TESTMODE0

GPIO0

GPIO3

PLX Technology, Inc. C 2013

SLOT 1

3.3VAUX

3.3VCC

12VCC

PWRGD_12

PWRGD2_12

I2C

SLOT 2

SLOT 3

LANEGOOD3#

LANEGOOD2#

LANEGOOD1#

LANEGOOD0#

FERR#

INTA#

PWRON_RST#

PERST#

DBG_PR2

DBG_PR3

DBG_SELBUS

DBG_PR0

DBG_PR1

JTAG

Figure 1. PEX8603 TQFP RDK Front View

PEX8603 TQFP-AIC RDK

1.1 PEX8603 Features

The PEX 8603 supports the following features:

•3-Port PCI Express switch

–3 Lanes with integrated on-chip SerDes

–Low-power SerDes (under 90 mW per Lane)

–Fully Non-Blocking Switch architecture

–Port configuration

3 independent Ports

Choice of Link width (quantity of Lanes) per unique Link/Port (x1, x2)

Configurable with serial EEPROM or I2C

•High Performance

–Full line rate on all Ports

–Cut-Thru packet latency of less than 250 ns between symmetric (x1 to x1)

–Maximum Payload Size –256 bytes

•Quality of Service (QoS) support

–All Ports support one, full-featured Virtual Channel (VC0)

–All Ports support eight Traffic Class (TC[7:0]) mapping, independently of the other Ports

–Weighted Round-Robin (WRR) Port arbitration

•Reliability, Availability, Serviceability (RAS) features

–Electromechanical Interlock supported with Power Enable output

–Baseline and Advanced Error Reporting capability

–JTAG AC/DC boundary scan

INTA# (PEX_INTA#) and FATAL ERROR (FATAL_ERR#) (Conventional PCI SERR# equivalent) pin support

3 General-Purpose Input/Output (GPIO) pins, which can be used for Link Status LEDs, GPIOs, and/or Interrupt

inputs

•Other PCI Express Capabilities

–Transaction Layer Packet (TLP) Digest support for Poison bit

–Lane reversal (Port 0 only, when Port 0 is configured with a x2 Link width)

–Polarity reversal

–Conventional PCI-compatible Link Power Management states

L0, L0s, L1, L2, and L2/L3 Ready

L3 (with Vaux supported)

–Conventional PCI-compatible Device Power Management states

D0, D1, D2, and D3hot

D3cold (with Vaux supported)

–Active State Power Management (ASPM)

–Dynamic speed (2.5 or 5.0 GT/s) negotiation

–Dynamic Link-width negotiation

•Out-of-Band Initialization options

PEX8603 TQFP-AIC RDK

–Serial EEPROM

–I2C and SMBus (7-bit Slave address with 100 Kbps)

•Testability –JTAG support for DC

•14x14mm2128-lead TQFP package

•Typical power –0.8W

1.2 PEX8603 AIC RDK Features

•PEX8603-AB PCI Express 3-port Gen 2 PCIE Switch

•X4 Upstream goldfinger

•Two downstream PCI Express x16 Slot Connectors

•DIP Switches for hardware configuration of PEX8603

•Socketable Serial EEPROM

•Manual push-button PERST# capability

•I2C /SMBus header for Out-of-Band register access

•JTAG header for testability

PEX8603 TQFP-AIC RDK

1.3 Getting Started

Figure 2. Getting Started

Follow the following steps to use the RDK.

1) Plug board into x16 PCI Express slot on motherboard.

2) Check and set dipswitches for desired port configuration.

3) Check that the correct configuration module is plugged into the socket.

4) Plug in PCI Express endpoints into downstream slots.

After all these steps are completed, system can be powered on.

PEX8603 TQFP-AIC RDK

2PEX8603 RDK Hardware Architecture

2.1 Architecture Block Diagram

PEX 8603 TQFP

(U1)

Lane0

Lane2

X4 Card Edge(P2)

X16 Connector(P3)

RefClk

Buffer (U8)

EEPROM

(U2) JTAG

(JP1)

I2C

(JP2)

DIPSW

PERST#

Status LED

X16 Connector(P5)

Lane1

Figure 3. RDK Architecture

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