II. GENERAL SYSTEM DESCRIPTION
Figure 1 is a block diagram of a typical acquisition system employing
this ADC. Figure 2 is a timing diagram showing the relative time scale
for the major signals involved in the analysis of an analog input.
Incident radiation at the detector is converted to an electrical signal
which is amplified and shaped by the amplifier. The output of the ampli-
fier connects to the ADC input where it triggers the ADC and starts con-
version of the analog input into a digital address. Once the ADC has
accepted a signal for conversion it is insensitive to other inputs until it
has been cleared (reset).
Briefly, conversion of the analog input is accomplished in the following
manner. The positive input pulse from the amplifier is applied to a stretcher
circuit which charges a capacitor to the peak amplitude of the input signal.
When the capacitor is fully charged a linear gate at the ADC input is closed,
blocking ADC response to any other input. At the same time a gate is opened
which allows 50 MHz clock pulses to start advancing a 10-bit scaler. Also
at this time logic circuits turn on a current source which linearly discharges
the stretcher capacitor back to zero. When the capacitor reaches zero the
50 MHz gate is closed and the 10-bit scaler contains a binary number whose
magnitude is directly proportional to the amplitude of the analog input pulse.
The binary number (address) is then presented to the memory unit for data
storage. When storage is complete the memory unit sends a clear signal to
the ADC. The clear signal resets the ADC, opens its linear gate; and the
ADC is available to convert another input.
The complete connection between ADC and memory unit consists of three
signals in addition to the 10-bit address. Signal STORE is generated approxi-
mately 1 usec after the ADC conversion is complete. The address is pre-
sented to the memory until 1 usec before STORE but presentation of an
address does not always mean it will be followed by a STORE. During the
1 usec, acceptance tests are performed on the address and only if these
tests are passed will a STORE follow 1 usec later. The tests performed
are: address underflow (address less than zero when using digital zero
offset), channel zero test (channel zero is reserved for live time and data
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