NEC MPD75512 Manual de usuario

DESCRIPTION

The

PD75512 is a 4-bit single-chip microcomputer which employs 75X series architecture, and its perform-

ance is comparable to that of an 8-bit microcomputer.

In addition to its high-speed processing capabilities, the

PD75512 is also capable of processing data in units

of 1, 4, or in 8-bits. With its internally provided A/D converter and serial interface, the

PD75512 provides the

highest performance in its class.

Detailed functions are described in the following user‘s manual. Be sure to read it for designing.

PD75516 User‘s Maual: IEM-5049

FEATURES

• Adequate I/O lines: 64

(can be provided pull-up/pull-down resistors: 47)

• Built-in 8-bit serial interface: 2-ch

NEC standard serial bus interface (SBI) internally provided

• Built-in 8-bit A/D converter: 8-ch

• Variable instruction execution time function which is convenient for high-speed operation and power saving

· 0.95

s/1.95

s/15.3

s (at 4.19 MHz operation),

· 122

s (at 32.768 kHz operation)

• Program memory (ROM) size: 12,160 ×8 bits

• Data memory (RAM) size: 512 ×4 bits

• High-performance timer function: 4-ch

· 8-bit timer/event counter

· Clock timer

· 8-bit basic interval timer

· Timer/pulse generator: Capable of outputting 14-bit PWM

• Clock operation for reduced power consumption possible

A TYP. at 3 V operation)

• PROM version (

PD75P516) available

APPLICATIONS

VCRs, CD players, telephones, cameras, etc.

NEC Corporation 1990

Document No. IC-2569D

(O. D. No. IC-7833E)

Date Published November 1993 P

Printed in Japan

DATA SHEET

MOS INTEGRATED CIRCUIT

PD75512

The information in this document is subject to change without notice.

4-BIT SINGLE-CHIP MICROCOMPUTER

The mark ★shows major revised points.

PD75512

ORDERING INFORMATION

Part Number Package Quality Grade

PD75512GF-xxx-3B9 80-pin plastic QFP Standard

(14 ×20mm)

Remarks: xxx is ROM code number.

Please refer to “Quality Grade on NEC Semiconductor Devices” (Document number IEI-1209) published by NEC

Corporation to know the specification of quality grade on the devices and its recommended applications.

PD75512 FUNCTIONS

Item Function

Internal ROM 12160 × 8 bits

Memory

Size RAM 512 × 4 bits

Genearl-Purpose Register (4 bits × 8 or 8 bits × 4) × 4 banks

Instruction Cycle • 0.95

s/1.91

s/15.3

s (Main system clock: at 4.19 MHz)

• 122

s (Subsystem clock: at 32.768 kHz)

Total 64 lines

CMOS Inputs 16 lines (also serve as INT, SIO, PPO, analog input; can be pulled up by software: 7

lines)

Input/

Output CMOS 28 lines (capable of driving LED: 4 lines)

Ports Input/Outputs • Can be pulled up by software: 16 lines

• Can be pulled down by mask option: 4 lines

N-ch Open-Drain 20 lines (capable of driving LED: 8 lines; 10 V withstand voltage; pins that can be

Input/Outputs pulled up by mask option: 20)

A/D Converter 8-bit resolution × 8 channels (successive approxmation type)

• Operation voltage: VDD = 3.5 to 6.0 V

• Timer/event counter

• Basic interval timer

• Timer/pulse generator (capable of outputting 14-bit PWM)

• Watch timer

• NEC standard serial bus interface (SBI)/3-line SIO: 1 channel

• Normal clock synchronized serial interface (3-line SIO): 1 channel

Vector Interrupt External: 3, Internal: 4

Test Input External: 1, Internal: 1

• Bit data set/reset/test/boolean operation instruction

Instruction Set • 4-bit data transfer/operation/increment/decrement /compare instructions

• 8-bit data transfer/operation/increment/decrement /compare instructions

• Ceramic/crystal oscillator for main system clock: 4.19 MHz

• Crystal oscillator for subsystem clock: 32.768 kHz

Operation Voltage VDD = 2.7 V to 6.0 V

Package 80-pin plastic QFP (14 ×20mm)

System Clock Generator













Timer/Counter 4 channels

Serial Interface 2 channels

PD75512

CONTENTS

1. PIN CONFIGURATION ..................................................................................................................... 5

2. TYPICAL SYSTEM CONFIGURATION ............................................................................................ 6

3. INTERNAL BLOCKDIAGRAM .......................................................................................................... 7

4. PIN FUNCTIONS .............................................................................................................................. 8

4.1 PORT PINS ............................................................................................................................................. 8

4.2 NON-PORT PINS ................................................................................................................................... 10

4.3 PIN INPUT/OUTPUT CIRCUITS ............................................................................................................ 11

4.4 RECOMMENDED CONDITIONS FOR UNUSED PINS.......................................................................... 14

4.5 MASK OPTION SELECTION ................................................................................................................. 15

5. MEMORY CONFIGURATION .......................................................................................................... 16

6. PERIPHERAL HARDWARE FUNCTIONS ........................................................................................ 19

6.1 PORT ...................................................................................................................................................... 19

6.2 CLOCK GENERATOR CIRCUIT ............................................................................................................. 20

6.3 CLOCK OUTPUT CIRCUIT..................................................................................................................... 21

6.4 BASIC INTERVAL TIMER ...................................................................................................................... 22

6.5 WATCH TIMER ...................................................................................................................................... 23

6.6 TIMER/EVENT COUNTER ..................................................................................................................... 23

6.7 TIMER/PULSE GENERATOR ................................................................................................................. 25

6.8 SERIAL INTERFACE............................................................................................................................... 26

6.9 A/D CONVERTER ................................................................................................................................... 30

6.10 BIT SEQUENTIAL BUFFER ................................................................................................................... 31

7. INTERRUPT FUNCTIONS ................................................................................................................ 31

8. STANDBY FUNCTIONS ................................................................................................................... 33

9. RESET FUNCTION ........................................................................................................................... 34

10. INSTRUCTION SET.......................................................................................................................... 36

11. ELECTRICAL SPECIFICATIONS....................................................................................................... 44

12. PERFORMANCE CURVES ............................................................................................................... 57

PD75512

13. PACKAGE DRAWINGS .................................................................................................................... 63

14. RECOMMENDED SOLDERING CONDITIONS................................................................................ 64

APPENDIX A. DEVELOPMENT TOOLS ................................................................................................ 65

APPENDIX B. RELATED DOCUMENTS ................................................................................................ 66

PD75512

1. PIN CONFIGURATION

AN0

PD75512GF– –3B9×××

AN4/P150

P120

AN1

2425 26

P93

27 28 29 30 31 32 33 34 35 36 37 38 39 40

AN2

AN3

AN5/P151

AN6/P152

AN7/P153

P121

P122

P123

P130

P131

P132

P133

REF

P113

P112

P111

P110

P103

P102

P101

P100

P92

P91

P90

SI1/P83

SO1/P82

SCK1/P81

PPO/P80

KR7/P73

KR6/P72

KR5/P71

KR4/P70

KR3/P63

KR2/P62

KR1/P61

KR0/P60

P53

P52

P51

P50

P43

P42

P41

P40

P33

P32

P31

P140

P141

P142

P143

RESET

XT2

XT1

P00/INT4

P01/SCK0

P02/SO0/SB0

P03/SI0/SB1

P10/INT0

P11/INT1

P12/INT2

P13/TI0

P20/PTO0

P21

P22/PCL

P23/BUZ

P30

79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

IC: Internally Connected (Connect directly to VSS)

*: Power must be supplied to both VDD pins.

PD75512

2. TYPICAL SYSTEM CONFIGURATION

VTR (Voltage synthesizer tuner)

PD75512

Remote control

Mechanism

Servo IC

INT0

Input port

Output

port

Mechanism

control

Mechanical

controller/

Timer

SIO

Analog

input

PPO

Key matrix

Port4, 5

KR0-KR7

SIO

OSD

LPF

FIP driver

Tuner

FIP

Clock for clock

System clock

PD75512

3. INTERNAL BLOCKDIAGRAM

PORT 0

PORT 1

PORT 2

PORT 3

PORT 4

PORT 5

PORT 6

PORT 7

PORT 8

PORT 9

PORT10

PORT11

PORT12

PORT13

PORT14

PORT15

P10-P13

P00-P03

4 P20-P23

4 P30-P33

4 P40-P43*

4 P50-P53*

4 P60-P63

4 P70-P73

P80-P83

4 P90-P93

4 P100-P103

4 P110-P113

4 P120-P123*

4 P130-P133*

4 P140-P143*

P150-P153

SP (8)

BANK

GENERAL REG.

ALU

PROGRAM

COUNTER (14)

ROM

PROGRAM

MEMORY

12160 ×8 BITS

DECODE

AND

CONTROL RAM

DATA MEMORY

512 x 4 BITS

TI0/P13 TIMER/EVENT

COUNTER

INTT0

PTO0/P20

BUZ/P23 WATCH

TIMER

INTW

INTCSI

SERIAL

INTERFACE0

SI0/SB1/P03

SO0/SB0/P02

SCK0/P01

INT0/P10

INT1/P11

INT2/P12

INT4/P00

KR0/P60

–KR7/P73

INTERRUPT

CONTROL

BIT SEQ.

BUFFER (16)

BASIC

INTERVAL

TIMER

INTBT

PPO/P80 TIMER/PULSE

GENERATOR

INTTPG

SERIAL

INTERFACE1

SI1/P83

SO1/P82

SCK1/P81

A/D

CONVERTER

REF

AN0-AN3

AN4

/P150-AN7/P15

f /2

RESET

PCL/P22 XT1 XT2 X1 X2

SUB MAIN

CLOCK

OUTPUT

CONTROL

CLOCK

DIVIDER

CLOCK

GENERATOR STAND BY

CONTROL CPU CLOCK

*: PORTs 4, 5, and 12 to 14 are 10 V middle voltage, N-ch open-drain input/output ports.

PD75512

4. PIN FUNCTIONS

4.1 PORT PINS (1/2)

Input/

Pin Input/ Shared Function 8-bit When Reset Output

Name Output Pin I/O Circuit

Type*1

P00 INT4 4-bit input port (PORT0). B

For P01 to P03, built-in pull-up

P01 SCK0 resistors can be specified in 3-bit F-A

Input units by software. x Input

P02 SO0/SB0 F-B

P03 SI0/SB1 M-C

P10 INT0 With noise

elimination function

P11 INT1

Input 4-bit input port (PORT1). x Input B-C

P12 INT2 Built-in pull-up resistors can be

specified by software in 4-bit units.

P13 TI0

P20 PTO0 4-bit input/output port (PORT2).

P21 Input/ — Built-in pull-up resistors can be

output specified by software in 4-bit units. x Input E-B

P22 PCL

P23 BUZ

P30*2— Programmable 4-bit input/output

port (PORT3).

P31*2Input/ — Input/output can be specified in

output bit units. x Input E-C

P32*2— Built-in pull-up resistors can be

specified by software in 4-bit unit.

P33*2—

N-ch open-drain 4-bit input/output High level

port (PORT4). (when pull-up

P40 to Input/ — A pull-up resistor can be provided resistor is M

P43*2output in bit units (mask option). provided) or

10V withstanding voltage in the high impedance

open-drain mode. O

N-ch open-drain 4-bit input/output High level

port (PORT5). (when pull-up

P50 to Input/ — A pull-up resistor can be provided resistor is M

P53*2output in bit units (mask option). provided) or

10V withstanding voltage in the high impedance

open-drain mode.

P60 KR0 Programmable 4-bit input/ output

port (PORT6).

P61 Input/ KR1 Input/output can be specified in

output bit units. O Input F-C

P62 KR2 Built-in pull-up resistors can be

specified by software in 4-bit units.

P63 KR3

*1: The number enclosed with a circle indicates Schmitt trigger input.

*2: Capable of direct driving on LED.

PD75512

4.1 PORT PINS (2/2)

Input/

Pin Input/ Shared Function 8-bit When Reset Output

Name Output Pin I/O Circuit

Type*1

P70 KR4 4-bit input/output port (PORT7).

P71 Input/ KR5 Built-in pull-up resistor can be

output specified in 4-bit units by software. O Input F-A

P72 KR6

P73 KR7

P80 PPO E

P81 SCK1 F

Input 4-bit input port (PORT8). x Input

P82 SO1 E

P83 SI1 B

Low level

4-bit input/output port (PORT9). (when pull-

P90 to Input/ — Built-in pull-up resistors can be x down resistor V

P93 output specified in bit units by mask is provided)

option. or high

impedance

P100 to Input/ — 4-bit input/output port (PORT10). Input E

P103 output x

P110 to Input/ — 4-bit input/output port (PORT11). Input E

P113 output

N-ch open-drain 4-bit input/output High level

port (PORT12). (when pull-up

P120 to Input/ — A pull-up resistor can be provided resistor is M

P123 output in bit units (mask option). x provided) or

10V withstanding voltage in the high impedance

open-drain mode.

N-ch open-drain 4-bit input/output High level

port (PORT13). (when pull-up

P130 to Input/ — A pull-up resistor can be provided x resistor is M

P133 output in bit units (mask option). provided) or

10V withstanding voltage in the high impedance

open-drain mode.

N-ch open-drain 4-bit input/output High level

port (PORT14). (when pull-up

P140 to Input/ — A pull-up resistor can be provided x resistor is M

P143 output in bit units (mask option). provided) or

10V withstanding voltage in the high impedance

open-drain mode.

P150 to Input AN4 to AN7 4-bit input port (PORT15). x Input Y-A

P153

*1: The number enclosed with a circle indicates Schmitt trigger input.

PD75512

XT2 —

4.2 NON-PORT PINS

Input/

Pin Input/ Shared Function When Reset Output

Name Output Pin Circuit

Type*

TI0 Input P13 The external event pulse input pin for the timer/ — B-C

event counter.

PTO0 Output P20 Timer/event counter output pin Input E-B

PCL Output P22 Clock output pin Input E-B

BUZ Output P23 Fixed frequency output pin (for buzzer output or Input E-B

system clock trimming)

SCK0 Input/ P01 Serial clock input/output pin output Input F-A

output

SO0/SB0 Input/ P02 Serial data output pin Input F-B

output Serial bus input/output pin

SI0/SB1 Input/ P03 Serial data input pin Input M-C

output Serial bus input/output pin

INT4 Input P00 Edge detection vector interrupt input pin (both — B

rising edge and falling edge detection)

INT0 P10 Edge detection vector Synchronized

interrupt input pin with clock

Input (detection edge selectable) — B-C

INT1 P11 Asynchronous

INT2 Input P12 Edge detection testable input Asynchronous — B-C

pin(rising edge detection)

KR0-KR3 Input P60-P63 Parallel falling edge detection testable input pin Input F-C

KR4-KR7 Input P70-P73 Parallel falling edge detection testable input pin Input F-A

SCK1 Input/ P81 Serial clock input/output pin Input F

output

SO1 Output P82 Serial data output pin Input E

SI1 Input P83 Serial data input pin Input B

AN0-AN3 — Y

Input A/D converter analog input pin —

AN4-AN7 P150-P153 Y-A

AVREF Input — A/C converter reference voltage input pin — Z

AVSS — — A/D converter reference ground pin — —

Pins for connecting the crystal ceramic oscillator

to the main system clock generator. When

X1, X2 Input — inputting the external clock, input the external — —

clock to pin X1, and the reverse phase of the

external clock to pin X2.

XT1 Input Pins for connecting the crystal oscillator to the

— subsystem clock generator. When the external — —

clock is used, inputs the external clock to pin

XT1. In this case, pin XT2 must be left open.

RESET Input — System reset input pin — B

PPO Output P80 Timer/pulse generator pulse output pin Input E

IC — — Internally Connected. Connect directly to VSS.——

VDD — — Positive power supply pin — —

VSS — — GND — —

*: The number enclosed with a circle indicates Schmidt trigger input.

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