National Semiconductor LMH1983 Manual de usuario

LMH1983 Evaluation Kit Users Guide

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LMH1983 Evaluation Kit Users Guide

Version 1.0

2/4/10

LMH1983 Evaluation Kit Users Guide

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INTRODUCTION

The LMH1983 Evaluation Kit (EVK) allows for the evaluation of the LMH1983

3G/HD/SD Video Clock Generator with Audio Clock. The LMH1983 device is

configured and controlled using National Semiconductor’s Analog Launch Pad (ALP)

software graphical user interface (GUI).

The GUI with the LMH1983 profile runs on Windows PC and can be used to program the

device’s control registers through the I2C interface. The Serial Peripheral Adapter (SPA)

board included in the kit provides I2C read/write control via the USB port of the PC with

the GUI. For more information about the GUI software and device register descriptions

and programming, please refer to the GUI software manual and LMH1983 datasheet.

Overview of LMH1983

The LMH1983 clock generator generates four video specific clocks. The device has four

PLLs in it.

PLL1 uses an external 27 MHz VCXO, and always generates a 27MHz reference

clock. This clock may be locked to an input reference which can be any of a

number of different types of reference – from video specific references to single

frequency reference signals.

PLL2 is dedicated to generating a 148.5 MHz clock (27 MHz * 5.5) , and is

locked to PLL1.

PLL3 is dedicated to generating a clock at 148.35 MHz (27 MHz * 5500/1001)

PLL4, by default is locked to PLL1, and generates a 24.576MHz clock which can

be used as an audio clock. PLL4 has a lot of versatility built in to it and can be

used for a broad variety of applications.

LMH1983 Evaluation Kit Users Guide

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LMH1983 EVALUATION BOARD OVERVIEW

The following block diagram shows an overview of the LMH1983 evaluation board and

general location of the main features, which will be discussed in the following sections of

this manual.

Applying power to the board:

The default configuration to apply power is to apply +5V across the top two pins on J8.

With a jumper on JP17, and on board LDO is used to generate the 3.3V rail that powers

the circuits on the evaluation board.

Alternately, JP17 may be removed, and a 3.3V rail may be applied directly to the bottom

two pins of J8.

LMH

1981

LMH1983

Quad

2:1

MUX

VCXO

3878

Power

Header

Analog

Ref. In BNC

Status LEDs

VCXO

LPF

CLKout1

SMA

CLKout4

SMAs

CLKout3

SMA

CLKout2

SMA

HVF

uts

Syncs

EXT.HVF

CLK

(VCXO

or SMA)

CLK In

SMA

Power LEDs

USB

Port

LMH1983 Evaluation Kit Users Guide

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Installing the software:

The evaluation kit contains a CD which has the control software on it. Running the

program on the CD will install the software on your computer.

Apply power to the Evaluation Board, and then attach a USB cable between the computer

and the board. Windows will recognize the board and pop up the

When this window comes up, select ‘No, not this time’ and ‘Next>’

LMH1983 Evaluation Kit Users Guide

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Select “Install from a list or specific location”

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LMH1983 Evaluation Kit Users Guide

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For the location, enter “C:\Program Files\National Semiconductor Corp\Analog

Launchpad Vxxx\DRIVERS” This directory was installed on your computer during the

ALP software installation.

The computer will warn you that the software has not passed Windows Logo Testing. Go

ahead and Continue Anyway.

The driver for the LMH1983 evaluation board will now be installed, and you can start the

ALP software.

When you start the Analog LaunchPAD software, it should recognize the evaluation

board and the screen will look like the figure below.

If the board is not connected properly, or not powered up, the ALP software will start up

in a demo mode which will look like the normal mode, but will not control the board.

Once the startup screen appears, click on the LMH1983 icon on the left side of the

window, and this will bring up the GUI:

LMH1983 Evaluation Kit Users Guide

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The status indications on the GUI are only updated when the Read Controls/Status button

is clicked. To have continuous updates, click the checkbox ‘Auto Refresh Status’, I also

like to check the ‘Perform ReadAll after write’ box – this will update all of the status

controls whenever something is written. In some cases, writing to one register will result

in multiple things changing, and checking this button will make sure that everything is

kept updated.

There are several panels in the GUI - the first is the main control panel and allows for

basic control over the board. Also very useful is the Registers tab, which will allow for

detailed manipulation of the various registers in the LMH1983.

LMH1983 Evaluation Kit Users Guide

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I2C SLAVE ADDRESS

The I2C address select jumper JP9 (3-way) can be configured as follows to select one of

the three I2C slave addresses offered by the LMH1983. The default for the board, and

for the ALP software is address ‘66h which corresponds to no jumper installed.

Table 1: LMH1983 I2C Slave Address Selection

7-bit I2C Slave Address JP1 Jumper Setting LMH1983 Address Input State

65’h (hex) Short Pins 1-2 Externally tied low

66’h Open Pins Internally biased to mid-supply

67’h Short Pins 2-3 Externally tied high

Observing the Outputs

The LMH1983 generates four clock signals (CLKout1, CLKout2, CLKout3, CLKout4)

and four timing signals (TOF1, TOF2, TOF3, TOF4). The LMH1983 outputs are

differential outputs, and can be observed directly at JP13, JP14, JP15 and JP16. There

are 100Ωtermination resistors situated near the connectors (R60,R66, R73 and R78). If

the differential signals are to be observed with a high impedance differential scope probe,

it can be attached directly to the pins. If it is desired that the differential outputs drive a

load, the load resistor should be moved to be adjacent to the final load. In addition to the

differential outputs, there are 50Ohm single ended outputs as well. These are provided

by using LMH0302 SDI cable drivers. On the initial version of the evaluation board

these outputs exhibit some undershoot and ringing at 4GHz which degrades the jitter

performance of these outputs.

Configuring the board for operation with an analog video

reference signal

The LMH1983 Evaluation board includes an LMH1981 sync separator which is able to

extract the timing signals from a broad range of analog sync signals. To use this feature,

install a jumper on JP4 (MUX ENABLE), and one on JP3 (Input Select). Supply the

reference signal to J1 (analog Ref In), and you can monitor the extracted H, V and F

signals at the yellow test points just to the left of the LMH1983.

The GUI will display what format is being detected under the PLL1

The LMH1983 can automatically detect and synchronize to the following reference input

formats received at its input pins:

HVF Sync timing from SMPTE standard video formats

o525i/29.97/30

o525p/59.94/60

LMH1983 Evaluation Kit Users Guide

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o625i/25

o625p/50

o720p/23.98/24/25/29.97/30/50/59.94/60

o1080i/25/29.97/30

o1080p/23.98/24/25/29.97/30/50/59.94/60

o1080pSf/23.98/24/25/29.97/30

Audio Word Clock

o32 kHz, 48 kHz, 96 kHz, 44.1 kHz

System Clock

o27 MHz

o10 MHz

Configuring the board for operation with a digital video

reference signal

An external digital reference signal, consisting of H,V and F may be applied to J2, a

jumper should installed on JP5, and the jumper on JP3 should be removed.

The GUI will display what format is being detected under the PLL1

For a comprehensive list of formats that can be detected, please refer to the LMH1983

datasheet. To determine format, the device measures the period of the Hsync input by

counting 27MHz clock pulses over several Hsync periods. There are some standards

where Hsync may be the same, in which case V and F are examined to determine if the

reference is an interlaced or progressive format before format detection is complete.

Configuring the board for operation in free-run mode, using

the on board reference oscillator

To operate the board in ‘stand-alone mode’, remove the jumper for JP3, make sure that

the jumper is removed from JP5, and in this mode, the frequency can be trimmed via R20

– the trim pot near the lower left corner of the board.

Configuring the board for operation, locked to an external

clock oscillator.

To operate the board locked to an external clock, supply the reference signal through the

SMA connector ‘J3’, remove the jumper form JP3 and install a jumper on JP5.

The automatic format detect algorithm in the LMH1983 will recognize reference clocks

of 27MHz or 10MHz. Other reference rates can be manually programmed.

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