Motorola MC68360 Manual de usuario

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Errata and Added Information to

MC68360 Quad Integrated Communication

Controller User's Manual Rev 1

MC68360



MOTOROLA, 1995

Microprocessor and Memory

Technologies Group

SEMICONDUCTOR PRODUCT INFORMATION

January 8, 1998

This document describes the latest information and changes to the first revision of the

MC68360 user’s manual.

Section 2 – Signal Descriptions

1. QUICC Functional Signal Groups.

On page 2-2, Figure 2-1, the signal names in the left column had a typo. The corrections for

the typo are in the right column.

As seen on page 2-2 Correction

A31-A27/WE3-WE0 A31-A27/WE0-WE3

SDACK2/L1TSYNCB/CTS3/PC8 SDACK2/L1TSYNCB/CTS3/PC8

L1RSYNB/CD3/PC9 L1RSYNB/CD3/PC9

SDACK1/L1TSYNCA/CTS4/PC10 SDACK1/L1TSYNCA/CTS4/PC10

L1RSYNCA/CD4/PC11 L1RSYNCA/CD4/PC11

2. Error on TRIS

On page 2-4, Table 2-1, the function description of TRIS stated that it is sampled during

system reset. This is not true. The TRIS signal is always sampled except during reset.

3. Missing Note.

On page 2-8, section 2.1.7.2 the following note should be added:

NOTE

User should note that the pin AVEC/IACK5 is always an open

drain output.

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2 MC68360 USER’S MANUAL ERRATA MOTOROLA

4. MC68040 Companion Mode Bus Cycle Note.

On page 2-14, section 2.2, add the following note after the second paragraph:

NOTE

In MC68040 companion mode, the QUICC understands

MC68040-type bus cycles but cannot generate them. If the

QUICC becomes busmaster, e. g. for SDMA transfers, it will

drive normal MC68030-type bus cycles with TT1 becoming DS

again. This should normally be no problem since the MC68040

does not interpret these input signals, but external circuitry han-

dling these signals must be aware of this fact.

Section 3 – Memory Map

1. Dual port RAM MAP

Onpage3-3,Table3-1indicatesthattheaddressrangeDPRBASE+700toDPRBASE+BFF

can be used for User data / BDs. This is not true. The address range 700-7FFF can be used

for User data / BDs but address range 800-BFFF is reserved.

2. Missing Underline in Table.

On pages 3-5 through 3-10, Tables 3-3 and 3-4, the following entries should have been

underlined.

RSR, CSR1, SDSR, CSR2, CIPR, CISR, TER1, TER2, TER3,

TER4, SCCE1, SCCE2, SCCE3, SCCE4, SMCE1, SMCE2,

SPIE

3. Missing Bold face in Table.

On pages 3-5 through 3-10, Tables 3-3 and 3-4, the following entries should have been in

bold face.

All entries in Table 3-3, ICCR, SDCR, PAPAR, PCPAR, TGCR,

RCCR, PBPAR.

Section 4 – Bus Operation

1. Byte Write Enable.

On page 4-5, section 4.1.8 the following sentences:

“The equations of the byte write enables for 32-bit port (16BM = 1) are as follows”

“The equations of the byte write enables for 16-bit port (B16M = 0) are as follows:”

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MOTOROLA MC68360 USER’S MANUAL ERRATA 3

are not correct, the correct text is below.

“The equations of the byte write enables for 32-bit port (DPS/SPS set to 32 bit) are as

follows:”

“The equations of the byte write enables for 16-bit port (DPS/SPS set to 16 bit) are as

follows:”

Also in the same section the first sentence of the note:

“Note that the WE signals are not affected by dynamic bus sizing.” is not correct and should

be removed.

2. Error in slave mode bus arbitration diagram.

On page 4-56, figure 4-38 an arrow head and text was missing.

The line top line between “QUICC waiting for bus, BR asserted” and “IDLE” state should

have an arrow head facing the IDLE state.

Also on the same figure, the Idle state should have a test of “BG Negated” under the text of

“BR Negated”.

3. Power on reset operation

On page 4-65, the note “User should make sure the ramp up time of Vcc never be faster

than 4mSec to ensure proper power on reset sequence. “This restriction has been removed

and the note should be deleted.

NOTE for Rev C.0

Due to a problem with Revision C.0 of the QUICC (masks

0E63C and 0F15W), a 4ms minimum Vcc ramp-up specification

was added. Characterization of Revision C.1 QUICCs (masks

1E68C and 0E68C) has demonstrated that this specification is

no longer necessary.

Users of Revision C.0 QUICCs should remain aware of this po-

tential problem source. Revision C.0 QUICCs used in systems

with very fast ramp-up times may experience problems at pow-

er-on reset. When the problem occurs, the QUICC never comes

out of reset and no bus activity occurs (similar to latch-up, but

without the high current drain). If the problem occurs, the only

solution is powering the device down and reapplying power (i.e.

another power-on reset).

Hardware reset (RESETH) will not solve the problem.

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4 MC68360 USER’S MANUAL ERRATA MOTOROLA

Section 5– CPU32+

1. Error in figure

On page 5-3, the data bus on figure 5-1 shows the data bus to be 16 bit. This is not correct,

the data bus on the QUICC™ is 32 bit wide.

Section 6 – System Integration Module

1. Added Information On Crystal Operation.

On page 6-13 the following sections should be added:

6.5.1.1 Using Oscillator as Input Clock

The preferred mode of operation of the 68360 is by driving the EXTAL pin with the output of

an oscillator. Oscillators are more costly than crystal circuits but are not subject to the same

sensitivity as crystal circuits. You have the choice of using a full speed oscillator (i.e. 25 MHz

oscillator) or using a lower speed oscillator such as 4 MHz or 32 kHz and having the system

frequency generated by the on-board PLL. Use of a lower speed oscillator will allow your

system to draw less power in a power-down mode.

NOTE

There are some limits to the speed of the oscillator that you can

use in certain situations. Please see Additional Information:

Phase Lock Loop for a description of these special situations.

6.5.1.2 Using Crystal as Input Clock

The 68360 has the ability to use a low speed crystal as its clock source. The on-chip PLL

can multiply the output of the crystal circuit up to the final system frequency. A crystal circuit

consists of a parallel resonant crystal, two capacitors, and two resistors. Example values for

both a 32kHz crystal and a 4MHz crystal are shown in Figures 6-6 and 6-6A. Note that these

are example values. Your circuit may require slightly different values to operate properly.

Crystals are typically much cheaper than similar speed oscillators. However, they may not

be as stable since they are affected by parameters such as: trace length, component quality,

board layout, 68360 package type, 68360 shrink level, etc. While crystal circuits are typically

stable, it is impossible to guarantee that they will remain stable due to 68360 process

changes or external component shifts.

NOTE

The internal frequency of the 68360 and the output of the CLKO

pins is dependent upon both the quality of the crystal circuit and

themultiplication factor (MF) used in the PLLCRregister.Please

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MOTOROLA MC68360 USER’S MANUAL ERRATA 5

see Additional Information: Phase Lock Loop for a description of

the PLL performance.

Also on page 6-14 the following figure should be added.

Figure 6-6A External Components for 4.192MHz

1. Missing Text.

On page 6-16, section 6.5.5.1, the following sentence should be added to the end of the

paragraph:

In the case where MODCK0-1 is 10, then SPCLK = EXTAL/128.

2. Error on Configuration Pins.

On page 6-19, Section 6.5.8, the last sentence states that the MODCK1-0 pins have an

internal pullup during reset. This is not correct and the sentence should be removed.

3. Missing Text.

On page 6-30, section 6.9.3.1, the note “SUPERVISOR ONLY” should appear below the

MCR register.

EXTAL

CRYSTAL

OSCILLATOR

XTAL XFC PIN VCCSYN

XFC

390nF

0.01 µF

0.1 µF

NOTE:

1. Must be low-leakage capacitor. See Section 10 Electrical Characteristics for recommended values.

2. Values are for

4.194MHz

crystal and may vary due to capacitance on PCB.

47pF 56pF

10 M

CLKO1

CLOCK

GENERATION CLKO2

VCCCLK

GNDCLK

0.1 µF

GNDSYN

VCCSYN

CRYSTAL 2

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6 MC68360 USER’S MANUAL ERRATA MOTOROLA

4. Typo on Reset Status Register.

On page 6-34, section 6.9.3.3, the 2nd bit of the register should be a reserved bit, not LOC.

Also the description of LOC in the following page should be removed.

5. Typo on SYPCR.

On page 6-35, section 6.9.3.5, the reset value for bits SWT1 and SWT0 were wrong. The

correct value for both bits is MODCK1.

6. Typo on PITR.

On page 6-36, section 6.9.3.7. The reset value for bits SWP and PTP were wrong. The

correct value for both bits is MODCK1.

7. Error in Text.

On page 6-36, section 6.9.3.5, the word EXTALDIV should be replaced with SPCLK.

8. Typo on Register Default.

On page 6-37, section 6.9.3.5, the description for DBFE and BME was not correct. The

correct descriptions are as follows:

DBFE—Double Bus Fault Monitor Enable

0 = Disable the double bus fault monitor function. (Default)

1 = Enable the double bus fault monitor function.

For more information, see 6.3.1.2.3 Double Bus Fault Monitor and Section 5 CPU32+.

BME—Bus Monitor External Enable

0 = Disable bus monitor function for the external bus cycles. (Default)

1 = Enable bus monitor function for the external bus cycles.

For more information see 6.3.1.2.1 Bus Monitor.

9. Typo on BKCR.

On page 6-47, section 6.9.3.13, the following statement, “NEG is ignored if the MA bits are

00" where NEG bit is described is not correct and should be removed.

10. Addition of note on External master support.

On page 6-57, section 6.11.7, the following note should be added after the first paragraph.

NOTE

The MC68EC040 and MC68040 type master is not supported

when the QUICC is configured to a master mode.

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MOTOROLA MC68360 USER’S MANUAL ERRATA 7

11. Corrections for RCNT—Refresh Counter Period Description.

On page 6-64, section 6.13.1, make the following corrections:

a) ‘RFCNT’ in the equation should be ‘RCNT’.

b) ‘24 (decimal)’ in the example should be ‘23 (decimal)’.

c) ‘24 / (25 MHz / 16)’ in the example should be ‘(23 + 1) / (25 MHz / 16)’.

12. Typo on Global Memory Register.

On page 6-65, section 6.13.1, the following should replace the definition of PGS2-PGS0:

PGS2–PGS0—Page Size

This attribute determines the page size and AMUX for the DRAM controller (see Table 6-

9). For multiplexing information see Table 6-8 on page 6-59. The page size is the smallest

DRAM size the user needs to support page mode capability.

Delay Write QUICC Bit Definition.

On page 6-66, section 6.13.1, the description of the DWQ bit was not clear. The bit definition

should be replaced as follows:

DWQ—Delay Write for QUICC (DRAM Bank Only)

This attribute is used to add a clock to the assertion and negation of the CAS signal on

DRAM page hit write cycles. The write cycle lasts one additional clock in this case. This

attribute is applicable to an internal QUICC master and to an external MC68030/QUICC.

0 = Reads and writes are the same length.

1 = Add one clock to write cycles for DRAM banks.

NOTE

This bit must be set by the user if page mode is enabled for this

DRAM bank (PGME = 1), and when a zero wait state DRAM is

implemented by setting TCYC to be zero. If this is not done the

DRAM may latch invalid data during writes.

Table 6-9. DRAM Page Size

DRAM Size PGS2-PGS0 Address Lines Compared

for Page Hit or Miss # Address/Page in Page Compare

128k 000 A10-25(32), A9-25(16) 256 Addresses

256k 001 A11-25(32), A10-25(16) 512 Addresses

512k 010 A11-25(32), A10-25(16) 512 Addresses

1M 011 A12-25(32), A11-25(16) 1024 Addresses

2M 100 A12-25(32), A11-25(16) 1024 Addresses

4M 101 A13-25(32), A12-25(16) 2048 Addresses

8M 110 A13-25(32), A12-25(16) 2048 Addresses

16M 111 A14-25(32), A13-25(16) 4096 Addresses

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8 MC68360 USER’S MANUAL ERRATA MOTOROLA

13. External MC040 type cycle (SRAM)

The following table should be placed after the table 6-11 on page 6-67.

14. Missing Note on Parity.

On page 6-71, section 6.13.3, the note below should be added after the note under the

definition of parity checking enable:

Parity is not supported with external assertion of DSACK or TA.

15. Error in note on CSNT40.

On page 6-72, the note on the top of the page states that SYNC bit must be set for CSNT40

function to take effect. This is not true. Regardless of the setting of SYNC bit CSNT40 will

take an effect.

16. Missing Statement on BACK40.

On page 6-72, the description of the BACK40, for the zero case, the following statement

should be added:

“The QUICC will assert TBI on an access to this memory area”.

17. Error in Note at TRLXQ.

On page 6-72, the 3rd note under TRLXQ-Timing Relax:

“User should avoid setting both TRLXQ and CSNTQ = 1, when TCYC = 0. This combination

will result in a bus cycle without CS assertion.” is not correct and should be removed.

18. Missing NOTE.

On page 6-74, bits 3 and 2 of the option register should have an asterisks. Also on the

bottom of the page the following note should be added.

External MC68040 Type bus

cycle Length

TCYC = TSS40=0 TSS40=1

023

134

245

356

467

578

689

…

15 17 18

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MOTOROLA MC68360 USER’S MANUAL ERRATA 9

NOTE

The default setting of bits 3 and 2 for option register 1 is deter-

mined by the settings of configuration pin.

19. Error in Table 6-14.

On page 6-77, The last column heading on Table 6-14 has an error. The heading should be:

“Number of clocks (DRAM)” not “Number of Wait States (DRAM)”

Section 7 – Communication Processor Module

1. Global advisory concerning Buffer Descriptor status bits.

The user is responsible for clearing (writing a zero) any buffer descriptor (RxBD or TxBD)

status bits set by the communication processor.

2. Deletion of STP bit.

On page 7-26, section 7.6.2.1. The STP bit in the ICCR was designed to conserve power

when IDMA was not in use. This function has been removed due to erratic behavior. The

user must keep this bit clear. Bit 15 of ICCR is now reserved.

3. Error in note.

On page 7-33, the note under section 7.6.3 Interface Signals should be as follows.

NOTE

DREQ must be level sensitive if IDMA uses buffer chaining or

auto buffer mode.

4. Wrong section number.

On page 7-34, the last sentence on the page "7.5.2.5 Timer Capture Register..." The section

was not correct. The correct section number is 7.6.2.5.

5. Wrong table reference.

On page 7-35, first sentence in section 7.6.4.2.1 reference, table 7-2. This should be table

7-3.

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10 MC68360 USER’S MANUAL ERRATA MOTOROLA

6. Error in sentence.

On page 7-40, Section 7.6.4.4.3 The last sentence in the first paragraph. " If DREQX is

negated long enough for the IDMA to win the bus, cycles will continue as long as DREQx is

asserted and no higher priority bus master or interrupt occurs." This sentence should be

replaced with. " If DREQX is asserted long enough for the IDMA to win the bus, cycles will

continue as long as DREQx is asserted and no higher priority bus master requests the bus

or interrupt occurs."

7. Missing paragraph in IDMA.

On page 7-41, section 7.6.4.4.3. The following paragraph should be added after point 6.

7. If the IDMA is being used in auto-buffer or buffer-chaining mode, the DREQ signal

will not be sampled at the S3 sampling time. It will be sampled after the RISC CP

has reconfigured the IDMA with the information contained in the next buffer de-

scriptor.Thus, you should continually assert DREQuntilyoureceivea DACK when

using buffer chaining mode or auto-buffer mode.

Also on page 7-43 the following paragraph should be added after point 3.

4. You may not use cycle steal mode if you are using buffer-chaining or auto-buffer

mode.

8. Error in example

On page 7-55, the third step in the buffer chaining example was printed incorrectly. The

correct step is as follows.

3. FCR1 = $89. Destination function code is 1000; Source function code is 1001.

9. Error in SDMA Bus Arbitration and Bus Transfers

On page 7-57, the first sentence of the last paragraph should read ‘…but the SDMA always

reads words (16 bits).’

10. Error in Programming the SI RAM Entries.

On page 7-72, section 7.8.4.5, the bit order of SSEL1-SSEL4 is not represented correctly.

The correct representation is as follows:

Bit 13 -> SSEL4

Bit 12 -> SSEL3

Bit 11 -> SSEL2

Bit 10 -> SSEL1

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