Microcomputer Systems MSI-P602 Manual de usuario
PC/104 Embedded
Industrial Analog I/O Series
Microcomputer Systems, Inc.
1814 Ryder Drive ¨Baton Rouge, LA 70808
Ph (225) 769-2154 ¨Fax (225) 769-2155
Email: [email protected]
http://www.microcomputersystems.com
MSI-P602 Trimble Lassen
iQ GPS & Digital I/O Card
Revision 2
User Manual
CONTENTS
I. INTRODUCTION 4
II.HARDWARE DESCRIPTION 6
A. CardConfiguration 6
B. Card Addressing 7
C. Interrupt Connections 8
D. Digital I/O Registers and Connections 10
E. 3.0V Battery 11
III. GPS SOFTWARE COMMANDS 12
A. Trimble Standard Interface Protocol (TSIP) 12
B. Trimble ASCII Interface Protocol (TAIP) 13
C. NMEA 0183 14
IV. SAMPLE BASIC LANGUAGE TEST PROGRAM 15
V. SPECIFICATIONS 19
APPENDIX
Schematic Diagrams of the MSI-P602 21
BLANKPAGE
Figure 1. Block Diagram of the MSI-P602.
I. INTRODUCTION
TheMSI-P602isalowcost,highperformanceglobalpositioning
system which uses the Trimble Lassen iQ module. It provides
12-channel GPS functionality that is fully compatible with
Trimble’spopularLassenSQmoduleusingTrimble’sFirstGPS®
architecturewhichdeliverscompleteposition,velocityandtime
(PVT) solutions for the host application. It features two GPS
signal sensitivity modes: Standard and Enhanced. With
Enhancedmodeenabled,themoduleautomaticallyswitchesto
higher sensitivity when satellite signals are weak. The module
alsosupportsTSIPdownloadofcriticalstartupinformationfor
fast acquisition. This aided GPS (A-GPS) startup provides hot
startperformanceforeachpower-up.Themodulesupportsthe
four most popular protocols: DGPS (RTCM), TSIP (Trimble
Standard Interface Protocol), TAIP (Trimble ASCII Interface
Protocol) and NMEA 0183 with an MTBF (mean time between
failures) figure of 60 years.
ThecardprovidestwoserialportsforprocessingtheGPSdata.
TheprimaryportgivesTSIPinputandoutputdataatadefault
BAUD rate of 9600. This port is also selectable for the TAIP
protocol.ThesecondaryportprovidesDGPS(RTCM)inputand
BLOCK DIAGRAM
PC/104 16-BIT STACKTHROUGH
CONNECTOR
ADDRESS
JUMPERS
3.0V
BATTERY
TRIMBLE iQ
GPS MODULE
POWER CONVERTER
& ANTENNA
DIGITAL I/O
4 TTL INPUTS
4 TTL OUTPUTS
UART 1
TSIP GPS DATA
I/O
MSI-P602
UART 2
TAIP/NMEA
GPS CONTROL
PC/104
BUS
INTERFACE
NETWORK
PC/104
BUS
INTERRUPT
NETWORK
INTERRUPT
JUMPERS
Page 4 MSI-P602 User Manual
Page 5 MSI-P602 User Manual
NMEA output at a default BAUD rate of 4800. Software
selectable NMEA protocols using the secondary serial port are
GGA (default), GLL, GSA, GSV, RMC, VTG (default) and ZDA.
Baud rates are selectable from 2400 to 38,400. The DGPS
protocol is RTCM SC-104.
The serial ports are standard IBM PC compatible UARTs. The
primary port is jumper selectable for COM1 or COM3 with an
optional 16-bit offset address. Similarly, the secondary port is
selectable at COM2 or COM4 with an optional 16-bit offset
address.
Atimemarkof1PPSisavailableasaninterruptorasinputinto
modemstatuslineDCDofthesecondaryUARTforsynchronizing
events. The primary and secondary UART interrupt are also
providedforallowinginterruptprocessingofGPSdata.Interrupts
are jumper selectable for IRQ3 thru IRQ7 and IRQ9, as
described in the next section.
Four TTL level digital inputs are provided by status lines CTS
and DSR of the primary and secondary UARTs. Four TTL level
outputs are provided by OUT1 and OUT2 of these UARTs.
The card is supplied with an active antenna having a 5 meter
(16.5 ft.) cable and a spacer kit. A sample test program is
supplied that illustrates programming of the UARTs for the
various protocols and data transfer rates. Operates from -40°
to 85° C.
II. HARDWARE DESCRIPTION
A.CardConfiguration
The MSI-P602 card is a CMOS design using through-hole and
surface-mounted devices. The card configuration is shown in
Figure 2 and a circuit diagram of the network is given in
Appendix B. The card contains two UARTS (U4 and U5) that
commnucatewith theGPSmodule. Connector J1providesfor
the digital I/O connections.
Jumper block JP1 for interrupt configuration (Pins 1 thru 12)
and JP2 is used for address selection (Pins 1 thru 14), as
described below.
Figure 2. MSI-P602 card outline.
Page 6 MSI-P602 User Manual
B.CardAddressing
The card address is set by installing appropriate jumper pairs
onJP2,pins1thru13,asshowninFig.3. Aninstalledjumper
foragivenaddressbitsetsthebitto1(true)andanuninstalled
jumper sets the bit equal to 0 (false).
AddressesA15thru A10 (JP2-1 thru 11) arejumperselectable
fordefiningthebaseaddressofthecardfrom0000HtoFC00H
on integral 10H boundaries, where H denotes a hexadecimal
number. Examples are as follow:
Example 1. Set a base address of 0000H.
No jumpers are installed for JP2-1 thru 11.
Example 2. Set a base address of 3800H.
Intall jumpers JP2-5, JP2-7 and JP2-9.
Jumper JP2-13 is used to select the port addresses of the
primaryandsecondaryUARTs,respectively.Thecardaddresses
fortheseselectionsaregiveninTableI. Itshouldbenotedthat
for a base address of zero, the addresses of the UARTs are the
standard serial port addresses for the IBM PC.
CAUTION: Make sure that the addresses you select for the
MSI-P602 are not in conflict with the serial ports of your CPU
card. For example, if your CPU uses COM1 and/or COM2,
o o o o o o o
o o o o o o o
1 A15
3 A14
5 A13
7 A12
9 A11
11 A10
13 COM1/COM2
Figure 3. Jumper block JP2 configuration.
Page 7 MSI-P602 User Manual
do not install JP2-13 so that COM3 and COM4 are selected for
the primary and secondary serial ports. If your CPU contains
COM1 thru COM4 ports and you are only using COM1 and
COM2, then disable COM3 and COM4 of the CPU card. If this
is not permissible, then you will have to select a base address
other than 0 by using jumpers for JP2-1 thru JP2-11. UART
addresses in this case are given in Table 1.
Table 1. Card UART Addresses for JP2-13 Selection.
Jumper JP2-13 Primary UART (U4) Secondary UART (U5)
Installed base address + COM1** base address + COM2
Uninstalled base address + COM3 base address + COM4
** COM1 = 3F8H
COM2 = 2F8H
COM3 = 3E8H
COM4 = 2E8H
where H denotes hexadecimal notational.
C.InterruptConnections
InterruptconnectionsareimplementedbyjumpersJP1-1thru
JP1-12. The steps in the procedure are as follows.
1) Odd numbered pins 1 thru 11 are connected to processor
interrupts IRQ9 thru IRQ3, as shown in Fig. 4. Wire-wrap
connections are necessary to select the desired interrupts as
described below.
2) JP1-2 is connected to the 1 PULSE/SEC output of the GPS
module for use in sychronizing data acquisitions. This can
jumpered to a desired interrupt, IRQ4 thru IRQ9, of JP1. The
signal is a tri-state gate which permits connecting multiple
sources to the same IRQx interrupt.
3) JP1-4 is connected to the interrupt request signal of the
primary UART (TSIP protocol). This can jumpered to a desired
interrupt,IRQ4 thru IRQ9, ofJP1.Thesignalis a tri-state gate
which permits connecting multiple sources to the same IRQx
interrupt.
Page 8 MSI-P602 User Manual
4) JP1-12 is connected to the interrupt request signal of the
secondary UART (TAIP/NMEA protocol). This can jumpered to
adesired interrupt, IRQ4 thru IRQ9,of JP1. The signal isa tri-
state gate which permits connecting multiple sources to the
same IRQx interrupt.
5) Three 1 KOhm pulldown resistors are available for use with
interrupts generated by 1 PPS and the serial ports. JP1-6,
JP1-8 and JP1-10 are connected to 1 KOhm resistors, as
shown in Fig. 4. These can be used to pulldown the IRQx
interrupts. The pulldown resistors and interrupts IRQx are
usually connected using wire-wrap connections. If no 1K
pulldownresistorisprovidedforagivenIRQxtobeused(either
bytheprocessorcardorbyanothercardinthesystemsharing
thisIRQx),thenoneoftheavailable1KpulldownsofJP1-6,etc.
should be interconnected with the interrupt source and the
chosen IRQx. For example, suppose the NMEA signal is to
interrupt the processor via IRQ5 and no 1K pulldown is
providedelsewhere.Awire-wrapchaincouldbeconnectedfrom
JP1-12 to JP1-8 to JP1-7.
o o o o o o
o o o o o o
IRQ9 1 2 1PPS
IRQ7 3 4 TSIP
IRQ6 5 6 1K Pulldown
IRQ5 7 8 1K Pulldown
IRQ4 9 10 1K Pulldown
IRQ3 11 12 NMEA
Figure 4. Interrupt jumper block JP1 configuration.
Page 9 MSI-P602 User Manual
D. DigitalI/ORegistersandConnections.
Four digital TTL inputs and four digital TTL outputs are
provided by the modem status and modem control registers of
UARTs U4 and U5. These I/O are connected to the card via J1
using a 16-pin flat cable connector. Register designations and
connector J1 pin assignments are given in Table 2. The inputs
and outputs on connector J1 are the inverted values of those
read or written in the modem status and control registers. For
example, a 1 written to OUT1 of U4 results in a 0 at J1-1
(OUT1_BUFFERED).Similarly,a1appliedtoJ1-9(IN1)results
in a 0 being read in CTS of U4.
Table 2. Digital I/O Register Designations and J1 Pin Assignments.
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
Name I/O UART Register J1 Pin*
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
OUT1_BUFFERED Output U4 (Primary) OUT1 1
OUT2 Output U4 (Primary) OUT2 3
OUT3 Output U5 (Secondary) OUT1 5
OUT4 Output U5 (Secondary) OUT2 7
IN1 Input U4 (Primary) CTS 9
IN2 Input U4 (Primary) DSR 11
IN3 Input U5 (Secondary) CTS 13
IN4 Input U5 (Secondary) DSR 15
−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−−
* J1 even numbered pins 2 thru 16 are ground.
Page 10 MSI-P602 User Manual
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