Lattice Semiconductor MIPI Manual de usuario

MIPI DSI to OpenLDI/FPD-Link/LVDS

Interface Bridge Soft IP

User Guide

FPGA-IPUG-02003 Version 1.2

November 2016

MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge Soft IP

User Guide

trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

2 FPGA-IPUG-02003-1.2

Contents

1. Introduction ..................................................................................................................................................................4

1.1. Quick Facts ..........................................................................................................................................................4

1.2. Features...............................................................................................................................................................5

1.3. Conventions.........................................................................................................................................................5

1.3.1. Nomenclature.................................................................................................................................................5

1.3.2. Data Ordering and Data Types .......................................................................................................................5

1.3.3. Signal Names ..................................................................................................................................................5

2. Functional Description ..................................................................................................................................................6

2.1. Top.......................................................................................................................................................................6

2.2. D-PHY Common Interface Wrapper ..................................................................................................................10

2.3. Rx Global Operations Controller .......................................................................................................................10

2.4. Capture Controller.............................................................................................................................................11

2.5. Byte2Pixel..........................................................................................................................................................12

2.6. Lane Distribution ...............................................................................................................................................12

2.7. LVDS Wrapper ...................................................................................................................................................12

2.8. Reset and Clocking ............................................................................................................................................13

3. Parameter Settings .....................................................................................................................................................15

4. IP Generation and Evaluation .....................................................................................................................................16

4.1. Licensing the IP..................................................................................................................................................16

4.2. Getting Started ..................................................................................................................................................16

4.3. Generating IP in Clarity Designer ......................................................................................................................17

4.4. Generated IP Directory Structure and Files.......................................................................................................20

4.5. Running Functional Simulation .........................................................................................................................21

4.6. Simulation Strategies ........................................................................................................................................23

4.7. Simulation Environment....................................................................................................................................23

4.8. Instantiating the IP ............................................................................................................................................24

4.9. Synthesizing and Implementing the IP ..............................................................................................................24

4.10. Hardware Evaluation .........................................................................................................................................25

4.10.1. Enabling Hardware Evaluation in Diamond ..................................................................................................25

4.11. Updating/Regenerating the IP...........................................................................................................................26

4.11.1. Regenerating an IP in Clarity Designer .........................................................................................................26

References ..........................................................................................................................................................................27

Technical Support Assistance .............................................................................................................................................27

Appendix A. Resource Utilization .......................................................................................................................................28

Appendix B. What is Not Supported ...................................................................................................................................29

Revision History ..................................................................................................................................................................30

MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge Soft IP

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FPGA-IPUG-02003-1.2 3

Figures

Figure 1.1. MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge System Diagram ............................................................4

Figure 2.1. MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP Block Diagram ...........................................................6

Figure 2.2. Single MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP (1:1) Block Diagram.........................................7

Figure 2.3. MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP (1:2, Split) Block Diagram ..........................................8

Figure 2.4. MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP (2:2) Block Diagram ...................................................8

Figure 2.5. High-Speed Data Transmission ...........................................................................................................................9

Figure 2.6. FPD-Link Transmit Interface Timing Diagram (RGB666) .....................................................................................9

Figure 2.7. FPD-Link Transmit Interface Timing Diagram (RGB888) .....................................................................................9

Figure 2.8. Single MIPI DSI to Dual FPD-Link (Split) Timing Diagram ..................................................................................10

Figure 2.9. MIPI D-PHY Clock Lane Module State Diagram ................................................................................................11

Figure 2.10. MIPI D-PHY Data Lane Module State Diagram ...............................................................................................11

Figure 4.1. Clarity Designer Window ..................................................................................................................................16

Figure 4.2. Starting Clarity Designer from Diamond Design Environment .........................................................................17

Figure 4.3. Configuring MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP in Clarity Designer................................18

Figure 4.4. Configuration Tab in IP GUI ..............................................................................................................................18

Figure 4.5. Video Tab in IP GUI ...........................................................................................................................................19

Figure 4.6. IP Directory Structure .......................................................................................................................................20

Figure 4.7. Simulation Environment Block Diagram ...........................................................................................................23

Figure 4.8. DSI Model Video Data.......................................................................................................................................24

Figure 4.9. Regenerating IP in Clarity Designer ..................................................................................................................26

Tables

Table 1.1. MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP Quick Facts .................................................................4

Table 2.1. MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP Pin Function Description ............................................6

Table 2.2. Capture Controller Outputs ...............................................................................................................................11

Table 2.3. Clock Frequency Calculations.............................................................................................................................13

Table 2.4. Supported Data Rates for MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP Configurations.................14

Table 3.1. MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP Parameter Settings ...................................................15

Table 4.1. Files Generated by Clarity Designer ...................................................................................................................20

Table 4.2. Testbench Directives..........................................................................................................................................21

Table 4.3. Testbench Directives for D-PHY Timing Parameters..........................................................................................22

Table 4.4. Testbench Directives for Reference Clock Period ..............................................................................................22

MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge Soft IP

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4 FPGA-IPUG-02003-1.2

1. Introduction

The Lattice Semiconductor MIPI®DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP with the Lattice Semiconductor

CrossLink™programmable device can translate DSI video streams from MIPI D-PHY interface to LVDS interface for an

FDP-Link connection to displays.

The Mobile Industry Processor Interface (MIPI) provides specifications for standardization in consumer mobile devices.

MIPI Display Serial Interface (DSI) and MIPI D-PHY specifications were developed to create a standardized interface for

all displays used in the mobile industry. As the industry evolves, bandwidth requirements have exceeded what display

manufacturers are capable of manufacturing, while application processor vendors can provide very fast interfacing

capabilities. For a cost effective solution, displays can be replaced with newer display, and the processor can be

retained. Low Voltage Differential Signaling (LVDS) interface has become popular to support fast data rates of video

transmission for Flat Panel Display Link (FPD-Link) connections.

Application

Processor

DCK

MIPI DSI LVDS

DCK0

D[0:3]

D0-D3 DCK1

D[4:7]

Figure 1.1. MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge System Diagram

1.1. Quick Facts

Table 1.1 provides quick facts about the MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP for CrossLink device.

Table 1.1. MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP Quick Facts

MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP Configuration

Single MIPI DSI to Single FPD-Link

(RX_GEAR=8, RGB888, HS_LP)

Dual MIPI DSI to Dual FPD-Link

(RX_GEAR=16, RGB888, HS_LP)

Core Requirements

FPGA Families Supported

CrossLink

Resource

Utilization

Targeted Device

LIF-MD6000-6MG81I

Data Path Width

32 bits total for 4 lanes

64 bits total for 4 lanes

LUTs

863

3367

sysMEM™EBRs

Registers

779

2636

Programmable IOs

Hard D-PHY

Design Tool

Support

Lattice Implementation

Lattice Diamond®3.8

Synthesis

Lattice Synthesis Engine

Synopsys®Synplify Pro®L-2016.03L

Simulation

Aldec®Active-HDL™10.3 Lattice Edition

MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge Soft IP

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FPGA-IPUG-02003-1.2 5

1.2. Features

The key features of the MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP are:

Compliant with MIPI D-PHY v1.1, MIPI DSI v1.1 and Open LVDS Display Interface (OpenLDI) v0.95 specifications

Supports MIPI DSI interfacing from 160 Mb/s up to 1.5 Gb/s

Supports 1:1, 1:2 (split) and 2:2 MIPI DSI to FPD-Link configurations

Supports 4 data lanes and one clock lane per MIPI DSI interface

Supports continuous and non-continuous MIPI D-PHY clock

Supports common MIPI DSI compatible video formats (RGB888, RGB666)

Supports MIPI DSI Video Mode operation of Non-Burst Mode with Sync Pulses

Supports dedicated EoT short packet (EoTp)

Transmits in OpenLDI unbalanced operating mode format

1.3. Conventions

1.3.1. Nomenclature

The nomenclature used in this document is based on Verilog HDL. This includes radix indications and logical operators.

1.3.2. Data Ordering and Data Types

The highest bit within a data bus is the most significant bit.

Single-bit data stream from each MIPI DSI data lane is deserialized into 8-bit or 16-bit parallel data where bit 0 is

the first received bit. The size of parallel data depends on the Rx gear setting (RX_GEAR).

Pixel data order before distribution to LVDS lanes is {Red[MSB:0], Green[MSB:0], Blue[MSB:0]}. One, two or four

pixels may be sent for distribution to LVDS lanes in one pixel clock cycle depending on number of Tx channels and

Tx gear setting (TX_GEAR). If there are multiple pixels per clock cycle, the pixel in the lower bits is the first received

pixel. For instance, the pixel order for 4 pixels per clock is {pixel3, pixel2, pixel1, pixel0} where pixel0 is received

first and pixel3 is received last.

Pixel data is transmitted over LVDS lanes according to OpenLDI 18-bit and 24-bit unbalanced operating mode

format.

1.3.3. Signal Names

Signal names that end with:

“_n” are active low

“_i” are input signals

Some signals are declared as bidirectional (IO) but are only used as input hence “_i” identifier is used.

“_o” are output signals

Some signals are declared as bidirectional (IO) but are only used as output hence “_o” identifier is used.

MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge Soft IP

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6 FPGA-IPUG-02003-1.2

2. Functional Description

The MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP serves as a bridge between a MIPI DSI host and a display

device.

2.1. Top

Figure 2.1 shows the MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP block diagram.

reset_n_i

clk_ref_i

clk_ch0_p_i

clk_ch0_n_i

d0_ch0_p_i

d0_ch0_n_i

d1_ch0_p_i

d1_ch0_n_i

d2_ch0_p_i

d2_ch0_n_i

d3_ch0_p_i

d3_ch0_n_i

clk_ch1_p_i

clk_ch1_n_i

d0_ch1_p_i

d0_ch1_n_i

d1_ch1_p_i

d1_ch1_n_i

d2_ch1_p_i

d2_ch1_n_i

d3_ch1_p_i

d3_ch1_n_i

clk_ch0_p_o

clk_ch0_n_o

d0_ch0_p_o

d0_ch0_n_o

d1_ch0_p_o

d1_ch0_n_o

d2_ch0_p_o

d2_ch0_n_o

d3_ch0_p_o

d3_ch0_n_o

clk_ch1_p_o

clk_ch1_n_o

d0_ch1_p_o

d0_ch1_n_o

d1_ch1_p_o

d1_ch1_n_o

d2_ch1_p_o

d2_ch1_n_o

d3_ch1_p_o

d3_ch1_n_o

lock_pll_o

pll_lol_o

ready_o

Figure 2.1. MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP Block Diagram

Table 2.1. MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP Pin Function Description

Port Name

Direction

Function Description

Clock and Reset

clk_ref_i

Reference clock for internal PLL. Available only when MIPI D-PHY clock is non-

continuous

reset_n_i

Asynchronous system reset (active low)

MIPI DSI Interface

clk_ch0_p_i, clk_ch0_n_i

MIPI D-PHY channel 0 clock lane

d0_ch0_p_i, d0_ch0_n_i

MIPI D-PHY channel 0 data lane 0

d1_ch0_p_i, d1_ch0_n_i

MIPI D-PHY channel 0 data lane 1

d2_ ch0_p_i, d2_ ch0_n_i

MIPI D-PHY channel 0 data lane 2

d3_ ch0_p_i, d3_ ch0_n_i

MIPI D-PHY channel 0 data lane 3

clk_ch1_p_i, clk_ch1_n_i

MIPI D-PHY channel 1 clock lane

d0_ch1_p_i, d0_ch1_n_i

MIPI D-PHY channel 1 data lane 0. Available only for configurations with two Rx

channels

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FPGA-IPUG-02003-1.2 7

Table 2.1. MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP Pin Function Description (Continued)

Port Name

Direction

Function description

d1_ch1_p_i, d1_ch1_n_i

MIPI D-PHY channel 1 data lane 1. Available only for configurations with two Rx

channels

d2_ ch1_p_i, d2_ ch1_n_i

MIPI D-PHY channel 1 data lane 2. Available only for configurations with two Rx

channels

d3_ ch1_p_i, d3_ ch1_n_i

MIPI D-PHY channel 1 data lane 3. Available only for configurations with two Rx

channels

FPD-Link Interface

clk_ch0_p_o, clk_ch0_n_o

LVDS channel 0 clock lane

d0_ch0_p_o, d0_ch0_n_o

LVDS channel 0 data lane 0

d1_ch0_p_o, d1_ch0_n_o

LVDS channel 0 data lane 1

d2_ ch0_p_o, d2_ ch0_n_o

LVDS channel 0 data lane 2

d3_ ch0_p_o, d3_ ch0_n_o

LVDS channel 0 data lane 3. Available only for configurations with RGB888 data

type

clk_ch1_p_o, clk_ch1_n_o

LVDS channel 1 clock lane

d0_ch1_p_o, d0_ch1_n_o

LVDS channel 1 data lane 0. Available only for configurations with two Tx

channels

d1_ch1_p_o, d1_ch1_n_o

LVDS channel 1 data lane 1. Available only for configurations with two Tx

channels

d2_ ch1_p_o, d2_ ch1_n_o

LVDS channel 1 data lane 2. Available only for configurations with two Tx

channels

d3_ ch1_p_o, d3_ ch1_n_o

LVDS channel 1 data lane 3. Available only for configurations with two Tx

channels and RGB888 data type

Miscellaneous Status Signals

lock_pll_o

PLL lock (active high). Available only when miscellaneous status signals option

is enabled

pll_lol_o

PLL loss of lock (active high). Available only when miscellaneous status signals

option is enabled

ready_o

Indicates reset sequence of DDR components is complete (active high).

Available only when miscellaneous status signals option is enabled

Figure 2.2 shows the single MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP (1:1) block diagram.

DPHY Common Interface

Wrapper

Hard

DPHY

RX Global

Operations

Controller

LP HS

Controller

Capture

Controller

Byte2Pixel

FIFO

PLL

clk_ch0_p_i

clk_ch0_n_i

clk_byte_fr from DPHY

clk_pixel_i

vsync_o

hsync_o

de_o

Pixel data

clk_ref_i

clk_byte_fr from

DPHY

d0_ch0_p_i

d0_ch0_n_i

d1_ch0_p_i

d1_ch0_n_i

d2_ch0_p_i

d2_ch0_n_i

d3_ch0_p_i

d3_ch0_n_i

Lane Distr

p_odd_o

LVDS

Wrapper

clk_ch0_p_o

clk_ch0_n_o

d0_ch0_p_o

d0_ch0_n_o

d1_ch0_p_o

d1_ch0_n_o

d2_ch0_p_o

d2_ch0_n_o

d3_ch0_p_o

d3_ch0_n_o

OSC

clk_lp_ctrl

eclk

clk_ref_i

clk_byte_fr from

DPHY

clk_ref_i

clk_byte_fr from

DPHY

Figure 2.2. Single MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP (1:1) Block Diagram

MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge Soft IP

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8 FPGA-IPUG-02003-1.2

Figure 2.3 shows the MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP (1:2, Split) block diagram.

DPHY Common Interface

Wrapper

Hard

DPHY

RX Global

Operations

Controller

LP HS

Controller

Capture

Controller

Byte2Pixel

FIFO

PLL

clk_byte_fr from DPHY

clk_pixel_i

clk_byte_fr

from PLL

vsync_o

hsync_o

de_o

Pixel data

clk_ref_i

clk_byte_fr from

DPHY

Lane Distr

p_odd_o

LVDS

Wrapper

clk_ch0_p_o

clk_ch0_n_o

d0_ch0_p_o

d0_ch0_n_o

d1_ch0_p_o

d1_ch0_n_o

d2_ch0_p_o

d2_ch0_n_o

d3_ch0_p_o

d3_ch0_n_o

OSC

clk_lp_ctrl

eclk

clk_ch0_p_i

clk_ch0_n_i

d0_ch0_p_i

d0_ch0_n_i

d1_ch0_p_i

d1_ch0_n_i

d2_ch0_p_i

d2_ch0_n_i

d3_ch0_p_i

d3_ch0_n_i

clk_ref_i

clk_byte_fr from

DPHY

clk_ref_i

clk_byte_fr from

DPHY

clk_ch1_p_o

clk_ch1_n_o

d0_ch1_p_o

d0_ch1_n_o

d1_ch1_p_o

d1_ch1_n_o

d2_ch1_p_o

d2_ch1_n_o

d3_ch1_p_o

d3_ch1_n_o

Figure 2.3. MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP (1:2, Split) Block Diagram

Figure 2.4 shows the MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP (2:2) block diagram.

DPHY Common Interface

Wrapper

Hard

DPHY

RX Global

Operations

Controller

LP HS

Controller

Capture

Controller

Byte2Pixel

FIFO

PLL

clk_ch0_p_i

clk_ch0_n_i

clk_byte_fr from DPHY

clk_pixel_i

(channel 0)

vsync_o

hsync_o

de_o

Pixel data

clk_ref_i

clk_byte_fr from

DPHY channel 0

d0_ch0_p_i

d0_ch0_n_i

d1_ch0_p_i

d1_ch0_n_i

d2_ch0_p_i

d2_ch0_n_i

d3_ch0_p_i

d3_ch0_n_i

Lane Distr

p_odd_o

LVDS

Wrapper

clk_ch0_p_o

clk_ch0_n_o

d0_ch0_p_o

d0_ch0_n_o

d1_ch0_p_o

d1_ch0_n_o

d2_ch0_p_o

d2_ch0_n_o

d3_ch0_p_o

d3_ch0_n_o

OSC

clk_lp_ctrl

eclk

DPHY Common Interface

Wrapper

Hard

DPHY

Capture

Controller

Byte2Pixel

FIFO

clk_ch1_p_i

clk_ch1_n_i

vsync_o

hsync_o

de_o

Pixel data

d0_ch1_p_i

d0_ch1_n_i

d1_ch1_p_i

d1_ch1_n_i

d2_ch1_p_i

d2_ch1_n_i

d3_ch1_p_i

d3_ch1_n_i

Lane Distr

p_odd_o

LVDS

Wrapper

clk_ch1_p_o

clk_ch1_n_o

d0_ch1_p_o

d0_ch1_n_o

d1_ch1_p_o

d1_ch1_n_o

d2_ch1_p_o

d2_ch1_n_o

d3_ch1_p_o

d3_ch1_n_o

clk_byte_fr clk_byte_fr

clk_pixel_i

(channel 1)

clk_ref_i

clk_byte_fr from

DPHY channel 0

clk_ref_i

clk_byte_fr from

DPHY channel 0

Figure 2.4. MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge IP (2:2) Block Diagram

The MIPI DSI receive interface has one MIPI D-PHY clock lane and four MIPI D-PHY data lanes. The clock lane is center-

aligned to the data lanes. The clock lane can either be continuous (high speed only, HS_ONLY) or non-continuous

(HS_LP).

When the clock lane is non-continuous, proper transition from low power (LP) to high speed (HS) mode of clock lane is

required. The data lanes also require proper transition from LP to HS modes. In HS mode, data stream from each data

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FPGA-IPUG-02003-1.2 9

lane is deserialized to byte data. The deserialization is done with 1:8 gearing or 1:16 gearing depending on Rx gear

setting (RX_GEAR). The byte data is word-aligned based on the SoT Sync sequence defined in the MIPI D-PHY

Specification version 1.1.

Figure 2.5. High-Speed Data Transmission

RGB data and control signals extracted from DSI packets are transmitted over FPD-Link interface such that output is

compliant to OpenLDI unbalanced format as shown in Figure 2.6 –Figure 2.8. Control signals include data enable (DE),

vertical and horizontal sync flags (VSYNC and HSYNC). Reserved bits (RES) are tied to 0.

VSYNC HSYNCDE VSYNC HSYNCDE

Current Cycle Next Cycle

clk_ch0_p_o

d0_ch0_p_o

d1_ch0_p_o

d2_ch0_p_o

Figure 2.6. FPD-Link Transmit Interface Timing Diagram (RGB666)

VSYNC HSYNCDE VSYNC HSYNCDE

Current Cycle Next Cycle

RES RESR6R7G6G7B6B7 R6R7G6G7B6B7

clk_ch0_p_o

d0_ch0_p_o

d1_ch0_p_o

d2_ch0_p_o

d3_ch0_p_o

Figure 2.7. FPD-Link Transmit Interface Timing Diagram (RGB888)

MIPI DSI to OpenLDI/FPD-Link/LVDS Interface Bridge Soft IP

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10 FPGA-IPUG-02003-1.2

VSYNC HSYNCDE VSYNC HSYNCDE

Current Cycle Next Cycle

RES RESR6R7G6G7B6B7 R6R7G6G7B6B7

clk_ch0_p_o

d0_ch0_p_o

d1_ch0_p_o

d2_ch0_p_o

d3_ch0_p_o

VSYNC HSYNCDE VSYNC HSYNCDE

RES RESR6R7G6G7B6B7 R6R7G6G7B6B7

clk_ch1_p_o

d0_ch1_p_o

d1_ch1_p_o

d2_ch1_p_o

d3_ch1_p_o

1st pixel received

2nd pixel received

3rd pixel received

4th pixel received

Figure 2.8. Single MIPI DSI to Dual FPD-Link (Split) Timing Diagram

Each data lane is serialized using ODDRx7 or ODDRx14 primitive, depending on Tx gear setting (TX_GEAR). RGB888

requires 4 data lanes while RGB666 requires 3 data lanes only. The clock lane is generated by feeding constant

“1100011” or “11000111100011” to another ODDRx7 or ODDRx14, respectively. The clock is edge-aligned against data.

Seven bits of data are transmitted in one clock cycle. When TX_GEAR is 14, the first pixel received is transmitted first

and the second pixel received is transmitted in the next clock cycle.

In single MIPI DSI to dual FPD-Link configuration, the incoming packets are split into the two channels in an alternate

manner. The first pixel received is transmitted over LVDS channel 0 while the next pixel received is transmitted over

LVDS channel 1 at the same clock cycle as shown in Figure 2.8. The same approach is implemented regardless of

TX_GEAR setting.

The dual MIPI DSI to dual FPD-Link configuration is two instances of single MIPI DSI to single FPD-Link that share the

same clocks. When MIPI D-PHY clock is continuous, the continuous byte clock from Rx channel 0 is used.

2.2. D-PHY Common Interface Wrapper

When two Rx channels are enabled, each channel has its own D-PHY common interface wrapper. This block instantiates

and configures hard D-PHY IP to receive MIPI D-PHY high-speed data from all enabled data lanes. The hard D-PHY IP

outputs 8-bit or 16-bit parallel data in non-continuous byte clock domain for each data lane. Size of parallel data

depends on Rx gear setting (RX_GEAR).

Byte data are transferred to continuous byte clock domain using multicycle registers. Data enable signal from this block

becomes active when SoT Sync is successfully detected by hard D-PHY IP from all enabled data lanes and becomes

inactive when MIPI D-PHY data lanes go to Stop state (LP11).

2.3. Rx Global Operations Controller

When two Rx channels are enabled, each channel has its own Rx global operations controller. This block controls the

high-speed termination enable of MIPI D-PHY clock and data lanes. When MIPI D-PHY clock is continuous, the HS

termination enable of clock lane is tied to VCC. When MIPI D-PHY clock is non-continuous, the HS termination enable of

clock lane becomes active after proper LP to HS transition is observed. Oscillator clock is used for this function. The

required LP to HS transition on clock lane is shown in Figure 2.9 as per MIPI D-PHY Specification version 1.1.

Tabla de contenidos

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