Lattice Semiconductor ECP5 Versa Manual de instrucciones

ECP5 and ECP5-5G High-Speed I/O Interface

Technical Note

FPGA-TN-02035-1.3

October 2020

ECP5 and ECP5-5G High-Speed I/O Interface

Technical Note

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

2 FPGA-TN-02035-1.3

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document is proprietary to Lattice Semiconductor, and Lattice reserves the right to make any changes to the information in this document or to any

products at any time without notice.

 ECP5 and ECP5-5G High-Speed I/O Interface 
 Technical Note 
 
© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. 
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 
FPGA-TN-02035-1.3 3 
Contents 
Acronyms in This Document.................................................................................................................................................9 
Introduction................................................................................................................................................................10 
External Interface Description....................................................................................................................................10 
High-Speed I/O Interface Building Blocks...................................................................................................................11 
1. Edge Clocks........................................................................................................................................................11 
2. Primary Clocks...................................................................................................................................................11 
3. DQS Lane...........................................................................................................................................................11 
4. PLL .....................................................................................................................................................................12 
5. DDRDLL..............................................................................................................................................................12 
6. DQSBUF.............................................................................................................................................................12 
7. DLLDEL...............................................................................................................................................................13 
8. Input DDR (IDDR)...............................................................................................................................................13 
9. Output DDR (ODDR)..........................................................................................................................................13 
10. Edge Clock Dividers (CLKDIV) ............................................................................................................................13 
11. Input/Output DELAY..........................................................................................................................................13 
Building Generic High Speed Interfaces .....................................................................................................................14 
1. Types of High-Speed DDR Interfaces.................................................................................................................14 
High-Speed DDR Interface Details ..............................................................................................................................15 
1. GDDRX1_RX.SCLK.Centered..............................................................................................................................15 
2. GDDRX1_RX.SCLK.Aligned.................................................................................................................................16 
3. GDDRX2_RX.ECLK.Centered..............................................................................................................................17 
4. GDDRX2_RX.ECLK.Aligned.................................................................................................................................18 
5. GDDRX2_RX.MIPI ..............................................................................................................................................20 
6. GDDRX71_RX.ECLK............................................................................................................................................21 
7. GDDRX1_TX.SCLK.Aligned.................................................................................................................................22 
8. GDDRX1_TX.SCLK.Centered ..............................................................................................................................22 
9. GDDRX2_TX.ECLK.Aligned.................................................................................................................................23 
10. GDDRX2_TX.ECLK.Centered ..............................................................................................................................24 
11. GDDRX71_TX.ECLK............................................................................................................................................25 
12. Generic DDR Design Guidelines ........................................................................................................................25 
12.1. Using the High Speed Edge Clock Bridge......................................................................................................25 
12.2. Receive Interface Guidelines........................................................................................................................26 
12.3. Transmit interface Guidelines ......................................................................................................................26 
12.4. Clocking Guidelines for Generic DDR Interface............................................................................................26 
13. Timing Analysis for High Speed DDR Interfaces ................................................................................................27 
13.1. Frequency Constraints..................................................................................................................................27 
13.2. DDR Input Setup and Hold Time Constraints ...............................................................................................27 
13.3. DDR Clock to Out Constraints for Transmit Interfaces.................................................................................28 
ECP5 and ECP5-5G Memory Interfaces ......................................................................................................................31 
1. DDR Memory Interface Requirements..............................................................................................................33 
2. Features for Memory Interface Implementation..............................................................................................34 
2.1. DQS Grouping...............................................................................................................................................34 
2.2. DLL-Compensated DQS Delay Elements.......................................................................................................35 
2.3. Data Valid Module........................................................................................................................................35 
2.4. READ Pulse Positioning Optimization...........................................................................................................36 
2.5. Dynamic Margin Control on DQSBUF...........................................................................................................38 
2.6. Read Data Clock Domain Transfer Using Input FIFO ....................................................................................38 
2.7. DDR Input and Output Registers (IDDR/ODDR)............................................................................................38 
3. Memory Interface Implementation ..................................................................................................................38 
3.1. Read Implementation...................................................................................................................................38 
3.2. Write Implementation (DQ, DQS, and DM)..................................................................................................40 
3.3. Write Implementation (DDR2, DDR3/DDR3L Address, Command, and Clock) ............................................41 

ECP5 and ECP5-5G High-Speed I/O Interface 
Technical Note 
 
© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. 
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 
FPGA-TN-02035-1.3 
3.4. Write Implementation (LPDDR2 and LPDDR3 Address, Command, and Clock) ...........................................42 
4. DDR Memory Interface Design Rules and Guidelines .......................................................................................44 
5. DDR2/DDR3 Memory Interface Termination Guidelines ..................................................................................45 
5.1. Termination for DQ, DQS, and DM...............................................................................................................45 
5.2. Termination for CK .......................................................................................................................................45 
5.3. Termination for Address, Commands, and Controls ....................................................................................46 
5.4. Termination for DDR3/DDR3L DIMM ...........................................................................................................46 
6. DDR Memory Interface Pinout Guidelines ........................................................................................................46 
7. Pin Placement Considerations for Improved Noise Immunity ..........................................................................47 
Using Clarity Designer to Build and Plan High Speed DDR Interfaces.........................................................................49 
1. Configuring DDR Modules in Clarity Designer...................................................................................................50 
2. Configuring SDR Modules..................................................................................................................................50 
3. Configuring DDR Generic modules....................................................................................................................53 
4. Configuring 7:1 LVDS Interface Modules...........................................................................................................57 
5. Configuring DDR Memory Interfaces ................................................................................................................58 
6. Building DDR Interfaces in Clarity Designer ......................................................................................................62 
7. Planning DDR Interfaces in Clarity Designer......................................................................................................63 
DDR Software Primitives and Attributes.....................................................................................................................64 
1. Input/Output DELAY..........................................................................................................................................64 
2. DELAYF...............................................................................................................................................................65 
3. DELAYG..............................................................................................................................................................65 
4. DELAY Attribute Description .............................................................................................................................66 
5. DDRDLL (Master DLL) ........................................................................................................................................66 
5.1. DDRDLLA.......................................................................................................................................................66 
6. DLL Delay (DLLDEL)............................................................................................................................................67 
7. Generic DDR Input and Output Primitives ........................................................................................................68 
8. Input DDR Primitives .........................................................................................................................................68 
8.1. IDDRX1F........................................................................................................................................................68 
8.2. IDDRX2F........................................................................................................................................................69 
8.3. IDDR71B........................................................................................................................................................69 
9. Output DDR Primitives ......................................................................................................................................70 
9.1. ODDRX1F ......................................................................................................................................................70 
9.2. ODDRX2F ......................................................................................................................................................70 
9.3. ODDR71B......................................................................................................................................................71 
10. Memory DDR Primitives....................................................................................................................................71 
10.1. DQSBUF (DQS Strobe Control Block)............................................................................................................71 
10.2. DQSBUFM.....................................................................................................................................................72 
11. Input and Output Memory DDR Primitives.......................................................................................................73 
12. Memory Input DDR Primitives...........................................................................................................................74 
12.1. IDDRX2DQA ..................................................................................................................................................74 
13. Memory Output DDR Primitives for DQ Output................................................................................................75 
13.1. ODDRX2DQA.................................................................................................................................................75 
14. Memory Output DDR Primitives for DQS Output..............................................................................................75 
14.1. ODDRX2DQSB...............................................................................................................................................75 
15. Memory Output DDR Primitives for Tristate Output Control ...........................................................................76 
15.1. TSHX2DQA....................................................................................................................................................76 
15.2. TSHX2DQSA ..................................................................................................................................................76 
16. Memory Output DDR Primitives for Address and Command............................................................................77 
16.1. OSHX2A.........................................................................................................................................................77 
Soft IP Modules...........................................................................................................................................................78 
1. Detailed Description of Each Soft IP..................................................................................................................78 
1.1. GDDR_SYNC..................................................................................................................................................78 
1.2. RX_SYNC .......................................................................................................................................................79 
1.3. MEM_SYNC...................................................................................................................................................80 

ECP5 and ECP5-5G High-Speed I/O Interface

Technical Note

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-TN-02035-1.3 5

9.1.4. BW_ALIGN....................................................................................................................................................80

9.1.5. MIPI_FILTER..................................................................................................................................................81

Technical Support Assistance .............................................................................................................................................83

Revision History..................................................................................................................................................................84

ECP5 and ECP5-5G High-Speed I/O Interface 
Technical Note 
 
© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. 
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 
6 FPGA-TN-02035-1.3 
Figures 
Figure 2.1. External Interface Definitions ...........................................................................................................................10 
Figure 3.1. ECP5 and ECP5-5G Device Clocking Diagram....................................................................................................11 
Figure 3.2. DDRDLL Connectivity ........................................................................................................................................12 
Figure 5.1. GDDRX1_RX.SCLK.Centered Interface (Static Delay) ........................................................................................15 
Figure 5.2. GDDRX1_RX.SCLK.Centered Interface (Dynamic Data Delay)...........................................................................15 
Figure 5.3. GDDRX1_RX.SCLK.Aligned Interface (Static Delay)...........................................................................................16 
Figure 5.4. GDDRX1_RX.SCLK.Aligned Interface (Dynamic Data/Clock Delay) ...................................................................17 
Figure 5.5. GDDRX2_RX.ECLK.Centered Interface (Static Delay)........................................................................................18 
Figure 5.6. GDDRX2_RX.ECLK.Centered Interface (Dynamic Data Delay)...........................................................................18 
Figure 5.7. GDDRX2_RX.ECLK.Aligned Interface (Static Delay)...........................................................................................19 
Figure 5.8. GDDRX2_RX.ECLK.Aligned Interface (Dynamic Data/Clock Delay) ...................................................................19 
Figure 5.9. GDDRX2_RX.MIPI..............................................................................................................................................20 
Figure 5.10. GDDRX71_RX.ECLK Interface ..........................................................................................................................21 
Figure 5.11. GDDRX1_TX.SCLK.Aligned Interface ...............................................................................................................22 
Figure 5.12. GDDRX1_TX.SCLK.Centered Interface.............................................................................................................23 
Figure 5.13. GDDRX2_TX.ECLK.Aligned Interface ...............................................................................................................23 
Figure 5.14. GDDRX2_TX.ECLK.Centered Interface ............................................................................................................24 
Figure 5.15. GDDRX71_TX.ECLK Interface ..........................................................................................................................25 
Figure 5.16. RX Centered Interface Timing.........................................................................................................................27 
Figure 5.17. RX Aligned Interface Timing............................................................................................................................28 
Figure 5.18. tCO Min and Max Timing Analysis ..................................................................................................................29 
Figure 5.19. Transmit Centered Interface Timing...............................................................................................................29 
Figure 5.20. Transmit Aligned Interface Timing..................................................................................................................30 
Figure 6.1. Typical DDR2/DDR3/DDR3L Memory Interface................................................................................................31 
Figure 6.2. Typical LPDDR2/LPDDR3 Memory Interface.....................................................................................................32 
Figure 6.3. DQ-DQS During Read ........................................................................................................................................32 
Figure 6.4. DQ-DQS During Write .......................................................................................................................................32 
Figure 6.5. DQ-DQS Grouping.............................................................................................................................................34 
Figure 6.6. DQSBUF Block Functions...................................................................................................................................35 
Figure 6.7. READ Signal Training Process............................................................................................................................37 
Figure 6.8. DDR2, DDR3/DDR3L, LPDDR2, and LPDDR3 Read Side Implementation ..........................................................39 
Figure 6.9. DDR2, DDR3/DDR3L, LPDDR2, and LPDDR3 Write Side (DQ, DQS, and DM) ....................................................40 
Figure 6.10. DDR2, DDR3/DDR3L Address, Command, and Clock Generation ...................................................................41 
Figure 6.11. LPDDR2 Output for CA Generation.................................................................................................................42 
Figure 6.12. LPDDR2 Output for CSN, CKE, and CLOCK Generation ...................................................................................43 
Figure 6.13. LPDDR3 Output Side for CA Generation .........................................................................................................43 
Figure 6.14. LPDDR3 Output Side for CSN, CKE, ODT, and CLOCK Generation...................................................................44 
Figure 7.1. Clarity Design Main Window.............................................................................................................................49 
Figure 7.2. SDR Option Selected in the Catalog Tab of Clarity Designer.............................................................................50 
Figure 7.3. SDR Configuration Tab......................................................................................................................................51 
Figure 7.4. DDR_Generic Option Selected in the Catalog Tab of Clarity Designer..............................................................53 
Figure 7.5. DDR_Generic Pre-Configuration Tab ................................................................................................................53 
Figure 7.6. DDR_Generic Configuration Tab.......................................................................................................................54 
Figure 7.7. GDDR_7:1 Option Selected in the Catalog Tab of Clarity Designer ..................................................................57 
Figure 7.8. GDDR_7:1 LVDS Configuration Tab...................................................................................................................57 
Figure 7.9. DDR_MEM Option Selected in the Catalog Tab of Clarity Designer .................................................................58 
Figure 7.10. DDR_MEM Configuration Tab.........................................................................................................................59 
Figure 7.11. DDR_MEM Clock/Address/Command Tab......................................................................................................61 
Figure 7.12. DDR_MEM Advanced Settings Tab.................................................................................................................62 
Figure 7.13. DDR Modules Paced Using Clarity Design Planner..........................................................................................63 
Figure 8.1. DELAYF Primitive...............................................................................................................................................65 
Figure 8.2. DELAYG Primitive ..............................................................................................................................................65 

 ECP5 and ECP5-5G High-Speed I/O Interface 
 Technical Note 
 
© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. 
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 
FPGA-TN-02035-1.3 7 
Figure 8.3. DDRDLLA Primitive............................................................................................................................................66 
Figure 8.4. DLLDELD Primitive ............................................................................................................................................67 
Figure 8.5. IDDDRX1F Primitive ..........................................................................................................................................68 
Figure 8.6. IDDRX2F Primitive.............................................................................................................................................69 
Figure 8.7. IDDR71B............................................................................................................................................................69 
Figure 8.8. ODDRX1F...........................................................................................................................................................70 
Figure 8.9. ODDRX2F...........................................................................................................................................................70 
Figure 8.10. ODDR71B Primitive.........................................................................................................................................71 
Figure 8.11. DQSBUFM Primitive........................................................................................................................................72 
Figure 8.12. IDDRX2DQA Primitive .....................................................................................................................................74 
Figure 8.13. ODDRX2DQA...................................................................................................................................................75 
Figure 8.14. ODDRX2DQSB Primitive..................................................................................................................................75 
Figure 8.15. TSHX2DQA Primitive.......................................................................................................................................76 
Figure 8.16. TSHX2DQSA Primitive .....................................................................................................................................76 
Figure 8.17. OSHX2A Primitive ...........................................................................................................................................77 
Figure 9.1. GDDR_SYNC Ports.............................................................................................................................................78 
Figure 9.2. RX_SYNC Ports ..................................................................................................................................................79 
Figure 9.3. MEM_SYNC Ports..............................................................................................................................................80 
Figure 9.4. BW_ALIGN Ports...............................................................................................................................................80 
Figure 9.5. MIPI_FILTER Ports.............................................................................................................................................81 

ECP5 and ECP5-5G High-Speed I/O Interface 
Technical Note 
 
© 2014-2020 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are as listed at www.latticesemi.com/legal. 
All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. 
8 FPGA-TN-02035-1.3 
Tables 
Table 4.1. Generic High-Speed I/O DDR Interfaces.............................................................................................................14 
Table 6.1. DDR Memory Configurations Support ...............................................................................................................33 
Table 6.2. DDRDLL Connectivity..........................................................................................................................................35 
Table 6.3. DDRDLL Connectivity..........................................................................................................................................36 
Table 6.4. I/O Standards for DDR Memory.........................................................................................................................45 
Table 7.1. SDR Configuration Parameters...........................................................................................................................52 
Table 7.2. DDR_Generic Pre-Configuration Parameters.....................................................................................................54 
Table 7.3. DDR_Generic Configuration Tab Parameters.....................................................................................................55 
Table 7.4. Clarity Designer DDR_Generic Interface Selection ............................................................................................56 
Table 7.5. GDDR_7:1 LVDS Configuration Parameters .......................................................................................................58 
Table 7.6. DDR_MEM Configuration Tab Parameters ........................................................................................................60 
Table 7.7. DDR_MEM Clock/Address/Command Parameters ............................................................................................61 
Table 7.8. DDR_MEM Advanced Settings Tab Parameters.................................................................................................62 
Table 8.1. Software Primitives............................................................................................................................................64 
Table 8.2. DELAYF Port List .................................................................................................................................................65 
Table 8.3. DELAYG Port List.................................................................................................................................................65 
Table 8.4. DELAYF and DELAYG Attributes..........................................................................................................................66 
Table 8.5. DDRDLLA Port List ..............................................................................................................................................67 
Table 8.6. DDRDLL Attributes .............................................................................................................................................67 
Table 8.7. DLLDELD Port List...............................................................................................................................................67 
Table 8.8. DLLDELD Attributes............................................................................................................................................68 
Table 8.9. IDDRX1F Port List ...............................................................................................................................................68 
Table 8.10. IDDRX2F Port List .............................................................................................................................................69 
Table 8.11. IDDRX2F Port List .............................................................................................................................................69 
Table 8.12. ODDRX1F Port List............................................................................................................................................70 
Table 8.13. ODDRX2F Port List............................................................................................................................................70 
Table 8.14. ODDR71B Port List ...........................................................................................................................................71 
Table 8.15. DQSBUF Port List..............................................................................................................................................72 
Table 8.16. DQSBUFM Attributes .......................................................................................................................................73 
Table 8.17. Summary of all DDR Memory Primitives..........................................................................................................73 
Table 8.18. DQSBUF Port List..............................................................................................................................................74 
Table 8.19. Memory Primitive Attributes ...........................................................................................................................74 
Table 8.20. ODDRX2DQA Port List ......................................................................................................................................75 
Table 8.21. ODDRX2DQA Port List ......................................................................................................................................76 
Table 8.22. TSHX2DQA Port List..........................................................................................................................................76 
Table 8.23. TSHX2DQSA Port List........................................................................................................................................77 
Table 8.24. OSHX2A Port List..............................................................................................................................................77 
Table 9.1. List of Soft IPs supported ...................................................................................................................................78 
Table 9.2. Soft IP Used in Each Interface ............................................................................................................................78 
Table 9.3. GDDR_SYNC Port List description ......................................................................................................................79 
Table 9.4. GDDR_SYNC Port List description ......................................................................................................................79 
Table 9.5. MEM_SYNC Port Description .............................................................................................................................80 
Table 9.6. BW_ALIGN Port Description...............................................................................................................................81 
Table 9.7. MIPI_FILTER Port Description ............................................................................................................................82 

ECP5 and ECP5-5G High-Speed I/O Interface

Technical Note

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

FPGA-TN-02035-1.3 9

Acronyms in This Document

A list of acronyms used in this document.

Acronym

Definition

CLKDIV

Edge Clock Dividers

DDR

Double Data Rate

DLL

Delay-Locked Loops

Data Mask

DSP

Digital Signal Processing

IDDR

Input DDR

ECLK

Edge Clock

ODDR

Output DDR

PCB

Printed Circuit Board

PCLK

Primary Clock

PIO

Programmable I/O

SDR

Single Data Rate

SSN

Simultaneous Switching Noise

ECP5 and ECP5-5G High-Speed I/O Interface

Technical Note

All other brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.

10 FPGA-TN-02035-1.3

1. Introduction

The ECP5™ and ECP5-5G™ devices support high-speed I/O interfaces, including Double Data Rate (DDR) and Single Data

Rate (SDR) interfaces, using the logic built into the Programmable I/O (PIO). SDR applications capture data on one edge

of a clock while DDR interfaces capture data on both the rising and falling edges of the clock, thus doubling the

performance. ECP5 and ECP5-5G device I/O also have dedicated circuitry that is used along with the DDR I/O to support

DDR2, DDR3, DDR3L, LPDDR2, and LPDDR3 SDRAM memory interfaces.

This document discusses how to utilize the capabilities of the ECP5 and ECP5-5G devices to implement high-speed

generic DDR interface and the DDR memory interfaces. Refer to the Implementing DDR Memory Interfaces section of

this document for more information.

2. External Interface Description

This technical note uses two types of external interface definitions, centered and aligned. A centered external interface

means that, at the device pins, the clock is centered in the data opening. An aligned external interface means that, at

the device pins, the clock and data transition are aligned. This is also sometimes called edge-on-edge.

Figure 2.1 shows the external interface waveform for SDR and DDR.

Figure 2.1. External Interface Definitions

The interfaces described are referenced as centered or aligned interfaces. An aligned interface needs to adjust the

clock location to satisfy the capture flip-flop setup and hold times. A centered interface needs to balance the clock and

data delay to the first flip-flop to maintain the setup and hold already provided.

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