Intersil ISL97676IRZ Manual de usuario

Application Note 1568

ISL97676IRZ-EVAL Quick Start Guide

This quick start guide pertains to the ISL97676IRZ-EVAL.

This board comes populated with 72 LED’s in a 6P12S

configuration to simplify evaluation and testing.

1. Apply input voltage to the VIN and GND post on the

top left corner of the evaluation board.

2. Apply a 100% duty-cycle PWM signal to PWM (J13)

and GND post.

3. Insert WR jumper.

4. To power-up the evaluation board in 6P12S

configuration, make sure jumpers JP8-14 are

inserted.

5. To power-up in 6P10S configuration, jumpers JP15-20

should be inserted.

6. Jumper JP5 should be inserted in the lower position.

See Figure 1.

7. Jumper J12 should be inserted in the top position.

See Figure 1.

8. LED current can be programmed by connecting a

current meter across J8 and varying R12.

ILED = 724/R12

The measured current divided by 6 is the LED current per

channel. For example, 120mA measured current will

correspond to 20mA/channel.

9. Floating jumper JP7 will provide direct PWM mode

such that the dimming frequency follows the input

PWM signal without frequency modulation. See

ISL97676 data sheet for more details (FN7600).

Note that equal phase shift feature is disabled in this

mode.

10.Inserting JP7 allows the dimming frequency to be

programmed with a resistor, R12 to GND. The

dimming frequency is calculated by Equation 1:

11.Switches SW1 and SW2 are used to program the

switching frequency and enable the equal phase

shift feature per Table 1. For additional information,

please consult the ISL97676 data sheet.

12.After following Steps 1 through 9, all 72 LEDs should

light up at 100% duty-cycle or full brightness.

13.Jumper JP1 can be inserted if the external fault

MOSFET Q1 is not used. See data sheet for

additional information.

14.Jumpers JP4, JP3, JP30 and the 10-pin white

connector in the bottom left are not used.

The ISL97676 evaluation board schematic and top and

bottom silkscreen layers are shown in Figures 2 through 4.

FIGURE 1. ISL97676 EVALUATION BOARD

FPWM 6.67 10^7×RFPWM⁄=(EQ. 1)

TABLE 1.

SW2 SW1

Up Up FSW = 1.2MHz, Equal Phase Shift Enabled

Up Down FSW = 570kHz, No Phase Shift

Down Up FSW = 1.2MHz, No Phase Shift

Down Down FSW = 570kHz, Equal Phase Shift Enabled

CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.

1-888-INTERSIL or 1-888-468-3774 |Intersil (and design) is a registered trademark of Intersil Americas Inc.

All other trademarks mentioned are the property of their respective owners.

July 15, 2010

AN1568.0

Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the

reader is cautioned to verify that the Application Note or Technical Brief is current before proceeding.

For information regarding Intersil Corporation and its products, see www.intersil.com

July 15, 2010

AN1568.0

Title

Size:

Date:

Revision:

Sheet of

Title

Size:

Date:

Revision:

Sheet of

FAULT

VIN

FSW

VDDIO

COMP

PWM

RFPWM/Direct PWM

GND 9

FB1 12

FB2 11

FB3 10

FB4 8

FB5 7

FB6 6

OVP 14

ISET

FPO

PGND 15

LX 16

ISL97676

SS25

R15

10K

R14

358K

C10

100pF/50V

C11

360nF

4.7uF/50V

LED1

LED2

LED3

LED4

LED5

LED6

LED7

LED8

LED9

LED10

LED11

LED12

LED13

LED26

LED25

LED24

LED23

LED22

LED21

LED20

LED19

LED18

LED17

LED16

LED15

LED14

LED27

LED28

LED29

LED30

LED31

LED32

JP9 JP10 JP11 JP12

LED33

LED34

LED35

LED36

LED37

LED38

LED39

LED52

JP13

LED51

LED50

LED49

LED48

LED47

LED46

LED45

LED44

JP14

LED55

LED56

LED57

LED58

LED59

LED60

LED61

LED62

LED64

LED65

LED78

LED77

LED76

LED75

LED74

LED73

LED43

LED42

LED41

LED40

LED53

LED63

LED72

LED54

LED71

LED70

LED69

LED68

LED67

LED66

JP16 JP17 JP18 JP19 JP20JP15

C15

4.7nF C14

4.7nF C13

4.7nF C12

4.7nF

C16

4.7nF

C17

4.7nF

J14

Vout JP8

JP24

JP23

JP22

JP21

JP25 JP26 JP27 JP28 JP29

R12

50K

0.1uF/50V

J1(Vin)

VIN= 4.75 ~26V

JP1

10uF/50V

FDMA530PZ

10uH

R11

Open

1uF/50V

R5 150K

100K

3.3nF

10k C5

390pf

J13

PWM

FAULT

8-13-2009

C18

Open

R16

Open

R17

Open

JP7

J5 J6

J6 J7

J7 J8

J8 J9

FB1

TP1

FB2

TP2

FB3

TP3

FB4

TP4

FB5

TP5

FB6

TP6

J2 (VLogic)

Vlogic

HDR1

HEADER10(FMale)

JP3

JP4

J10

SDA

J11

SCL

R10

R13

SW2

SPDT

2SW1 SPDT

J12

SW1 SW2

1.2MHZ _ No Phase Shift

1.2MHZ _ with Phase Shift

600KHZ _ with Ph ase Shift

600KHZ _ No Phase Shift

Position Selecting

4.7K

R18

100

SCL

SDA

JP30

JP5

FIGURE 2. ISL97676 EVALUATION BOARD SCHEMATIC

Application Note 1568

3July 15, 2010

AN1568.0

FIGURE 3. EVALUATION BOARD TOP LAYER

Application Note 1568

4July 15, 2010

AN1568.0

FIGURE 4. EVALUATION BOARD BOTTOM LAYER

Application Note 1568

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