Intel SL7PG - Xeon 3.4 GHz/800MHz/1MB Cache CPU... Manual de usuario

64-bit Intel®Xeon®Processor

with 800 MHz System Bus (1 MB

and 2 MB L2 Cache Versions)

Specification Update

June 2006

Document Number: 302402-022

Notice: The 64-bit Intel®Xeon®processor with 800 MHz system bus (1 MB and 2 MB L2 cache

versions) may contain design defects or errors known as errata which may cause the product to

deviate from published specifications. Current characterized errata are documented in this

specification update.

264-bit Intel®Xeon®Processor with 800 MHz System Bus

(1 MB and 2 MB L2 Cache Versions) Specification Update

INFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL®PRODUCTS. EXCEPT AS PROVIDED IN INTEL'S TERMS

AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS ANY EXPRESS

OR IMPLIED WARRANTY RELATING TO SALE AND/OR USE OF INTEL PRODUCTS, INCLUDING LIABILITY OR WARRANTIES RELATING TO

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INTELLECTUAL PROPERTY RIGHT.

Intel products are not intended for use in medical, life saving, life sustaining, critical control or safety systems, or in nuclear facility applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Intel, the Intellogo, Pentium, Pentium III Xeon, Celeron, Intel NetBurst and Intel Xeon are trademarks or registered trademarks of Intel Corporation or

its subsidiaries in the United States and other countries.

*Other names and brands may be claimed as the property of others.

64-bit Intel®Xeon®Processor with 800 MHz System Bus 3

(1 MB and 2 MB L2 Cache Versions) Specification Update

Contents

Revision History .................................................................................................................5

Preface...............................................................................................................................6

Identification Information....................................................................................................7

Summary Table of Changes.............................................................................................12

Errata................................................................................................................................19

Specification Changes......................................................................................................44

Specification Clarifications ...............................................................................................45

Documentation Changes..................................................................................................46

464-bit Intel®Xeon®Processor with 800 MHz System Bus

(1 MB and 2 MB L2 Cache Versions) Specification Update

64-bit Intel®Xeon®Processor with 800 MHz System Bus 5

(1 MB and 2 MB L2 Cache Versions) Specification Update

Revision History

Version Description Date

-001 • Initial release of the document. July 2004

-002 • Removed erratum P18 and renumbered existing errata. July 2004

-003 • Added errata S32-S35. Renamed errata numbering from P to S. August 2004

-004 • Removed erratum S29 and renumbered existing errata.

• Added errata S35-S65.

• Added E0 step processor information to Table 1, “Identification

Information”.

• Added new notes to Table 2, “64-bit Intel® Xeon® Processor with 800

MHz System Bus (1 MB and 2 MB L2 Cache Versions) Identification

Information” and deleted unnecessary notes.

• Added Table 3, “DP Platform Population Matrix for the 64-bit Intel®

Xeon® Processor with 800 MHz System Bus (1 MB and 2 MB L2

Cache Versions) FC-PGA4 Package”.

September 2004

-005 • Added errata S66-S73. October 2004

-006 • Updated S-Spec table, code key, and mixed steppings statement to

include Low Voltage Intel® Xeon® processor

• Added errata S74-S75.

November 2004

-007 • Updated erratum S26. Added errata S76and S77. December 2004

-008 • Added errata S78-S79; added additional text to “Mixed Steppings In

DP Systems” chapter. January 2005

-009 • Added 2 MB L2 cache version of the 64-bit Intel® Xeon® processor

with 800 MHz system bus; added errata S80-S81; added S-spec

numbers SL7ZC, SL7ZD, SL7ZE, and SL7ZF to Table 2.

February 2005

-010 • Updated errata S28 and S53; updated summary table entries for S19

and S43. March 2005

-011 • Updated Table 2; added erratum S82; updated plans column for

erratum S27; added Specification Clarification 1. April 2005

-012 • Updated steppings affected for erratum S27. May 2005

-013 • Updated Table 2. June 2005

-014 • Added erratum S83. Updated relevant document lists. July 2005

-015 • Updated summary table entry for S19. Added erratum S84. August 2005

-016 • Added errata S85 and S86. Added S-spec numbers to Table 2. Added

R-0 stepping to summary table of changes. Updated summary table

entries. Removed duplicate erratum S33.

September 2005

-017 • Added erratum S87. Updated letters in Codes used in Summary

Table. Corrected S-spec notes for 3.40 GHz entries. October 2005

-018 • Added errata S88 and S89. Updated steppings affected for S22.

Updated Mixed Steppings in DP Systems section. November 2005

-019 • Added erratum S90. December 2005

-020 • Added erratum S91. Updated erratum S17. January 2006

-021 • Added erratum S1S and S92. May 2006

-022 • Added erratum S93. June 2006

664-bit Intel®Xeon®Processor with 800 MHz System Bus

(1 MB and 2 MB L2 Cache Versions) Specification Update

Preface

This document is an update to the specifications contained in the following documents:

1. 64-bit Intel®Xeon®Processor with 2 MB L2 Cache Datasheet (Document Number 306249)

Link: http://developer/design/xeon/datashts/306249.htm

2. Intel®Xeon®Processor with 800 MHz System Bus Datasheet (Document Number 302355)

Link: http://developer/design/xeon/datashts/302355.htm

This document is intended for hardware system manufacturers and software developers of

applications, operating systems, or tools.

Nomenclature

S-Spec Number is a five-digit code used to identify products. Products are differentiated by their

unique characteristics, e.g., core speed, L2 cache size, package type, etc. as described in the

processor identification information table. Care should be taken to read all notes associated with

each S-Spec number.

Errata are design defects or errors. Errata may cause the processor’s behavior to deviate from

published specifications. Hardware and software designed to be used with any given processor

must assume that all errata documented for that processor are present on all devices unless

otherwise noted.

Specification Changes are modifications to the current published specifications. These changes

will be incorporated in the next release of the specifications.

Specification Clarifications describe a specification in greater detail or further highlight a

specification’s impact to a complex design situation. These clarifications will be incorporated in

the next release of the specifications.

Documentation Changes include typos, errors, or omissions from the current published

specifications. These changes will be incorporated in the next release of the specifications.

64-bit Intel®Xeon®Processor with 800 MHz System Bus 7

(1 MB and 2 MB L2 Cache Versions) Specification Update

Identification Information

64-bit Intel®Xeon®Processor with 800 MHz System Bus

(1 MB and 2 MB L2 Cache Versions) Package Markings

(604-pin FC-mPGA4 Package)

The 64-bit Intel®Xeon®Processor with 800 MHz System Bus (1 MB and 2 MB L2 cache

versions) can be identified by the following values:

Figure 1. Top-Side Processor Marking Example

Figure 2. Bottom-Side Marking Example

2D Matrix Includes

ATPO and Serial Number

(front end mark)

Pin 1 Indicator

Intel Confidential

SL7DV

80546KE0461M

Pin Field

Cavity

with

Components

Text Line1

Text Line2

Text Line3

Pin 1 Indicator

S-Spec

FPO – Serial Number

864-bit Intel®Xeon®Processor with 800 MHz System Bus

(1 MB and 2 MB L2 Cache Versions) Specification Update

Identification Information

Cache and TLB descriptor parameters are provided in the EAX, EBX, ECX and EDX registers

after the CPUID instruction is executed with a 2 in the EAX register. Please refer to the Intel

Processor Identification and the CPUID Instruction Application Note (AP-485) for further

information on the CPUID instruction.

Table 1. Identification Information

Family1Model2Brand ID3

1111b 0011b 0000b

1111b 0100b 0000b

NOTES:

1. The Family corresponds to bits [11:8] of the EDX register after RESET, bits [11:8] of the

EAX register afterthe CPUID instruction is executed with a 1 in theEAX register, and the

generation field of the Device ID registers accessible through Boundary Scan

2. The Model corresponds to bits [7:4] of the EDX register after RESET, bits [7:4] of the

EAX register afterthe CPUID instruction is executed with a 1 in theEAX register, and the

model field of the Device ID registers accessible through Boundary Scan.

3. Brand ID returns 0000b, which means that Brand ID is unsupported in this processor.

Table 2. 64-bit Intel®Xeon®Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache

Versions) Identification Information (Sheet 1 of 2)

S-Spec Core

Stepping CPUID Core

Freq

(GHz)

Data Bus

Freq

(MHz)

Cache

Size

Processor

Package

Revision Package and Revision Notes

SL7DV D-0 0F34h 2.80 800 1 MB 01 604-pin micro-PGA with 42.5 x

42.5 mm FC-PGA4 package

SL7HF 1

SL7DW D-0 0F34h 3 800 1 MB 01 604-pin micro-PGA with 42.5 x

42.5 mm FC-PGA4 package

SL7HG 1

SL7DX D-0 0F34h 3.20 800 1 MB 01 604-pin micro-PGA with 42.5 x

42.5 mm FC-PGA4 package

SL7HH 1

SL7DY D-0 0F34h 3.40 800 1 MB 01 604-pin micro-PGA with 42.5 x

42.5 mm FC-PGA4 package 2, 3

SL7HJ 1, 2, 3

SL7DZ D-0 0F34h 3.60 800 1 MB 01 604-pin micro-PGA with 42.5 x

42.5 mm FC-PGA4 package 2, 3

SL7HK 1, 2, 3

SL7PD E-0 0F41h 2.80 800 1 MB 01 604-pin micro-PGA with 42.5 x

42.5 mm FC-PGA4 package 4, 6

SL7TB 1, 4, 6

SL7PE E-0 0F41h 3 800 1 MB 01 604-pin micro-PGA with 42.5 x

42.5 mm FC-PGA4 package 4, 6

SL7TC 1, 4, 6

SL7PF E-0 0F41h 3.20 800 1 MB 01 604-pin micro-PGA with 42.5 x

42.5 mm FC-PGA4 package 4, 6

SL7TD 1, 4, 6

SL7PG E-0 0F41h 3.40 800 1 MB 01 604-pin micro-PGA with 42.5 x

42.5 mm FC-PGA4 package 3, 4, 6

SL7TE 1, 3, 4, 6

SL7PH E-0 0F41h 3.60 800 1 MB 01 604-pin micro-PGA with 42.5 x

42.5 mm FC-PGA4 package 2, 3, 4, 6

SL7VF 1, 2, 3, 4,

SL84B E-0 0F41h 2.80 800 1 MB 01 604-pin micro-PGA with 42.5 x

42.5 mm FC-PGA4 package 4, 5, 6

SL8KN G-1 0F49h 2.80 800 1 MB 01 604-pin micro-PGA with 42.5 x

42.5 mm FC-PGA4 package 4, 6

64-bit Intel®Xeon®Processor with 800 MHz System Bus 9

(1 MB and 2 MB L2 Cache Versions) Specification Update

Identification Information

NOTES:

1. These are Intel boxed processors.

2. These parts have Thermal Monitor 2 (TM2) feature enabled. For D-0 stepping, TM2 is enabled on 3.40 GHz and above, but it is

NOT supported.

3. These parts are enabled for Enhanced Intel SpeedStep®Technology (EIST).

4. These parts are enabled for Enhanced Halt State (C1E).

5. These parts are LV (low-power) processors.

6. These parts have Execute Disable bit functionality.

7. These parts are MV (mid-power) processors.

SL8KP G-1 0F49h 3 800 1 MB 01 604-pin micro-PGA with 42.5 x

42.5 mm FC-PGA4 package 4, 6

SL8KQ G-1 0F49h 3.20 800 1 MB 01 604-pin micro-PGA with 42.5 x

42.5 mm FC-PGA4 package 4, 6

SL8KR G-1 0F49h 3.40 800 1 MB 01 604-pin micro-PGA with 42.5 x

42.5 mm FC-PGA4 package 3, 4, 6

SL8KS G-1 0F49h 3.60 800 1 MB 01 604-pin micro-PGA with 42.5 x

42.5 mm FC-PGA4 package 2, 3, 4, 6

SL8RW G-1 0F49h 2.80 800 1 MB 01 604-pin micro-PGA with 42.5 x

42.5 mm FC-PGA4 package 4, 5, 6

SL7ZC N-0 0F43h 3.60 800 2 MB 01 604-pin micro-PGA with 42.5 x

42.5 mm FC-PGA4 package 2, 3, 4, 6

SL7ZD N-0 0F43h 3.40 800 2 MB 01 604-pin micro-PGA with 42.5 x

42.5 mm FC-PGA4 package 2, 3, 4, 6

SL7ZE N-0 0F43h 3.20 800 2 MB 01 604-pin micro-PGA with 42.5 x

42.5 mm FC-PGA4 package 2, 4, 6

SL7ZF N-0 0F43h 3 800 2 MB 01 604-pin micro-PGA with 42.5 x

42.5 mm FC-PGA4 package 2, 4, 6

SL8P7 R-0 0F4Ah 2.80 800 2 MB 01 604-pin micro-PGA with 42.5 x

42.5 mm FC-PGA4 package 2, 3, 4, 6

SL8P6 R-0 0F4Ah 3 800 2 MB 01 604-pin micro-PGA with 42.5 x

42.5 mm FC-PGA4 package 2, 4, 6

SL8P5 R-0 0F4Ah 3.20 800 2 MB 01 604-pin micro-PGA with 42.5 x

42.5 mm FC-PGA4 package 2, 4, 6

SL8P4 R-0 0F4Ah 3.40 800 2 MB 01 604-pin micro-PGA with 42.5 x

42.5 mm FC-PGA4 package 2, 3, 4, 6

SL8P3 R-0 0F4Ah 3.60 800 2 MB 01 604-pin micro-PGA with 42.5 x

42.5 mm FC-PGA4 package 2, 3, 4, 6

SL8P2 R-0 0F4Ah 3.80 800 2 MB 01 604-pin micro-PGA with 42.5 x

42.5 mm FC-PGA4 package 2, 3, 4, 6

SL8SV R-0 0F4Ah 3 800 2 MB 01 604-pin micro-PGA with 42.5 x

42.5 mm FC-PGA4 package 2, 3, 4, 5,

SL8T3 R-0 0F4Ah 3.20 800 2 MB 01 604-pin micro-PGA with 42.5 x

42.5 mm FC-PGA4 package 2, 4, 6, 7

Table 2. 64-bit Intel®Xeon®Processor with 800 MHz System Bus (1 MB and 2 MB L2 Cache

Versions) Identification Information (Sheet 2 of 2)

S-Spec Core

Stepping CPUID Core

Freq

(GHz)

Data Bus

Freq

(MHz)

Cache

Size

Processor

Package

Revision Package and Revision Notes

10 64-bit Intel®Xeon®Processor with 800 MHz System Bus

(1 MB and 2 MB L2 Cache Versions) Specification Update

Identification Information

Mixed Steppings in DP Systems

Intel Corporation fully supports mixed steppings of the 64-bit Intel Xeon processor with 800 MHz

system bus as well as mixed steppings of the 64-bit Intel Xeon processor with 2 MB L2 cache. The

following list and processor matrix describes the requirements to support mixed steppings:

•Mixed steppings are only supported with processors that have identical family numbers as

indicated by the CPUID instruction.

•While Intel has done nothing to specifically prevent processors operating at differing

frequencies from functioning within a multiprocessor system, there may be uncharacterized

errata that exist in such configurations. Intel does not support such configurations. In mixed

stepping systems, all processors must operate at identical frequencies (i.e., the highest

frequency rating commonly supported by all processors).

•While there are no known issues associated with the mixing of processors with differing cache

sizes in a multiprocessor system, and Intel has done nothing to specifically prevent such

system configurations from operating, Intel does not support such configurations since there

may be uncharacterized errata that exist. In mixed stepping systems, all processors must be of

the same cache size.

•While Intel believes that certain customers may wish to perform validation of system

configurations with mixed frequencies, cache sizes or voltages and that those efforts are an

acceptable option to our customers, customers would be fully responsible for the validation of

such configurations.

•Intel requires that the proper microcode update be loaded on each processor operating in a

multiprocessor system. Any processor that does not have the proper microcode update loaded

is considered by Intel to be operating out of specification.

•The workarounds identified in this and following specification updates must be properly

applied to each processor in the system. Certain errata are specific to the multiprocessor

environment. Errata for all processor steppings will affect system performance if not properly

worked around. Also see Also see Table 2 and Table 3 for additional details on which

processors are affected by specific errata.

•In mixed stepping systems, the processor with the lowest feature-set, as determined by the

CPUID Feature Bytes, must be the Bootstrap Processor (BSP). In the event of a tie in

feature-set, the tie should be resolved by selecting the BSP as the processor with the lowest

stepping as determined by the CPUID instruction.

•While there are no known issues associated with the mixing of processors of different

power-optimization segments (i.e. LV or MV) in a multiprocessor system, and Intel has done

nothing to specifically prevent such system configurations from operating, Intel does not

support such configurations since there may be uncharacterized errata that exist. In mixed

stepping systems, all processors must be of the same power-optimization segment.

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