Intel RH80536GC0332M - Pentium M 1.8 GHz Processor Manual de usuario

Intel® Pentium® M Processor on

90 nm Process with 2-MB L2

Cache

Datasheet

January 2006

Document Number: 302189-008

2Datasheet

IINFORMATION IN THIS DOCUMENT IS PROVIDED IN CONNECTION WITH INTEL®PRODUCTS. NO LICENSE, EXPRESS OR IMPLIED, BY

ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IS GRANTED BY THIS DOCUMENT. EXCEPT AS PROVIDED IN

INTEL'S TERMS AND CONDITIONS OF SALE FOR SUCH PRODUCTS, INTEL ASSUMES NO LIABILITY WHATSOEVER, AND INTEL DISCLAIMS

ANY EXPRESS OR IMPLIED WARRANTY, RELATING TO SALE AND/OR USE OF INTEL PRODUCTS INCLUDING LIABILITY OR WARRANTIES

RELATING TO FITNESS FOR A PARTICULAR PURPOSE, MERCHANTABILITY, OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER

INTELLECTUAL PROPERTY RIGHT. Intel products are not intended for use in medical, life saving, life sustaining applications.

Intel may make changes to specifications and product descriptions at any time, without notice.

Designers must not rely on the absence or characteristics of any features or instructions marked “reserved” or “undefined.” Intel reserves these for

future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them.

The Intel®Pentium®M processor on 90 nm process with 2-MB L2 cache may contain design defects or errors known as errata which may cause the

product to deviate from published specifications. Current characterized errata are available on request.

Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order.

Intel processor numbers are not a measure of performance. Processor numbers differentiate features within each processor family, not across

different processor families. See www.intel.com/products/processor_number for details.

Intel, Pentium, Celeron, MMX, Intel SpeedStep andthe Intel logo aretrademarks or registered trademarks of Intel Corporation or its subsidiaries in the

United States and other countries.

*Other names and brands may be claimed as the property of others.

Datasheet 3

Contents

1 Introduction....................................................................................................................................7

1.1 Terminology..........................................................................................................................9

1.2 References ...........................................................................................................................9

2 Low Power Features....................................................................................................................11

2.1 Clock Control and Low Power States .................................................................................11

2.1.1 Normal State..........................................................................................................11

2.1.2 AutoHALT Power-Down State ...............................................................................11

2.1.3 Stop-Grant State....................................................................................................12

2.1.4 HALT/Grant Snoop State.......................................................................................12

2.1.5 Sleep State ............................................................................................................13

2.1.6 Deep Sleep State...................................................................................................13

2.1.7 Deeper Sleep State ...............................................................................................14

2.2 Enhanced Intel SpeedStep®Technology ...........................................................................14

2.3 Front Side Bus Low Power Enhancements ........................................................................15

2.4 Processor Power Status Indicator (PSI#) Signal ................................................................15

3 Electrical Specifications .............................................................................................................17

3.1 Power and Ground Pins......................................................................................................17

3.1.1 FSB Clock (BCLK[1:0]) and Processor Clocking...................................................17

3.2 Voltage Identification ..........................................................................................................17

3.3 Catastrophic Thermal Protection........................................................................................18

3.4 Signal Terminations and Unused Pins................................................................................19

3.5 FSB Frequency Select Signals (BSEL[1:0]) .......................................................................19

3.6 FSB Signal Groups.............................................................................................................19

3.7 CMOS Signals ....................................................................................................................20

3.8 Maximum Ratings...............................................................................................................21

3.9 Processor DC Specifications ..............................................................................................21

4 Package Mechanical Specifications and Pin Information .......................................................47

4.1 Processor Pinout and Pin List.............................................................................................54

4.2 Alphabetical Signals Reference..........................................................................................70

5 Thermal Specifications and Design Considerations................................................................77

5.1 Thermal Specifications .......................................................................................................80

5.1.1 Thermal Diode .......................................................................................................80

5.1.2 Thermal Diode Offset.............................................................................................81

5.1.3 Intel®Thermal Monitor...........................................................................................82

4Datasheet

Figures

2-1 Clock Control States...................................................................................................................11

3-1 Illustration of Active State VCC Static and Ripple Tolerances (HFM- VID#A)............................31

3-2 Illustration of Deep Sleep State VCC Static and Ripple Tolerances (LFM- VID#A) ...................32

3-3 Illustration of Active State VCC Static and Ripple Tolerances (HFM- VID#B)............................33

3-4 Illustration of Deep Sleep State VCC Static and Ripple Tolerances (LFM- VID#B) ...................34

3-5 Illustration of Active State VCC Static and Ripple Tolerances (HFM- VID#C) ...........................35

3-6 Illustration of Deep Sleep State VCC Static and Ripple Tolerances (LFM- VID#C)...................36

3-7 Illustration of Active State VCC Static and Ripple Tolerances (HFM- VID#D) ...........................37

3-8 Illustration of Deep Sleep State VCC Static and Ripple Tolerances (LFM- VID#D)...................38

3-9 Illustration of Active State VCC Static and Ripple Tolerances (HFM- VID#E)............................39

3-10Illustration of Deep Sleep State VCC Static and Ripple Tolerances (LFM- VID#E) ...................40

3-11Active VCC and ICC Load Line ..................................................................................................43

3-12Deep Sleep VCC and ICC Load Line.........................................................................................44

4-1 Micro-FCPGA Package Top and Bottom Isometric Views .........................................................47

4-2 Micro-FCPGA Package - Top and Side Views...........................................................................48

4-3 Micro-FCPGA Package - Bottom View.......................................................................................49

4-4 Micro-FCBGA Package Top and Bottom Isometric Views .........................................................51

4-5 Micro-FCBGA Package Top and Side Views .............................................................................52

4-6 Micro-FCBGA Package Bottom View.........................................................................................54

4-7 The Coordinates of the Processor Pins as Viewed from the Top of the Package......................55

Datasheet 5

Tables

1-1 References ...................................................................................................................................9

3-1 Voltage Identification Definition ..................................................................................................18

3-2 FSB Pin Groups..........................................................................................................................20

3-3 Processor DC Absolute Maximum Ratings.................................................................................21

3-4 Voltage and Current Specifications - Standard Voltage Processors ..........................................22

3-5 Voltage and Current Specifications - Low Voltage Processors ..................................................24

3-6 Voltage and Current Specifications - Ultra Low Voltage Processors..........................................26

3-7 Voltage and Current Specifications (Continued).........................................................................28

3-8 Voltage Tolerances for the Intel®Pentium®M Processor (Active State) VID#A........................31

3-9 Voltage Tolerances for the Intel®Pentium®M Processor (Deep Sleep State) VID#A...............32

3-10Voltage Tolerances for the Intel®Pentium®M Processor (Active State) VID#B........................33

3-11Voltage Tolerances for the Intel®Pentium®M Processor (Deep Sleep State) VID#B...............34

3-12Voltage Tolerances for the Intel®Pentium®M Processor (Active State) VID#C........................35

3-13Voltage Tolerances for the Intel®Pentium®M Processor (Deep Sleep State) VID#C...............36

3-14Voltage Tolerances for the Intel®Pentium®M Processor (Active State) VID#D........................37

3-15Voltage Tolerances for the Intel®Pentium®M Processor (Deep Sleep State) VID#D...............38

3-16Voltage Tolerances for the Intel®Pentium®M Processor (Active State) VID#E........................39

3-17Voltage Tolerances for the Intel®Pentium®M Processor (Deep Sleep State) VID#E...............40

3-18Voltage Tolerances for the Intel®Pentium®M Processor LV (Active State)..............................41

3-19Voltage Tolerances for the Intel®Pentium®M Processor LV (Deep Sleep State).....................42

3-20Voltage Tolerances for the Intel®Pentium®M Processor ULV (Active State)............................42

3-21Voltage Tolerances for the Intel®Pentium®M Processor ULV (Deep Sleep State)...................43

3-22FSB Differential BCLK Specifications.........................................................................................44

3-23AGTL+ Signal Group DC Specifications.....................................................................................45

3-24CMOS Signal Group DC Specifications......................................................................................45

3-25Open Drain Signal Group DC Specifications..............................................................................46

4-1 Micro-FCPGA Package Dimensions...........................................................................................50

4-2 Micro-FCBGA Package Dimensions...........................................................................................53

4-3 Pin Listing by Pin Name..............................................................................................................57

4-4 Pin Listing by Pin Number ..........................................................................................................63

4-5 Signal Description.......................................................................................................................70

5-1 Power Specifications for the Intel®Pentium M Processor..........................................................78

5-2 Thermal Diode Interface.............................................................................................................81

5-3 Thermal Diode Specification.......................................................................................................81

6Datasheet

Revision History

Revision Description Date

001 Initial release of datasheet May 2004

002 Added Intel®Pentium®M processor 725 and 715 specifications June 2004

003

• Specifications of Intel®Pentium®M processor Low Voltage 738

and Ultra Low Voltage 733 & 723 added in chapter 3 and chapter

• Chapter 2 section 2.1.3 - Missing Stop Grant State title added.

Description was previously merged with Auto Halt state section

and is unchanged.

• Table 4 - Max ratings specifications updated

July 2004

004 Added Intel®Pentium®M processor 765 specifications October 2004

005

• Added Intel®Pentium®M processor 753 and 758 specifications

• Added Execute Disable support feature and lead free SLI

(second layer interconnect) Micro-FCPGA packaging

information in chapter 1

• Added Table 3-20 AGTL + Signal Group Signal DC

Specifications

• Table 3-18 - Voltage Tolerances for Intel®Pentium®M

processor ULV (Deep Sleep State) updated

January 2005

006 • Added Intel®Pentium®M processor 778 specifications July 2005

007 Updated Intel® Pentium®M processor 753 and 733J specifications

for optimized VID July 2005

008 Added Intel®Pentium®M processor 773 specifications January 2006

Datasheet 7

Introduction

1Introduction

The Intel®Pentium®M processor based on 90 nm process technology featuring 2-MB L2 cache

and 400-MHz front side bus (FSB) is the next generation high- performance, low-power mobile

processor based on the Intel®Pentium®processor architecture.

Throughout this document, Intel Pentium M processor based on 90 nm technology featuring 2-MB

L2 cache and 400 MHz FSB will be referred to as Pentium M processor, or simply the processor,

including low voltage and ultra low voltage processors.

This document contains specifications for the Pentium M processors 765/ 755/ 745/ 735/ 725/ 715

Standard Voltage, 778/758/738 Low Voltage and 773/753/733J/733/723 Ultra Low Voltage.

Intel processor numbers are not a measure of performance. Processor numbers differentiate

features within each processor family, not across different processor families. See www.intel.com/

products/processor_number for details.

The following list provides some of the key features on this processor:

•Supports Intel®Architecture with Dynamic Execution

•On-die, primary 32-KB instruction cache and 32-KB write-back data cache

•On-die, 2 MB second level cache with Advanced Transfer Cache Architecture

•Way set associativity and ECC (Error Correcting Code) support

•Data Prefetch Logic

•Streaming SIMD extensions 2 (SSE2)

•400 MHz, source-synchronous FSB

•Advanced power management features including Enhanced Intel SpeedStep®technology

•Micro-FCPGA and Micro-FCBGA packaging technologies

•Manufactured on Intel’s advanced 90 nanometer process technology with copper interconnect.

•Support for MMX™ technology and Internet Streaming SIMD instructions

•The processor’s data prefetch logic fetches data to the L2 cache before L1 cache requests

occurs, resulting in reduced bus cycle penalties and improved performance

•Micro-FCPGA and Micro-FCBGA packaging technologies, including lead free SLI (second

level interconnect) technology for the Micro-FCBGA package (for Pentium M processors 755,

745, 778, 758, 738, 773, 753, 733J/733, 723)

•Execute Disable Bit support for enhanced security (available on processors with CPU

Signature = 06D8h and recommended for implementation on Intel®915 Express chipset

family-based platforms only)

The Pentium M processor will be manufactured on Intel’s advanced 90 nm process technology

with copper interconnect. The processor maintains support for MMX technology and Internet

Streaming SIMD instructions and full compatibility with IA-32 software. The on-die, 32-KB

Level 1 instruction and data caches along with the 2-MB L2 cache with advanced transfer cache

8Datasheet

Introduction

architecture enable significant performance improvement over existing mobile processors. The

processor’s data prefetch logic fetches data to the L2 cache before L1 cache requests occurs,

resulting in reduced bus cycle penalties and improved performance.

The streaming SIMD extensions 2 (SSE2) enable break-through levels of performance in

multimedia applications including 3-D graphics, video decoding/encoding, and speech recognition.

The new packed double-precision floating-point instructions enhance performance for applications

that require greater range and precision, including scientific and engineering applications and

advanced 3-D geometry techniques, such as ray tracing.

The Pentium M processor’s 400-MHz FSB utilizes a split-transaction, deferred reply protocol. The

400-MHz FSB uses source-synchronous transfer (SST) of address and data to improve

performance by transferring data four times per bus clock (4X data transfer rate, as in AGP 4X).

Along with the 4X data bus, the address bus can deliver addresses two times per bus clock and is

referred to as a “double-clocked” or 2X address bus. Working together, the 4X data bus and 2X

address bus provide a data bus bandwidth of up to 3.2 GB/second. The FSB uses Advanced

Gunning Transceiver Logic (AGTL+) signaling technology, a variant of GTL+ signaling

technology with low power enhancements.

The processor features Enhanced Intel SpeedStep technology, which enables real-time dynamic

switching between multiple voltage and frequency points. This results in optimal performance

without compromising low power. The processor features the Auto Halt, Stop Grant, Deep Sleep,

and Deeper Sleep low power states.

The Pentium M processor utilizes socketable Micro Flip-Chip Pin Grid Array (Micro-FCPGA) and

surface mount Micro Flip-Chip Ball Grid Array (Micro-FCBGA) package technology. The Micro-

FCPGA package plugs into a 479-hole, surface-mount, zero insertion force (ZIF) socket, which is

referred to as the mPGA479M socket.

Pentium M processors with CPU Signature = 06D8h will also include the Execute Disable Bit

capability. This feature combined with a support operating system allows memory to be marked as

executable or non executable. If code attempts to run in non-executable memory the processor

raises an error to the operating system. This feature can prevent some classes of viruses or worms

that exploit buffer overrun vulnerabilities and can thus help improve the overall security of the

system. See the Intel®Architecture Software Developer's Manual for more detailed information.

Intel will validate this feature only on Intel 915 Express chipset family based platforms and

recommends customers implement BIOS changes related to this feature, only on Intel 915 Express

chipset family based platforms.

Note: The term AGTL+ is used to refer to Assisted GTL+ signalling technology on some Intel processors.

Datasheet 9

Introduction

1.1 Terminology

1.2 References

Material and concepts available in the following documents may be beneficial when reading this

document. Please note that “platform design guides,” when used throughout this document, refers

to the platform design guides listed below:

Term Definition

# A “#” symbol after a signal name refers to an active low signal, indicating a signal is in

the active state when driven to a low level. For example, when RESET# is low, a reset

has been requested. Conversely, when NMI is high, a nonmaskable interrupt has

occurred. In the case of signals where the name does not imply an active state but

describes part of a binary sequence (such as address or data), the “#” symbol implies

that the signal is inverted. For example, D[3:0] = “HLHL” refers to a hex ‘A’, and

D[3:0]# = “LHLH” also refers to a hex “A” (H= High logic level, L= Low logic level).

XXXX means that the specification or value is yet to be determined.

Front Side Bus

(FSB) Refers to the interface between the processor and system core logic (also known as

the chipset components).

Table 1-1. References (Sheet 1 of 2)

Document Document Number/

Location1

IntelPentiumM Processor on 90 nm Process with 2-MB L2 Cache -

Specification Update http://www.intel.com/

design/mobile/specupdt/

302209.htm

Mobile Intel915PM/GM/GMS and 910GML Express Chipset Datasheet http://www.intel.com/

design/mobile/datashts/

305264.htm

Mobile Intel915PM/GM/GMS and 910GML Express Chipset Specification

Update http://www.intel.com/

design/mobile/specupdt/

307167.htm

Intel855PM Chipset Platform Design Guide: For use with IntelPentiumM and

IntelCeleronProcessors http://developer.intel.com/

design/mobile/desguide/

252614.htm

Intel855PM Chipset Memory Controller Hub (MCH) Datasheet http://developer.intel.com/

design/chipsets/datashts/

252613.htm

Intel855PM Chipset MCH DDR 333/200/266 MHz Specification Update http://developer.intel.com/

design/chipsets/specupdt/

253488.htm

Intel855GM/GME Chipset Graphics and Memory Controller Hub (GMCH)

Datasheet http://developer.intel.com/

design/chipsets/datashts/

252615.htm

Intel855GM/GME Chipset Graphics and Memory Controller Hub (GMCH)

Chipset Specification Update http://developer.intel.com/

design/chipsets/specupdt/

253572.htm

Intel855GM/855GME Chipset Platform Design Guide http://developer.intel.com/

design/mobile/desguide/

252616.htm

10 Datasheet

Introduction

NOTE: Contact your Intel representative for the latest revision and document number of this document.

IA-32 IntelArchitecture Software Developer's Manual http://www.intel.com/

design/pentium4/

manuals/index_new.htm

Volume 1: Basic Architecture

Volume 2A: Instruction Set Reference

Volume 2B: Instruction Set Reference

Volume 3: System Programming Guide

Table 1-1. References (Sheet 2 of 2)

Document Document Number/

Location1

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