Ingenic JZ4775 Guía

Ingenic®JZ4775

Board Design Guide

Revision: 1.1

Date: Sept. 2013

Ingenic JZ4775

Board Design Guide

Release history

Date

Revision

Change

Mar 2013

1.0

First release

Sep.2013

1.1

Change the company address and etc

Disclaimer

This documentation is provided for use with Ingenic products. No license to Ingenic property rights is

granted. Ingenic assumes no liability, provides no warranty either expressed or implied relating to

the usage, or intellectual property right infringement except as provided for by Ingenic Terms and

Conditions of Sale.

Ingenic products are not designed for and should not be used in any medical or life sustaining or

supporting equipment.

All information in this document should be treated as preliminary. Ingenic may make changes to this

document without notice. Anyone relying on this documentation should contact Ingenic for the

current documentation and errata.

Ingenic Semiconductor Co., Ltd.

Junzheng Bld, Zhongguancun Software Park 2 Dongbeiwang West Road, Haidian

District Beijing,China,100193

Tel: 86-10-56345000

Fax: 86-10-56345001

Http: //www.ingenic.cn

Content

Board Design Guide for JZ4775, Revision 1.1

Content

1Overview............................................................................................. 1

1.1 Introduction.........................................................................................................................1

1.2 Reference Platform.............................................................................................................2

2Platform Stack-Up and Placement...................................................... 3

2.1 General Design Considerations...........................................................................................3

2.2 Nominal 6-Layer Board Stack-Up........................................................................................3

2.3 PCB Technology Considerations.........................................................................................4

2.4 4-Layer Board Stack-Up......................................................................................................5

2.5 8-Layer HDI Board Stack-Up...............................................................................................6

3Static Memory Interface Design Guidelines ....................................... 7

3.1 Overview ............................................................................................................................7

3.2 Boot Memory......................................................................................................................7

3.3NAND Flash Connection.....................................................................................................8

4DDR3 SDRAM.................................................................................... 9

4.1 Overview ............................................................................................................................9

4.2 Connection to two 2Gb x 16 DDR3 SDRAM device.............................................................9

4.3 Connection to four 1Gb x 8 DDR3 SDRAM device.............................................................10

4.4 Layout Guideline...............................................................................................................10

5Audio Codec Design Guidelines....................................................... 14

5.1 Overview ..........................................................................................................................14

5.2 Audio Power .....................................................................................................................14

5.3 Headphone Out ................................................................................................................14

5.4 Mic In................................................................................................................................15

5.5 Speaker............................................................................................................................16

5.6 Receiver...........................................................................................................................16

5.7 Line In...............................................................................................................................16

5.8 Layout Guideline...............................................................................................................17

6USB and OTG Design Guidelines .................................................... 19

6.1 USB Overview ..................................................................................................................19

6.1.1 USB Power................................................................................................................19

6.2 OTG Overview..................................................................................................................19

6.2.1 OTG Power ...............................................................................................................19

6.3 Guidelines for the USB and OTG interface........................................................................20

7LCD................................................................................................... 23

Content

Board Design Guide for JZ4775, Revision 1.1

8EPD ...................................................................................................26

8.1 Overview..........................................................................................................................26

9Camera..............................................................................................27

9.1 Overview..........................................................................................................................27

10 SAR A/D Controller............................................................................28

10.1 Overview..........................................................................................................................28

10.2 Touch Screen...................................................................................................................28

10.3 Battery Voltage Measurement...........................................................................................29

11 OTP EFUSE ......................................................................................30

11.1 Overview..........................................................................................................................30

12 Ethernet Design Guidelines...............................................................31

12.1 Overview..........................................................................................................................31

12.2 JZ4775 Ethernet Controller Connection............................................................................ 31

13 RTC ...................................................................................................32

13.1 Overview..........................................................................................................................32

13.2 RTC Clock........................................................................................................................ 32

13.3 Power Control ..................................................................................................................32

14 Miscellaneous Peripheral Design Guidelines....................................34

14.1 SSI Design Guideline .......................................................................................................34

14.2 UART...............................................................................................................................35

14.2.1 UART Implementation...............................................................................................35

14.3 SMB BUS.........................................................................................................................36

14.4 PWM................................................................................................................................36

14.5 GPIO................................................................................................................................36

14.6 JTAG/Debug Port ............................................................................................................. 36

15 Platform Clock Guidelines.................................................................38

16 Platform Power Guidelines................................................................39

16.1 Overview..........................................................................................................................39

16.2 Power Delivery and Decoupling........................................................................................39

Overview

Board Design Guide for JZ4775, Revision 1.1

1 Overview

JZ4775 is a mobile application processor targeting for multimedia rich and mobile devices like tablet

computer, EBook, mobile digital TV. This SOC introduces a kind of innovative architecture to fulfill

both high performance mobile computing and high quality video decoding requirements addressed

by mobile multimedia devices. JZ4775 provides high-speed CPU computing power and fluent 720p

video replay.

The CPU (Central Processing Unit) core, equipped with 16kB instruction and 16kB data level 1

cache, and 256kB level 2 cache, operating at 1GHz, and full feature MMU function performs OS

related tasks.

At the heart of the CPU core is XBurst® processor engine. XBurst® is an industry leading

microprocessor core which delivers superior high performance and best-in-class low power

consumption. A hardware floating-point unit which compatible with IEEE754 is also included.

The VPU (Video Processing Unit) core is powered with another XBurst® processor engine. The

SIMD instruction set implemented by XBurst® engine, in together with the on chip video

accelerating engine and post processing unit, delivers high video performance. The maximum

resolution of 720p in the formats of H.264, VC-1, MPEG-1/2, MPEG-4, RealVideo and VP8 are

supported in decoding.

The memory interface supports a variety of memory types that allow flexible design requirements,

including glueless connection to SLC NAND flash memory or up to 64-bit ECC MLC/TLC NAND

flash memory and toggle NAND flash for cost sensitive applications. It provides the interface to

DDR2, DDR3 and LPDDR memory chips with lower power consumption.

On-chip modules such as audio CODEC, multi-channel SAR-ADC, AC97/I2S controller and camera

interface offer designers a rich suite of peripherals for multimedia application. The LCD controller

support regular RGB, 1024x768 output, WLAN, Bluetooth and expansion options are supported

through high-speed SPI and MMC/SD/SDIO host controllers. Other peripherals such as USB OTG

and USB 1.1 host, UART and SPI as well as general system resources provide enough computing

and connectivity capability for many applications.

1.1 Introduction

This design guide provides recommendations for system designs based on the JZ4775 processor.

Design issues (e.g., thermal considerations) should be addressed using specific design guides or

application notes for the processor.

The design guidelines in this document are used to ensure maximum flexibility for board designers

while reducing the risk of board related issues. The design information provided in this document

falls into two categories:

• Design Recommendations: It is based on INGENIC‟s simulations and lab experience to date

are strongly recommended, if not necessary, to meet the timing and signal quality

specifications.

• Design Considerations: Suggestions for platform design provide one way to meet the design

recommendations. Design considerations are based on the reference platforms designed by

Overview

Board Design Guide for JZ4775, Revision 1.1

INGENIC. They should be used as an example, but may not be applicable to particular

designs.

Note: In this manual, processor means the JZ4775 processor if not specified.

The guidelines recommended in this manual are based on experience and simulation work

completed by INGENIC while developing systems with JZ4775. This work is ongoing, and the

recommendations and considerations are subject to change.

Platform schematics can be obtained and are intended as a reference for board designers.

While the schematics may cover a specific design, the core schematics remain the same for

most platforms. The schematic set provides a reference schematic for each platform

component, and common system board options. Additional flexibility is possible through other

permutations of these options and components.

The document can help customer span doorstep, design product using existent software and

hardware resources. Your advice is the best encourage for us.

1.2 Reference Platform

Figure 1-1 shows the JZ4775 Development Board Architecture.

LCD I2C1 LCD/EPD

BOARD

HEADER

EPD

TOUCH SCREEN

32.768K I2C1

LINE OUT

HP OUT

Reset

MIC811

DRAMS(DDR3)

MSC1(Boot)

26M

USB

HOST

3223

CRY

CAMERA

HEADER

RTC

USB

OTG

CRY

MIC1/MIC2

AUDIO

JACK

PMU

CIM1

Reset

RS232 DB9,UART2

Line IN

AUDIO

Jack

AMPRECEIVER

UART2

JZ4775

PCM

DRAMBUS

UART2

SD&TF SOCKET

Line IN(differ)

USB2.0 USB1.1

NAND\MCP\INAND\Toggle NAND

I2C2

STATIC MEMBUS

JTAG

HEADER

WIFI

I2C1

UART0

MSC1

10M/100M/1000M

ETHERNET

Figure 1-1 JZ4775 Development Board Architecture

Platform Stack-Up and Placement

Board Design Guide for JZ4775, Revision 1.1

2 Platform Stack-Up and Placement

In this section, an example of a JZ4775 platform component placement and stack-up is presented

for a PMP product.

2.1 General Design Considerations

This section describes motherboard layout and routing guidelines for JZ4775 platforms. This section

does not describe the function of any bus, or the layout guidelines for an add-in device. If the

guidelines listed in this manual are not followed, it is very important that thorough signal integrity and

timing simulations are completed for each design. Even when the guidelines are followed, critical

signals are recommended to be simulated to ensure proper signal integrity and flight time. Any

deviation from the guidelines should be simulated.

The trace impedance typically noted (i.e., 50Ω ± 10%) is the nominal trace impedance for a 4-mil

wide trace. That is, the impedance of the trace when not subjected to the fields created by changing

current in neighboring traces. When calculating flight times, it is important to consider the minimum

and maximum impedance of a trace based on the switching of neighboring traces. Using wider

spaces between the traces can minimize this trace-to-trace coupling. In addition, these wider spaces

reduce settling time. Coupling between two traces is a function of the coupled length, the distance

separating the traces, the signal edge rate, and the degree of mutual capacitance and inductance.

To minimize the effects of trace-to-trace coupling, the routing guidelines documented in this section

should be followed. Additionally, these routing guidelines are created using a PCB stack-up similar

to that illustrated in Figure 2-1.

2.2 Nominal 6-Layer Board Stack-Up

The JZ4775 platform requires a board stack-up yielding a target board impedance of 50 Ω ± 10%.

Recommendations in this design guide are based on the following a 6-layer board stack-up:

Core Layer 8

Ground Layer 9

Prepreg Layer 10

Signal Layer 11

Figure 2-1 6-layer PCB Stack-Up

Prepreg Layer 6

Ground Layer 3

Signal Layer 1

Prepreg Layer 2

Core Layer 4

Power Layer 7

-----------------------------------------------------

Total Thickness 62 mils.

Signal Layer 5

Platform Stack-Up and Placement

Board Design Guide for JZ4775, Revision 1.1

Table 2-1 PCB Parameter

Description

Nominal Value

Tolerance

Comments

Board Impedance Z0

50Ω

±10%

With nominal 4 mil trace width

Dielectric Thickness

4.3 mils

±0.5 mils

1 x 2116 Pre-Preg

Micro-stripline Er

4.1

±0.4

@ 100 MHz

Trace Width

4.0 mils

±0.5 mils

Standard trace

Trace Thickness

2.1 mils

±0.5 mils

0.5 oz foil + 1.0 oz plate

Solder mask Er

4.0

±0.5

@ 100 MHz

Solder mask Thickness

1.0 mils

±0.5 mils

From top of trace

2.3 PCB Technology Considerations

The following recommendation aids in the design of a JZ4775 based platform. Simulations and

reference platform are based on the following technology, and we recommend that designers

adhere to these guidelines.

Figure 2-2 PCB Technologies –Stack-Up

L1 Signal

L6 Signal

L2 Ground

Copper

L4 Power

Copper

L3 Signal

L5 Ground

Copper

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