IDT 89HPES5T5 Manual de usuario

January 2011

6024 Silver Creek Valley Road, San Jose, California 95138

Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775

Printed in U.S.A.

IDT™89HPES5T5

PCI Express® Switch

Preliminary User Manual

GENERAL DISCLAIMER

Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance

and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitryembodied in an IDT product. The

Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is

granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc.

CODE DISCLAIMER

Code examples providedby IDT are forillustrative purposes only and should not be relieduponfor developing applications.Any use ofthecode examples belowiscompletely

at your own risk. IDT MAKES NOREPRESENTATIONSOR WARRANTIES OF ANYKINDCONCERNING THE NONINFRINGEMENT, QUALITY, SAFETY OR SUITABILITY

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LAR PURPOSE, ORNON-INFRINGEMENT. FURTHER, IDT MAKES NO REPRESENTATIONS OR WARRANTIES AS TO THETRUTH, ACCURACY OR COMPLETENESS

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SPECIAL DAMAGES, HOWEVER THEY MAY ARISE, AND EVEN IF IDT HAS BEEN PREVIOUSLY ADVISED ABOUT THE POSSIBILITY OF SUCH DAMAGES. The code

examples also may besubjectto United States export control lawsand maybe subjectto theexportorimportlaws of other countriesand it is your responsibility to complywith

any applicable laws or regulations.

LIFE SUPPORT POLICY

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such intended use is executed between the manufacturer and an officer of IDT.

1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform,

when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

2. A critical component is anycomponents of a life supportdevice or system whosefailure to performcanbe reasonably expected tocausethe failureofthe life support device

or system, or to affect its safety or effectiveness.

IDT, the IDT logo, and Integrated Device Technology are trademarks or registered trademarks of Integrated Device Technology, Inc.

Notes

PES5T5 User Manual 1 January 28, 2011

About this Manual

Introduction

This user manual includes hardware and software information on the 89HPES5T5, a member of IDT’s

PRECISE™ family of PCI Express® switching solutions offering the next-generation I/O interconnect stan-

dard.

Finding Additional Information

Informationnot included inthis manualsuchas mechanicals,package pin-outs, andelectrical character-

istics can be found in the data sheet for this device, which is available from the IDT website (www.idt.com)

as well as through your local IDT sales representative.

Content Summary

Chapter 1, “PES5T5 Device Overview,” provides a complete introduction to the performance capabili-

ties of the 89HPES5T5. Included in this chapter is a summary of features for the device as well as a system

block diagram and pin description.

Chapter 2, “Clocking, Reset, and Initialization,” provides a description of the two differential refer-

ence clock inputs that are used internally to generate all of the clocks required by the internal switch logic

and the SerDes.

Chapter 3, “Theory of Operation,” describes the operation of the link feature including polarity inver-

sion, link width negotiation, and lane reversal.

Chapter 4, “Link Operation,” describes the operation of the link feature including polarity inversion,

link width negotiation, and lane reversal.

Chapter 5, “General Purpose I/O,” describes how the 16 General Purpose I/O (GPIO) pins may be

individually configured as general purpose inputs, general purpose outputs, or alternate functions.

Chapter 6, “SMBus Interfaces,” describes the operation of the 2 SMBus interfaces on the PES5T5.

Chapter 7, “Power Management,” describes the power management capabilitystructure located in the

configuration space of each PCI-PCI bridge in the PES5T5.

Chapter 8, “Hot-Plug and Hot-Swap,” describes the behavior of the hot-plug and hot-swap features in

the PES5T5.

Chapter 9, “Configuration Registers,” discusses the base addresses, PCI configuration space, and

registers associated with the PES5T5.

Chapter 10, “JTAG Boundary Scan,” discusses an enhanced JTAG interface, including a system logic

TAP controller, signal definitions, a test data register, an instruction register, and usage considerations.

Signal Nomenclature

To avoid confusion when dealing with a mixture of “active-low” and “active-high” signals, the terms

assertion and negation are used. The term assert or assertion is used to indicate that a signal is active or

true, independent of whether thatlevel is represented by a high or lowvoltage. The term negate or negation

is used to indicate that a signal is inactive or false.

To define the active polarity of a signal, a suffix will be used. Signals ending with an ‘N’ should be inter-

preted as being active, or asserted, when at a logic zero (low) level. All other signals (including clocks,

buses and select lines) will be interpreted as being active, or asserted when at a logic one (high) level.

IDT

PES5T5 User Manual 2 January 28, 2011

Notes To define buses, the most significant bit (MSB) will be on the left and least significant bit (LSB) will be on

the right. No leading zeros will be included.

Throughout this manual, when describing signal transitions, the following terminology is used. Rising

edgeindicates a low-to-high(0 to1) transition. Falling edge indicates a high-to-low (1 to0)transition. These

terms are illustrated in Figure 1.

Figure 1 Signal Transitions

Numeric Representations

To represent numerical values, either decimal, binary, or hexadecimal formats will be used. The binary

format is as follows: 0bDDD, where “D” represents either 0 or 1; the hexadecimal format is as follows:

0xDD, where “D” represents the hexadecimal digit(s); otherwise, it is decimal.

The compressed notation ABC[x|y|z]D refers to ABCxD, ABCyD, and ABCzD.

The compressed notation ABC[x:y]D refers to ABCxD, ABC(x+1)D, ABC(x+2)D,... ABCyD if x < y or to

ABCxD, ABC(x-1)D, ABC(x-2)D,... ABCyD if x > y.

Data Units

The following data unit terminology is used in this document.

In quadwords, bit 63 is always the most significant bit and bit 0 is the least significant bit. In double-

words, bit 31 is always the most significant bit and bit 0 is the least significant bit. In words, bit 15is always

the most significant bit and bit 0 is the least significant bit. In bytes, bit 7 is always the most significant bit

and bit 0 is the least significant bit.

The ordering of bytes within words is referred to as either “big endian” or “little endian.” Big endian

systems label byte zero as the most significant (leftmost) byte of a word. Little endian systems label byte

zero as the least significant (rightmost) byte of a word.

Term Words Bytes Bits

Byte 1/2 1 8

Word 1 2 16

Doubleword (Dword) 2 4 32

Quadword (Qword) 4 8 64

Table 1 Data Unit Terminology

1 2 3 4

high-to-low

transition low-to-high

transition

single clock cycle

IDT

PES5T5 User Manual 3 January 28, 2011

Notes

Table 2 Example of Byte Ordering for “Big Endian” or “Little Endian” System Definition

Note: Software in the context of this register terminology refers to modifications made by PCIe

rootconfiguration writes toregisters made throughthe slave SMBusinterface,or serial EEPROM

Type Abbreviation Description

Hardware Initialized HWINIT Register bits are initialized by firmware or hardware mecha-

nisms such as pin strapping or serial EEPROM. (System firm-

ware hardware initialization is only allowed for system

integrateddevices.)Bitsareread-onlyafterinitializationandcan

only be reset (for write-once by firmware) with reset.

Read Only and Clear RC Software can read the register/bits with this attribute. Reading

the value will automatically cause the register/bit to be reset to

zero. Writing to a RC location has no effect.

Read Clear and Write RCW Software can read the register/bits with this attribute. Reading

the value will automatically cause the register/bits to be reset to

zero. Writes cause the register/bits to be modified.

Reserved Reserved The value read from a reserved register/bit is undefined. Thus,

software must deal correctly with fields that are reserved. On

reads, software must use appropriate masks to extract the

defined bits and not rely on reserved bits being any particular

value. On writes, software must ensure that the values of

reserved bit positions are preserved. That is, the values of

reserved bit positions must first be read, merged with the new

values for other bit positions and then written back.

Read Only RO Software can only read registers/bits with this attribute. Con-

tents are hardwired to a constant value or are status bits that

may be set and cleared by hardware. Writing to a RO location

has no effect.

Read and Write RW Software can both read and write bits with this attribute.

Table 3 Register Terminology (Sheet 1 of 2)

0123

bit 0bit 31

Address of Bytes within Words: Big Endian

3210

bit 0bit 31

Address of Bytes within Words: Little Endian

IDT

PES5T5 User Manual 4 January 28, 2011

Notes

Use of Hypertext

In Chapter 9, Tables 9.2 and 9.3 contain register names and page numbers highlighted inblue under the

clicking on the register name in the source table. Each register name in the table is linked directly to the

appropriate register in the register section of the chapter. To return to the source table after having jumped

to the register section, click on the same register name (in blue) in the register section.

Reference Documents

PCI Express Base Specification, Revision 1.1, PCI Special Interest Group.

PCI Power Management Interface Specification, Revision 1.2, PCI Special Interest Group.

PCI to PCI Bridge Architecture Specification, Revision 1.2, PCI Special Interest Group.

SMBus Specification, Revision 2.0.

Read and Write Clear RW1C Software can read and write to registers/bits with this attribute.

However,writing avalueof zerotoa bitwiththis attributehas no

effect. A RW1C bit canonlybe settoavalueof 1by a hardware

event. To clear a RW1C bit (i.e., change its value to zero) a

value of one must be written to the location. An RW1C bit is

never cleared by hardware.

Read and Write when

Unlocked RWL Software can read the register/bits with this attribute. Writing to

modified if the REGUNLOCK bit in the SWCNTL register is set.

When the REGUNLOCK bit is cleared, writes are ignored and

the register/bits are effectively read-only.

These registers are Sticky as they are preserved across a hot

reset. These bits are not preserved during fundamental reset.

Read Only Sticky ROS Registers are read-only and cannot be altered by software. Reg-

isters are not initialized or modified by hot reset.

When device consumes AUX power, some of these bits main-

tain their value across fundamental reset and are marked

FRSticky.

Read and Write Sticky RWS Registers are read-write and may be either set or cleared by

software to the desired state. Bits are not initialized or modified

by hot reset.

When device consumes AUX power, some of these bits main-

tain their value across fundamental reset and are marked

FRSticky.

Read Write-1-to-Clear

Sticky RWICS Registers indicate status when read, a set bit indicating a status

event may be cleared by writing a 1. Writing a 0 to RW1CS bits

has no effect. Bits are not initialized or modified by hot reset.

When device consumes AUX power, some of these bits main-

tain their value across fundamental reset and are marked

FRSticky.

Write Transient WT The zero is always read from a bit/field of this type. Writing of a

one is used to qualify the writing of other bits/fields in the same

Zero Zero A zero register or bit must be written with a value of zero and

returns a value of zero when read.

Type Abbreviation Description

Table 3 Register Terminology (Sheet 2 of 2)

IDT

PES5T5 User Manual 5 January 28, 2011

Notes Revision History

June 5, 2007: Initial Publication.

July 11, 2007: Corrected AERUCS to AERUES in AERCTL register, Chapter 8.

July 16, 2007: Made numerous minor edits throughout manual.

January 23, 2008: In Table 9.2, changed pins PE0RN/RP/TN/TP to read [0] instead of [1:0].

September 24, 2009: In Chapter 3, change made to L2 description in Link States section. Made

numerous changes in Chapter 6, Power. In Chapter 8, Registers, modified description of the LDIS bit in the

PCI Express Link Control register and changed bit field for CTLPTOC in the Switch Time-Out Count register to

[24:16].

November 10, 2009: Added a new Chapter 3 called Theory of Operations.

January 28, 2011: ZB silicon added to Table 1.9, Revision ID.

IDT

PES5T5 User Manual 6 January 28, 2011

Notes

PES5T5 User Manual i January 28, 2011

Table of Contents

PES5T5 Device Overview

Introduction.....................................................................................................................................1-1

List of Features...............................................................................................................................1-1

System Diagrams............................................................................................................................1-3

Logic Diagram.................................................................................................................................1-4

SSID/SSVID............................................................................................................................1-4

Device Serial Number Enhanced Capability...........................................................................1-5

Pin Description................................................................................................................................1-5

Pin Characteristics..........................................................................................................................1-9

System Identification.....................................................................................................................1-10

Vendor ID..............................................................................................................................1-10

Device ID..............................................................................................................................1-10

Revision ID...........................................................................................................................1-10

JTAG ID................................................................................................................................1-11

Port Configuration.........................................................................................................................1-11

Clocking, Reset, and Initialization

Introduction.....................................................................................................................................2-1

Initialization.....................................................................................................................................2-3

Reset...............................................................................................................................................2-5

Fundamental Reset................................................................................................................2-5

Hot Reset................................................................................................................................2-7

Upstream Secondary Bus Reset............................................................................................2-8

Downstream Secondary Bus Reset........................................................................................2-8

Downstream Port Reset Outputs....................................................................................................2-9

Power Enable Controlled Reset Output..................................................................................2-9

Power Good Controlled Reset Output..................................................................................2-10

Hot Reset Controlled Reset Output......................................................................................2-10

Theory of Operation

Port Interrupts.................................................................................................................................3-1

Legacy Interrupt Emulation.............................................................................................................3-1

Link Operation

Introduction.....................................................................................................................................4-1

Polarity Inversion............................................................................................................................4-1

Link Width Negotiation....................................................................................................................4-1

Link Retraining................................................................................................................................4-1

Link Down.......................................................................................................................................4-1

Slot Power Limit Support................................................................................................................4-2

Upstream Port.........................................................................................................................4-2

Downstream Port....................................................................................................................4-2

Link States......................................................................................................................................4-2

Active State Power Management....................................................................................................4-3

Link Status......................................................................................................................................4-4

IDT Table of Contents

PES5T5 User Manual ii January 28, 2011

Notes General Purpose Inputs/Outputs

Introduction.....................................................................................................................................5-1

GPIO Configuration ........................................................................................................................5-1

GPIO Pin Configured as an Input...........................................................................................5-2

GPIO Pin Configured as an Output........................................................................................5-2

GPIO Pin Configured as an Alternate Function......................................................................5-2

SMBus Interfaces

Introduction.....................................................................................................................................6-1

Master SMBus Interface.................................................................................................................6-2

Initialization.............................................................................................................................6-2

Serial EEPROM......................................................................................................................6-2

I/O Expanders.........................................................................................................................6-6

Slave SMBus Interface.................................................................................................................6-12

Initialization...........................................................................................................................6-12

SMBus Transactions ............................................................................................................6-12

Power Management

Introduction.....................................................................................................................................7-1

PME Messages...............................................................................................................................7-2

Power Express Power Management Fence Protocol.....................................................................7-3

Power Budgeting Capability............................................................................................................7-3

Wakeup Protocol ............................................................................................................................7-4

WAKEN Signal as an Input.....................................................................................................7-5

WAKEN Signal as an Output..................................................................................................7-5

WAKEN and Beacon Disabled...............................................................................................7-5

Auxiliary Power Implementation .....................................................................................................7-5

Switch System States.............................................................................................................7-5

Auxiliary Power Control ..................................................................................................................7-6

PES5T5 Auxiliary Power Usage............................................................................................7-8

Hot-Plug and Hot-Swap

Introduction.....................................................................................................................................8-1

Hot-Plug I/O Expander ...........................................................................................................8-4

Hot-Plug Interrupts and Wake-up...........................................................................................8-4

Legacy System Hot-Plug Support ..........................................................................................8-4

Hot-Swap........................................................................................................................................8-6

Configuration Registers

Configuration Space Organization..................................................................................................9-1

Upstream Port (Port 0) ...........................................................................................................9-3

Downstream Ports (Ports 2 through 5)...................................................................................9-7

Register Definitions.......................................................................................................................9-11

Type 1 Configuration Header Registers...............................................................................9-11

PCI Express Capability Structure.........................................................................................9-21

Power Management Capability Structure.............................................................................9-32

Message Signaled Interrupt Capability Structure.................................................................9-34

Subsystem ID and Subsystem Vendor ID............................................................................9-35

Extended Configuration Space Access Registers................................................................9-36

Advanced Error Reporting (AER) Enhanced Capability.......................................................9-37

Device Serial Number Enhanced Capability.........................................................................9-43

PCI Express Virtual Channel Capability...............................................................................9-43

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