IDT EB8T5A Eval Board Manual de usuario

July 2009

6024 Silver Creek Valley Road, San Jose, California 95138

Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775

Printed in U.S.A.

IDT™89EBPES8T5A

Evaluation Board Manual

(Eval Board: 18-636-002)

DISCLAIMER

Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance

and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The

Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is

granted by implication or otherwise under any patent, patent rights or other rights, of Integrated Device Technology, Inc.

Boards that fail to function should be returned to IDT for replacement. Credit will not be given for the failed boards nor will a

Failure Analysis be performed.

LIFE SUPPORT POLICY

Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unless a specific written agreement pertaining to

such intended use is executed between the manufacturer and an officer of IDT.

1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform,

when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user.

2. A critical component is any components of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device

or system, or to affect its safety or effectiveness.

IDT, the IDT logo, and Integrated Device Technology are trademarks or registered trademarks of Integrated Device Technology, Inc.

Notes

EB8T5A Eval Board Manual i July 23, 2009

Table of Contents

Description of the EB8T5A Eval Board

Introduction .....................................................................................................................................1-1

Board Features ...............................................................................................................................1-2

Hardware ................................................................................................................................1-2

Software..................................................................................................................................1-2

Other.......................................................................................................................................1-2

Revision History..............................................................................................................................1-3

Installation of the EB8T5A Eval Board

EB8T5A Installation ........................................................................................................................2-1

Hardware Description .....................................................................................................................2-1

Host System ...........................................................................................................................2-1

Reference Clocks............................................................................................................................2-1

Power Sources................................................................................................................................2-3

External Power Source...........................................................................................................2-3

Vaux Support..........................................................................................................................2-4

PCI Express Serial Data Transmit Termination Voltage Converter........................................2-6

PCI Express Digital Power Voltage Converter........................................................................2-6

PCI Express Analog Power Voltage Converter ......................................................................2-6

Core Logic Voltage Converter ................................................................................................2-6

3.3V I/O Power Module...........................................................................................................2-6

Power-up Sequence ...............................................................................................................2-6

Required Jumpers ..................................................................................................................2-6

Reset...............................................................................................................................................2-6

Fundamental Reset ................................................................................................................2-6

Downstream Reset .................................................................................................................2-7

Boot Configuration Vector...............................................................................................................2-7

SMBus Interfaces............................................................................................................................2-8

SMBus Slave Interface ...........................................................................................................2-8

SMBus Master Interface .......................................................................................................2-10

JTAG Header................................................................................................................................ 2-10

Attention Buttons...........................................................................................................................2-11

Miscellaneous Jumpers, Headers................................................................................................. 2-11

LEDs .............................................................................................................................................2-12

PCI Express Connectors...............................................................................................................2-14

EB8T5A Board Figure...................................................................................................................2-16

Software for the EB8T5A Eval Board

Introduction .....................................................................................................................................3-1

Device Management Software........................................................................................................3-1

Schematics

Schematics .....................................................................................................................................4-1

IDT Table of Contents

EB8T5A Eval Board Manual ii July 23, 2009

Notes

EB8T5A Eval Board Manual iii July 23, 2009

List of Tables

Table 2.1 Clock Source Selection .......................................................................................................2-1

Table 2.2 Clock Frequency Selection .................................................................................................2-2

Table 2.3 Spread Spectrum Clock Selection ......................................................................................2-2

Table 2.4 SMA Connectors - Onboard Reference Clock ....................................................................2-2

Table 2.5 External Power Connector - J4 ...........................................................................................2-3

Table 2.6 Downstream Reset Selection .............................................................................................2-7

Table 2.7 Boot Configuration Vector Signals ......................................................................................2-7

Table 2.8 Boot Configuration Vector Switches S3, S4, and S5 (ON=0, OFF=1) ................................2-8

Table 2.9 Slave SMBus Interface Connector ......................................................................................2-9

Table 2.10 SMBus Slave Interface Address Configuration ...................................................................2-9

Table 2.11 PES8T5A SMBus Slave Interface Address Setting ............................................................2-9

Table 2.12 EEPROM SMBus Address Setting ...................................................................................2-10

Table 2.13 JTAG Connector Pin Out ..................................................................................................2-11

Table 2.14 Attention Buttons ..............................................................................................................2-11

Table 2.15 Miscellaneous Jumpers, Headers .....................................................................................2-11

Table 2.16 LED Indicators .................................................................................................................. 2-13

Table 2.17 PCI Express x4 Connector Pinout ....................................................................................2-14

Table 2.18 PCI Express x1 Connector Pinout ....................................................................................2-15

IDT List of Tables

EB8T5A Eval Board Manual iv July 23, 2009

Notes

EB8T5A Eval Board Manual v July 23, 2009

List of Figures

Figure 1.1 Function Block Diagram of the EB8T5A Eval Board ..........................................................1-1

Figure 2.1 Clock Distribution Block Diagram .......................................................................................2-3

Figure 2.2 Power Distribution Block Diagram ......................................................................................2-4

Figure 2.3 APWRDIS# Timing ............................................................................................................2-5

Figure 2.4 APWRDIS# Timing Circuit .................................................................................................2-5

IDT List of Figures

EB8T5A Eval Board Manual vi July 23, 2009

Notes

EB8T5A Eval Board Manual 1 - 1 July 23, 2009

Chapter 1

Description of the EB8T5A

Eval Board

Introduction

In this manual, references to the PES8T5A also apply to the PES6T5 and PES5T5 unless otherwise

indicated.

The 89HPES8T5A switch (also referred to as PES8T5A in this manual) is a member of IDT’s PCI

Express® standard (PCIe®) based line of products. It is an 8-lane, 5-port switch. One upstream port is

provided for connecting to the root complex (RC), and up to four downstream ports are available for

connecting to PCIe endpoints or to another switch. More information on this device can be found in the

appropriate User Manual (89HPES8T5A, 89HPES6T5, or 89HPES5T5).

The 89EBPES8T5A Evaluation Board (also referred to as EB8T5A in this manual) provides an evalua-

tion platform for the PES8T5A switch. It is also a cost effective way to add a PCIe downstream port (x1) to

an existing system with a limited number of PCIe downstream ports. The EB8T5A eval board is designed to

function as an add-on card to be plugged into a x4 PCIe slot available on a motherboard hosting an appro-

priate root complex, microprocessor(s), and four downstream ports. The EB8T5A is a vehicle to test and

evaluate the functionality of the PES8T5A chip. Customers can use this board to get a headstart on soft-

ware development prior to the arrival of their own hardware. The EB8T5A is also used by IDT to reproduce

system-level hardware or software issues reported by customers. Figure 1.1 illustrates the functional block

diagram representing the main parts of the EB8T5A board.

Figure 1.1 Function Block Diagram of the EB8T5A Eval Board

JTAG

Header

Main

Reset

I/O Expander

PCA9555

PCIe x4 Upstream Edge

EEPROM

24LC512

SMBUS

HEADER

PES8T5A

PCI Express

Switch

External Power

PCIe x1 Downstream Slot

x4 (PES8T5A)

25 MHz

SSC Clock

Buffer

Clock

Fanout

SMBus

Voltages on board

+12V, +3.3V, +1.5V, +1.0V

Connector

Power

Module

PTH08T240

PCIe x1 Downstream Slot

x2 (PES6T5)

x1 (PES5T5)

IDT Description of the EB8T5A Eval Board

EB8T5A Eval Board Manual 1 - 2 July 23, 2009

Notes Board Features

Hardware

PCIe 5 port switch

– PES8T5A — Five ports (one x4 port and four x1 ports), 8 PCIe lanes

– PES6T5 — Five ports (one x2 port and four x1 ports), 6 PCIe lanes

– PES5T5 — Five ports (five x1 ports), 5 PCIe lanes

– PCIe Base Specification Revision 1.1 compliant

– Integrates eight 2.5 Gbps embedded SerDes

– Up to 256 byte maximum Payload Size

– Automatic lane reversal and polarity inversion supported on all lanes

– Automatic per port link width negotiation to x4, x2, x1

– Load configuration from an optional serial EEPROM via SMBUS

Upstream, Downstream Port

– One edge connector on the upstream port, to be plugged into a slot with at least x4 capable

mechanical slot connector on a host motherboard

– Four slot connectors on the downstream ports, for PCIe endpoint add-on cards to be plugged in.

Numerous user selectable configurations set using onboard jumpers and DIP-switches

– Source of clock - host clock or onboard clock generator

– Two clock rates and spread spectrum settings

– Boot mode selection

Vaux Support

SMBUS Slave Interface (4 pin header)

SMBUS Master Interface connected to the Serial EEPROMs through I/O expander

“Attention” button for each downstream port to initiate a hot swap event on each port

Four pin connector for optional external power supply

Push button for Warm Reset

Several LEDs to display status, reset, power, “Attention”, etc.

One 14-pin JTAG header

Software

There is no software or firmware executed on the board. However, useful software is provided along

with the Evaluation Board to facilitate configuration and evaluation of the PES8T5A within host systems

running popular operating systems.

Installation programs

– Operating Systems Supported: Windows2000, WindowsXP, Linux

GUI based application for Windows and Linux

– Allows users to view and modify registers in the PES8T5A

– Binary file generator for programming the serial EEPROMs attached to the SMBUS.

Other

A metal bracket is required to firmly hold in place the four endpoints plugged into the EB8T5A

board.

An external power supply may be required under some conditions.

SMBUS cable may be required for certain evaluation exercises.

SMA connectors are provided on the EB8T5A board for specific test points.

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