IDT 89EBPES12N3 Manual de usuario

November 2006

6024 Silver Creek Valley Road, San Jose,California 95138

Telephone: (800) 345-7015 • (408) 284-8200 • FAX: (408) 284-2775

Printed in U.S.A.

IDT™89EBPES12N3

Evaluation Board Manual

(Eval Board: 18-597-001)

DISCLAIMER

Integrated Device Technology, Inc. reserves the right to make changes to its products or specifications at any time, without notice, in order to improve design or performance

and to supply the best possible product. IDT does not assume any responsibility for use of any circuitry described other than the circuitry embodied in an IDT product. The

Company makes no representations that circuitry described herein is free from patent infringement or other rights of third parties which may result from its use. No license is

granted by implication or otherwise under any patent, patentrights or other rights, of Integrated Device Technology, Inc.

Boards that fail to function should be returned to IDT for replacement. Credit will not be given for the failed boards nor will a

Failure Analysis be performed.

LIFE SUPPORT POLICY

Integrated Device Technology's products are not authorized for use as critical components in life support devices or systems unlessa specific written agreementpertaining to

such intended use is executed between the manufacturer and an officer of IDT.

1. Life support devices or systems are devices or systems which (a) are intended for surgical implant into the body or (b) support or sustain life and whose failure to perform,

when properly used in accordance with instructions for use providedin the labeling, can be reasonably expected toresult in a significant injury to the user.

2.A criticalcomponentisany componentsof alifesupportdeviceor systemwhosefailure toperformcanbe reasonablyexpected to cause the failure of the life support device

or system, or to affect its safety or effectiveness.

IDT, theIDT logo, andIntegrated Device Technology are trademarks or registered trademarksof IntegratedDevice Technology, Inc.

Notes

EB12N3 Eval Board Manual (18-597-001) i November 2, 2006

Table of Contents

1 Description of the EB12N3 Eval Board

Introduction..................................................................................................................................1-1

Board Features............................................................................................................................1-2

Hardware............................................................................................................................1-2

Software.............................................................................................................................1-2

Other..................................................................................................................................1-2

Revision History...........................................................................................................................1-3

2 Installation of the EB12N3 Eval Board

EB12N3 Installation.....................................................................................................................2-1

Hardware Description..................................................................................................................2-1

Host System.......................................................................................................................2-1

Reference Clocks ........................................................................................................................2-3

Power Sources ............................................................................................................................2-4

External Power Source.......................................................................................................2-4

PCI Express Serial Data Transmit Termination Voltage Regulator.....................................2-4

PCI Express Digital Power Voltage Regulator....................................................................2-4

PCI Express Analog Power Voltage Regulator..................................................................2-4

Core Logic Voltage Regulator............................................................................................2-4

Required Jumpers..............................................................................................................2-4

Power Selection for Downstream Ports.......................................................................................2-5

Reset ...........................................................................................................................................2-6

Fundamental Reset............................................................................................................2-6

Downstream Reset.............................................................................................................2-6

Boot Configuration Vector............................................................................................................2-7

SMBus Interfaces ........................................................................................................................2-9

SMBus Slave Interface.......................................................................................................2-9

SMBus Master Interface...................................................................................................2-10

JTAG Header.............................................................................................................................2-12

Attention Buttons .......................................................................................................................2-12

LEDs..........................................................................................................................................2-12

PCI Express Connector.............................................................................................................2-13

Locations of Connectors, Jumpers, and Switches.....................................................................2-15

3 Software for the EB12N3 Eval Board

Introduction..................................................................................................................................3-1

Device Management Software.....................................................................................................3-1

4 Schematics

Schematics..................................................................................................................................4-1

IDT Table of Contents

EB12N3 Eval Board Manual (18-597-001) ii November 2, 2006

Notes

EB12N3 Eval Board Manual (18-597-001) iii November 2, 2006

List of Tables

Table 2.1 Clock Source Selection.....................................................................................................2-3

Table 2.2 Clock Frequency Selection...............................................................................................2-3

Table 2.3 Clock Spread Spectrum Selection....................................................................................2-3

Table 2.4 SMA Connectors - Onboard Reference Clock..................................................................2-3

Table 2.5 Power Connector Pin-Out.................................................................................................2-4

Table 2.6 Power Selection for Downstream Ports Jumpers, Headers..............................................2-5

Table 2.7 W13 Shunt Selection for Cold Reset................................................................................2-6

Table 2.8 W13 Shunt Selection for Warm Reset..............................................................................2-6

Table 2.9 Downstream Reset Selection ...........................................................................................2-7

Table 2.10 Boot Configuration Vector Signals....................................................................................2-7

Table 2.11 Boot Configuration Vector Switches.................................................................................2-8

Table 2.12 Slave SMBus Interface Connector....................................................................................2-9

Table 2.13 SMBus Slave Interface Address Configuration.................................................................2-9

Table 2.14 PES12N3 SMBus Slave Interface Address Setting........................................................2-10

Table 2.15 I/O Expander Address Setting........................................................................................2-11

Table 2.16 EEPROM SMBus Address Setting.................................................................................2-11

Table 2.17 Required EEPROM Headers..........................................................................................2-11

Table 2.18 JTAG Connector Pin Out................................................................................................2-12

Table 2.19 Attention Buttons ...........................................................................................................2-12

Table 2.20 LED Status Indicators.....................................................................................................2-12

Table 2.21 PCI Express Connector Pin-Out.....................................................................................2-13

IDT List of Tables

EB12N3 Eval Board Manual (18-597-001) iv November 2, 2006

Notes

EB12N3 Eval Board Manual (18-597-001) iii November 2, 2006

List of Figures

Figure 1.1 Functional Block Diagram of the EB12N3 Eval Board......................................................1-1

Figure 2.1 SuperMicro X6DH8-G2 Motherboard...............................................................................2-2

IDT List of Figures

EB12N3 Eval Board Manual (18-597-001) iv November 2, 2006

Notes

EB12N3 Eval Board Manual (18-597-001) 1 - 1 November 2, 2006

Chapter 1

Description of the EB12N3

Eval Board

Introduction

The 89HPES12N3 switch (also referred to as PES12N3 in this manual) is a member of IDT’s PCI

Express standard (PCIe) based line of products. It is a 3 port switch, with 4 serial lanes per port (x4). One

upstream port is provided for connecting to the root complex (RC), and two downstream ports areavailable

for connecting to PCIe endpoints or to another switch. More information on this device can be found in the

89HPES12N3 User Manual.

The 89EBPES12N3 Evaluation Board (also referred to as EB12N3 in this manual) provides an evalua-

tion platform for the PES12N3 switch. It is also a cost effective way to add a PCIe downstream port (x4) to

an existing system with a limited number of PCIe downstream ports. The EB12N3 eval board is designed to

function as an add-on card to beplugged into a x4 PCIe slot available on a motherboard hosting an appro-

priate root complex andmicroprocessor(s). The EB12N3 is a vehicle to test and evaluatethe functionality of

the PES12N3 chip, and it can also play an important role for customers to get a headstart on software

development while they await the arrival of their own hardware. It is also used inside IDT to reproduce

system level hardware or software issues reported by customers. Figure 1.1 illustrates the functional block

diagram representing the main parts of the EB12N3 board.

Figure 1.1 Functional Block Diagram of the EB12N3 Eval Board

Voltages on board

+12 V

5 V

External Power

Connector

(optional)

+3.3 V

+1.5 V

+1.0 V

JTAG

Header

Main

Reset

I/O Expander

PCA9555

PCIe x4 Upstream Edge

24LC512

EPROM

SMBUS

HEADER

PES12N3

PCI Express

Switch

MIC2951B

Controller

Dual Power

PCIe x4 Downstream Slot

25 MHz

SSC Clock

Buffer

Clock

Fanout HCSL CLK

SMBus

IDT Description of the EB12N3 Eval Board Board Features

EB12N3 Eval Board Manual (18-597-001) 1 - 2 November 2, 2006

Notes Board Features

Hardware

PES12N3 PCIe 3 port switch

–Three x4 ports, 12 PCIe lanes

–PCIe Base Specification Revision 1.0a compliant

–48 Gbps aggregate switching capacity

–128 to 2048 byte maximum payload size

–Static lane reversal and polarity inversion supported on all lanes

–Automatic per port link width negotiation to x4, x2, x1

–Can load configuration from serial EEPROM via SMBUS

x4 PCIe Connectors

–One edge connector on the upstream port, to be plugged into a x4 slot on a host motherboard

–Two slot connectors on the downstream ports, for PCIe endpoint add-on cards to be plugged in

Numerous user selectable configurations set using onboard jumpers and DIP-switches

–Source of clock - host clock or onboard clock generator

–multiple clock rates and spread spectrum settings

–Boot mode selection

SMBUS Slave Interface (4 pin header)

SMBUS Master Interface connected to two optional Serial EEPROMs through I/O expander

–Facilitates testing with two different settings of initialization data witha simple changeof a jumper

–Only one EEPROM can be selectively connected to the SMBUS at a time

“Attention” button for each port to initiate a hot swap event on each port

4 pin connector for optional external power supply Push button for Warm Reset

Several LEDs to display status, reset, power, “Attention”, etc.

One 10 pin JTAG connector (pitch 2.54 mm x 2.54 mm)

Software

There is no software or firmware executed on the board. However, useful software is provided along

with the Evaluation Board to facilitate configuration and evaluation of the PES12N3 within host systems

running popular operating systems.

Installation programs

–Operating Systems Supported: Windows2000, WindowsXP, Linux

GUI based application for Windows and Linux

–Allows users to view and modify registers in thePES12N3

–Binary file generator for programming the serial EEPROMs attached to the SMBUS

Other

A metal bracket is required to hold firmly in place the two endpoints plugged into the EB12N3 board.

An external power supply may be required under some conditions.

SMBUS cable may be required for certain evaluation exercises.

SMA connectors are provided on the EB12N3 board for specific test points.

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