Hadaru HPM103H-6 Manual de usuario
CONFIDENTIAL 1 페이지 2005-06-08
GPS Engine Module
HPM103H-6 GPS Receiver
REV 1.10
HPM103H-6
CONFIDENTIAL 2 페이지 2005-06-08
CONTENTS
1. SYSTEM DESCRIPTION ............................................................................... 3
1.1 General Description........................................................................ 3
1.2 Physical specification...................................................................... 3
1.3 Technical specification…………………………………………..……………….. 4
1.4 Block diagram................................................................................. 4
2. MECHANICAL SPECIFICATION.................................................................... 5
2.1 Pictures.......................................................................................... 5
2.2 Pin Configuration……………….......................................................... 6
3. EXTERNAL INTERFACES............................................................................. 7
3.1 System connector.......................................................................... 7
3.2 Reset............................................................................................ 10
3.3 UART interface.............................................................................. 10
3.4 GPIO interface.............................................................................. 11
3.5 RF-interface ................................................................................. 12
3.6 Interfacing considerations.............................................................13
4. APPLICATION NOTES FOR HPM103H-6..................................................... 15
4.1 External Interfaces ...................................................................... 15
4.2 Antenna issues.............................................................................. 15
4.3 Application Circuit......................................................................... 17
HPM103H-6
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1. SYSTEM DESCRIPTION
1.1 General Description
A complete GPS receiver is implemented on the HPM103H-6 module. The module
includes the following features:
z25.4x25.4mm form factor
zInput for Active GPS antenna bias supply
z16.3676MHz TCXO
zGPS radio based on uN8021 RF chip
zGPS base-band processor based on uN8031 chip
zDual UART (3V CMOS levels) for serial data
zSPI-interface (option)
z16-bit GPIO interface
z32768Hz RTC
z16Mbit FLASH memory (1024k x 16bit)
The receiver needs only the following external inputs:
zRegulated 2.7 ~ 3.3V supply
zActive GPS antenna bias supply (if needed)
zExternal reset input
zGPS Antenna signal (passive or active antenna)
1.2 Physical specification
zSize: 25.4 x 25.4 x 3.0 mm
zOperating Temperature: -40 ºC to +85 ºC
zOperating Humidity: 0% to 95% RH, non condensing
zVibration: 4 G
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1.3 Technical specification
zReceiver: L1, C/A code
zChannels: 12
zUpdate rate: 1 Hz or user configurable
zAGC Range: 0…+32dB external gain
zPower supply: 2.7 ~ 3.3V, regulated power
zRecommended Supply: 3.0 V
zTTFF: Hot Start: 8.6 sec typ
Warm Start: 38 sec typ
Cold Start: 53 sec typ
zSensitivity: - 138 dBm (Acquisition)
- 150.5 dBm (Navigation)
- 152 dBm (Tracking)
zPower Consumption: Navigating: 130mW @ 2.7V ave.
Idle mode(Navigation stopped): 22mW @2.7V typ.
Sleep mode: 120µW @ 2.7V typ.
RTC Back-Up mode: 1.5 uA max
zProtocols: NMEA-0183 V3.0, proprietary iTALK binary protocol
1.4 Block diagram
Figure 1 Block diagram of HPM103H-6 GPS receiver
HPM103H-6
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2. MECHANICAL SPECIFICATION Pictures
2.1 Pictures
Figure 2 HPM103H-6 modules w/ shield
Figure 3 HPM103H-6
, Top view w/o shield
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2.2 HPM103H-6 Pin Configurations
Figure 4 Pin Configuration
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3. EXTERNAL INTERFACES
3.1 System connector
zRFInput A
zGPIO[0..15] GPIO-lines I/O
zUART ports PORT0 and PORT1 UART ports I/O
zXRESET External reset (active low) I
zSupply voltage S
zV_ANTENNA External antenna bias S
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Table 1 System connector
HPM103H-6
PIN I/O Note
1 VCC Input Supply Voltage
2 GND Input Power and signal ground
3 GPIO15 Input Boot Mode Select (2)
4 RXD0 Input UART Port 0, Receive Data (3)
5 TXD0 Output UART Port 0, Transmit Data
6 TXD1 Output UART Port 1, Transmit Data
7 RXD1 Input UART Port 1, Receive Data (3)
8 GPIO3 I/O General Purpose I/O (1)
9 RF_ON Output High if VCC_RF is on
10 GND Power and signal ground
11 GND Power and signal ground
12 GND Power and signal ground
13 GND Power and signal ground
14 GND Power and signal ground
15 GND Power and signal ground
16 GND Power and signal ground
17 RF Input RF input, 50 ohm
18 GND Power and signal ground
19 V_ANTENNA Input Leave unconnected if not used
20 VCC_RF Output Can be used as power supply
for an active antenna
21 V_Bat Input Backup voltage supply for RTC
22 XRESET Input Active low reset (4)
23 GPIO10 I/O General Purpose I/O (1)
24 GPIO6 I/O General Purpose I/O (1)
25 GPIO5 I/O General Purpose I/O (1)
26 GPIO7 I/O General Purpose I/O (1)
27 GPIO0 I/O General Purpose I/O (1)
28 GPIO1 I/O General Purpose I/O (1)
29 GPIO4 I/O General Purpose I/O (1)
30 GND Power and signal ground
31 GPIO12 I/O General Purpose I/O (1)
SPI Interface Data In (Option) (5)
32 GPIO13 I/O LNA control (0:LNA ON, 1:LNA OFF)
33 GPIO14 I/O General Purpose I/O (1)
34 NC NC
35 GPIO2 I/O General Purpose I/O (1)
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36 GPIO9 I/O RTC Chip Control (SDA)
37 GPIO8 I/O RTC Chip Control (SCL)
38 GPIO11 I/O Wake-UP (1)
Notes:
(1): The base-band processor uN8031 includes a keeper so that no external pull
down or pull up resistor is needed. VIH min = 0.7 x VBB, VIL max = 0.3
x VBB. When the GPIO is configured as an input (e.g. External Wake-up
GPIO11), the drive impedance should be less than 10kohm in order to
change the state.
(2): HPM103H-6 module contains internal 100k pull up resistor to VCC. VIH min =
0.7 x VCC, VIL max = 0.3 x VCC. The base-band processor uN8031
includes also a keeper and the drive impedance should be less than
10kohm in order to change the state.
(3): The base-band processor uN8031 includes an internal 100k pull up resistor to
VCC (no keeper). VIH min = 0.7 x VCC, VIL max = 0.3 x VCC.
(4): HPM103H-6 module contains internal 10k pull up resistor to VCC. VIH min =
0.7 x VCC, VIL max = 0.3 x VCC.
(5): The base-band processor uN8031 includes an internal 10k pull up resistor to
VCC (no keeper). VIH min = 0.7 x VCC, VIL max = 0.3 x VCC.
Some of the inputs of the uN8031 include a pull-up or a pull-down resistor or a keeper;
therefore external resistors to the HPM103H-6 are not required. Unused pins can be
left unconnected.
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3.2 Reset
NOTE
HPM103H-6 requires an external Power-On-Reset (POR) circuit which
provides a reset pulse at XRESET-pin after the supply voltages are
connected. The reset pulse should be active (low state) at least 100ms after
power-up.
3.3 UART interface
Two asynchronous UART ports are available for serial interfacing. The baud rates are
fully programmable.
The data format is however fixed: x, N, 8, 1, i.e. x baud, No parity, eight data bits and
1 stop bit. No other data formats are supported. LSB is sent first. CMOS signal levels
are used.
Parity: N
Data Bits: 8
Stop bits: 1
Figure 7 UART Data format.
The UART ports are named PORT0 and PORT1. PORT0 is used e.g. for booting. PORT1
can be utilized for the emulator or NMEA interface.
HPM103H-6
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