Goodix GR551 Series Manual de instrucciones

GR551x Hardware Design Guidelines

Version: 2.1

Release Date: 2021-06-15

Shenzhen Goodix Technology Co., Ltd.

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Preface

Purpose

This document is to present the necessary circuit required for proper operation of GR551x Bluetooth System-on-Chips

(SoCs). Recommended schematic, chip interfaces, peripherals, schematic diagram, and PCB layout guidelines of the

GR551x SoC family are provided.

This Hardware Design Guidelines intends to help system designers build minimal Bluetooth Low Energy (Bluetooth LE)

hardware circuits and develop products.

Audience

This document is intended for:

• GR551x user

• GR551x tester

• Bluetooth product engineer

• Bluetooth LE system designer

Release Notes

This document is the eighth release of GR551x Hardware Design Guidelines, corresponding to GR551x SoC series.

Revision History

Version Date Description

1.0 2019-12-08 Initial release

1.3 2020-03-16 Updated the package pinout diagrams to the top views in “Pinout”.

1.5 2020-05-30

•Updated chip model numbers and pinout diagrams, package size diagrams, and reference

schematic diagrams;

•Changed power supplies and RF and explained by taking a QFN56 circuit as an example;

•Added “PCB Layout Reference Design”; updated “ESD Considerations”.

1.6 2020-06-30

•Updated the package layouts and data in the Appendix;

•Changed the maximum supply voltage from 4.38 V to 3.8 V; changed I/O voltage from 3.6 V

to 3.3 V (typical value).

•Added “Solutions for Improving ESD Protection Level on Products” by introducing the

hardware watchdog timer; added “Two-layer PCBs in QFN56”.

1.7 2020-08-30

Introduced the GR5515I0ND SoC:

•Added “GR5515I0ND” for pinout details;

•Added “External Flash” to describe recommended external Flash for GR5515I0ND;

•Added the reference schematic for GR5515I0ND in “Reference Design”;

Preface

Version Date Description

•Added “For External Flash Connection on GR5515I0ND” as reference design.

1.8 2020-11-27 Polished descriptions in "GR551x Overview" and "Pinout".

1.9 2021-03-03

•Updated description on the TEST_MODE pin; introduced the number of I/O pins in “GR551x

Overview”;

•Added description on PWM configuration in "I/O Pins";

•Updated the recommended Flash models for GR5515I0ND in "External Flash";

•Updated description on I/O voltage of GR5515I0ND;

•Changed the previous “ESD Considerations” into “ESD Protection Design” and updated

contents in this section.

2.0 2021-04-29

•Updated description on I/O voltage of GR5515I0ND in “Power Supply” and “FAQ”.

•Updated descriptions in “Power Supply Scheme”, “Power Supply”, “Clock”, “ESD Schematic

Design”, “PCB Layout Design” and “Two-layer PCBs in QFN Packages”.

2.1 2021-06-15

Add a note of not recommended for new designs for GR5515RGBD.

Updated the recommended external flash models for GR5515I0ND.

Contents

Preface.................................................................................................................................................................... I

1 GR551x Overview................................................................................................................................................1

1.1 Features............................................................................................................................................................... 1

1.2 Block Diagram......................................................................................................................................................3

2 Pinout................................................................................................................................................................. 5

2.1 GR5515IGND QFN56............................................................................................................................................5

2.2 GR5515I0ND QFN56............................................................................................................................................ 8

2.3 GR5515RGBD BGA68 (NRND)............................................................................................................................12

2.4 GR5515GGBD BGA55.........................................................................................................................................15

2.5 GR5513BEND QFN40......................................................................................................................................... 18

3 Minimal Design for GR551x SoC........................................................................................................................22

3.1 Schematic Design Guideline.............................................................................................................................. 22

3.1.1 Power Supply............................................................................................................................................ 22

3.1.1.1 Introduction......................................................................................................................................22

3.1.1.2 Power Supply Scheme......................................................................................................................23

3.1.1.3 I/O LDO.............................................................................................................................................25

3.1.2 Clock..........................................................................................................................................................27

3.1.2.1 Introduction......................................................................................................................................27

3.1.2.2 32 MHz Clock (XO)........................................................................................................................... 27

3.1.2.3 32.768 kHz Clock..............................................................................................................................28

3.1.3 RF.............................................................................................................................................................. 29

3.1.3.1 Introduction......................................................................................................................................29

3.1.3.2 RF Scheme........................................................................................................................................29

3.1.4 I/O Pins..................................................................................................................................................... 30

3.1.5 SWD Interfaces..........................................................................................................................................30

3.1.6 External Flash............................................................................................................................................31

3.2 PCB Design and Layout Guideline..................................................................................................................... 31

3.2.1 PCB Layer Stackup.................................................................................................................................... 32

3.2.2 Components Layout.................................................................................................................................. 32

3.2.3 Power Supply............................................................................................................................................ 33

3.2.3.1 DC-DC Switching Regulator.............................................................................................................. 33

3.2.3.2 RF Input Power Supply.....................................................................................................................34

3.2.4 Clock..........................................................................................................................................................35

3.2.5 RFIO Port...................................................................................................................................................36

3.2.6 Grounding................................................................................................................................................. 37

3.2.7 ESD Protection Design.............................................................................................................................. 37

3.2.7.1 System-level ESD Design.................................................................................................................. 38

3.2.7.2 ESD Considerations in Production, Transport, and Debugging........................................................ 43

Contents

4 Reference Design...............................................................................................................................................44

4.1 Reference Schematic Diagram...........................................................................................................................44

4.2 PCB Layout Reference Design............................................................................................................................48

4.2.1 Four-layer PCBs in QFN56 Package...........................................................................................................48

4.2.2 Two-layer PCBs in QFN Packages..............................................................................................................51

4.2.3 External Flash Connection for GR5515I0ND.............................................................................................52

4.2.4 Four-layer PCBs in BGA68 Package(NRND)...............................................................................................53

5 FAQ................................................................................................................................................................... 56

5.1 Can the Voltages of All GR551x I/O Pins Be Set to 3.3 V?................................................................................56

5.2 Why Is the Power Consumption in GR551x Sleep Modes High?...................................................................... 56

5.3 Can the RF PI Circuits Be Simplified or Removed?........................................................................................... 57

6 Glossary and Abbreviations...............................................................................................................................58

7 Appendix: QFN and BGA Assembly Guideline................................................................................................... 59

7.1 Package Information..........................................................................................................................................60

7.1.1 GR5515IGND/GR5515I0ND QFN56........................................................................................................... 60

7.1.2 GR5515RGBD BGA68 (NRND)................................................................................................................... 62

7.1.3 GR5515GGBD BGA55................................................................................................................................ 64

7.1.4 GR5513BEND QFN40................................................................................................................................ 66

7.2 Board Mounting Guideline................................................................................................................................ 68

7.2.1 Stencil Design for Perimeter Pads............................................................................................................ 68

7.2.2 Via Types and Solder Voiding................................................................................................................... 69

7.2.2.1 Stencil Thickness and Solder Paste.................................................................................................. 69

7.2.2.2 PCB Materials................................................................................................................................... 69

7.2.3 SMT Printing Process................................................................................................................................ 70

7.3 SMT Reflow Process.......................................................................................................................................... 70

7.4 Rework Guideline.............................................................................................................................................. 72

7.4.1 Component Removal................................................................................................................................ 73

7.4.2 Site Redress...............................................................................................................................................73

7.4.3 Solder Paste Printing.................................................................................................................................73

7.4.4 Component Placement............................................................................................................................. 74

7.4.5 Component Attachment........................................................................................................................... 74

7.5 RoHS Compliant.................................................................................................................................................74

7.6 SVHC Materials (REACH)....................................................................................................................................74

7.7 Halogen Free......................................................................................................................................................74

GR551x Overview

1 GR551x Overview

The Goodix GR551x family is a single-mode, low-power Bluetooth 5.1 System-on-Chip (SoC). It can be configured as a

Broadcaster, an Observer, a Central, or a Peripheral and supports the combination of all the above roles, making it an

ideal choice for Internet of Things (IoT) and smart wearable devices.

Based on ARM® Cortex®-M4F CPU core, the GR551x integrates Bluetooth 5.1 Protocol Stack, a 2.4 GHz RF transceiver,

on-chip programmable Flash memory, RAM, and multiple peripherals.

The GR551x series includes GR5515IGND, GR5515RGBD, GR5515GGBD, GR5513BEND and GR5515I0ND.

Table 1-1 GR551x series

GR551x Series GR5515IGND GR5515RGBD GR5515GGBD GR5513BEND GR5515I0ND

CPU Cortex®-M4F Cortex®-M4F Cortex®-M4F Cortex®-M4F Cortex®-M4F

RAM 256 KB 256 KB 256 KB 128 KB 256 KB

Flash 1 MB 1 MB 1 MB 512 KB N/A

Package (mm) QFN56

(7 x 7 x 0.75)

BGA68

(5.3 x 5.3 x 0.88)

BGA55

(3.5 x 3.5 x 0.60)

QFN40

(5 x 5 x 0.75)

QFN56

(7 x 7 x 0.75)

I/O Number 39 39 29 22 39

Note:

The GR5515RGBD is not recommended for new designs.

1.1 Features

• A Bluetooth Low Energy (Bluetooth LE) 5.1 transceiver integrates Controller and Host layers

◦ Supported data rates: 1 Mbps, 2 Mbps, Long Range 500 kbps, Long Range 125 kbps

◦ TX power: -20 dBm to +7 dBm

◦ -97 dBm sensitivity (in 1 Mbps mode)

◦ -93 dBm sensitivity (in 2 Mbps mode)

◦ -99.5 dBm sensitivity (in Long Range 500 kbps mode)

◦ -103 dBm sensitivity (in Long Range 125 kbps mode)

◦ TX current: 3.05 mA @ 0 dBm, 1 Mbps

◦ RX current: 3.9 mA @ 1 Mbps

•ARM® Cortex®-M4F 32-bit micro-processor with floating point support

◦ Maximum frequency: 64 MHz

◦ Power consumption: 30 µA/MHz

• Memory

GR551x Overview

◦ 256 KB RAM with retention (four 8 KB RAM blocks and seven 32 KB RAM blocks) for GR5515 series SoCs,

and 128 KB RAM with retention (four 8 KB RAM blocks and three 32 KB RAM blocks) for the GR5513 SoC.

◦ 1 MB Flash for GR5515 series SoCs (The GR5515I0ND SoC uses external QSPI Flash with various model

options.) and 512 KB Flash for the GR5513 SoC.

• Power management

◦ On-chip DC-DC Converter

◦ On-chip I/O LDO to provide I/O voltage and supply external components

◦ Supply voltage: 1.7 V to 3.8 V (The supply voltage of the GR5515I0ND SoC is equal to the working voltage of

external SPI Flash.)

◦ I/O voltage: 1.8 V to 3.3 V (Typical) (On GR5515I0ND, VDDIO0 is bonded to VIO_LDO_OUT internally and

I/O LDO is set to off mode in the application firmware by default, so VIO_LDO_OUT shall be connected to

VBATL.)

◦ OFF mode: 0.15 µA (Typical); nothing is on except VBAT, chip in reset mode

◦ Ultra deep sleep mode: 0.65 µA (Typical); I/O LDO off, no memory retention. Wake-up on an external GPIO

or an internal Timer.

◦ Sleep mode: 1.3 µA (Typical); Bluetooth LE link alive, I/O LDO off, supporting AON_RTC, AON GPIO and

Bluetooth LE Event, memory retention and wake-up on an external GPIO or an internal Timer.

• Peripherals

◦ 2 x QSPI interfaces, up to 32 MHz

◦ 2 x SPI interfaces (1 SPI Master Interface with 2 slave CS pins + 1 SPI Slave Interface), up to 32 MHz

◦ 2 x I2C interfaces at 100 kHz, 400 kHz, 1 MHz, 2 MHz

◦ 2 x I2S interfaces (1 I2S Master Interface + 1 I2S Slave Interface)

◦ 2 x UART interfaces, one with DMA channel.

◦ 13-bit ADC, up to 1 Msps, 8 channels (5 external test channels and 3 internal signal channels), supporting

both single-ended and differential inputs

◦ ISO 7816 interface

◦ 6-channel PWM

◦ Built-in temperature and voltage sensors

◦ 4 x Hardware timers

◦ 1 x AON hardware timer

◦ 2 x Watchdog timers(1 System Watchdog Timer and 1 Always-on watchdog timer)

◦ Calendar timer

◦ Wake-up comparator

GR551x Overview

◦ Up to 39 multiplexed GPIO pins

• Security

◦ Complete secure computing engine:

- AES 128-bit/192-bit/256-bit symmetric encryption (ECB, CBC)

- Keyed Hash Message Authentication Code (HMAC)

- PKC

- TRNG

◦ Comprehensive security operation mechanism:

- Secure boot

- Encrypted firmware runs directly from Flash

- eFuse for encrypted key storage

- Differentiate application data key and firmware key, supporting one data key per device/product

• Packages

◦ QFN56: 7 mm x 7 mm

◦ BGA68: 5.3 mm x 5.3 mm

◦ BGA55: 3.5 mm x 3.5 mm

◦ QFN40: 5 mm x 5 mm

• Operating temperature range: -40°C to +85°C

1.2 Block Diagram

The block diagram of GR551x is shown in the figure below.

GR551x Overview

PMU Subsystem

Bluetooth Subsystem

RF Transceiver Communicaon Core

PLL

Mixer

CLK

Gen.

Dig.Front End Bluetooth LE

Modem

Bluetooth LE

MAC Packet Buﬀer

DC/DC

LP LDO

Sleep Osc.

RTC

Power

Sequencer

MCU Subsystem

SRAM

ROM

Security

Cores

Memory/State

Retenon

Wake up

LP Comp.

Always-On

Domain

Flash

Cache

Cache Ctrl. Flash & XIP

Ctrl.

ARM®Cortex®-

M4F

BB ADC

System

WDT.

Dual.

Timer

TimerQSPI

I2S

ADC

GPIO

UART

PWM

SPI

I2C

ISO781

LNA

Figure 1-1 GR551x block diagram

Note:

For more details of each module in this block diagram, see GR551x Datasheet.

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