Force Computers SYS68K/CPU-40 Manual de usuario

P/N 202368

FORCE COMPUTERS Inc./GmbH

This document shall not be duplicated, nor its contents used

for any purpose, unless express permission has been granted.

SYS68K/CPU-40/41

User’s Manual

Edition No. 8

February 1997

INTRODUCTION

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TABLE OF CONTENTS

1. GENERAL INFORMATION ........................................... 1-1

1.1 Features of the CPU Board ........................................... 1-4

2. THE PROCESSOR ................................................. 2-1

2.1 The CPU 68040 ................................................... 2-1

2.2 The Shared RAM .................................................. 2-3

2.2.1 The DRM-01/4 ..................................................... 2-3

2.2.2 The DRM-01/16 .................................................... 2-4

2.2.3 The SRM-01/4 ..................................................... 2-5

2.2.4 The SRM-01/8 ..................................................... 2-6

2.3 The System EPROM ................................................ 2-7

2.4 The Local SRAM ................................................... 2-7

2.5 The Local FLASH EPROM ........................................... 2-7

2.6 The Boot EPROM .................................................. 2-7

2.7 The FGA-002 ..................................................... 2-8

2.8 The PI/T 68230 .................................................... 2-9

2.8.1 The I/O Configuration of PI/T1 ........................................ 2-10

2.8.2 The I/O Configuration of PI/T2 ........................................ 2-10

2.9 The Real Time Clock 72423 ......................................... 2-11

2.10 The DUSCC 68562 ................................................ 2-12

2.10.1 The I/O Configuration of DUSCC1 and DUSCC2 .......................... 2-13

2.11 The EAGLE Modules ............................................... 2-15

2.12 The VMEbus Interface .............................................. 2-15

2.13 The Monitor of the CPU board ........................................ 2-17

2.14 Default Jumper Settings on the CPU Board .............................. 2-18

3. SPECIFICATIONS OF THE CPU BOARD ................................ 3-1

4. ORDERING INFORMATION .......................................... 4-1

5. HISTORY OF MANUAL REVISIONS .................................... 5-1

LIST OF FIGURES

Figure 1-1: Photo of the CPU Board ............................................. 1-2

Figure 1-2: Block Diagram of the CPU Board ...................................... 1-3

Figure 2-1: Location Diagram for All Jumperfields ................................. 2-20

Figure 2-2: The Front Panel of the CPU Board .................................... 2-21

LIST OF TABLES

Table 1-1: The Memory Map .................................................. 1-6

Table 1-2: The Base Addresses of the Local I/O Devices ............................. 1-7

iii

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SECTION 1 INTRODUCTION

1-1

1. GENERAL INFORMATION

This CPU board is a high performance single board computer based on the 68040 microprocessor and the

VMEbus. The board incorporates a modular I/O subsystem which provides a high degree of flexibility for

a wide variety of applications. The CPU board can be used with or without an I/O subsystem, called an

"EAGLE" module.

The board is able to hold a RAM Module which can be DRAM (CPU-40) or SRAM (CPU-41) based.

The CPU-40/41 family design utilizes all of the features of the powerful FORCE Gate Array (FGA-002).

Among its features is a 32-bit DMA controller which supports local (shared) memory, VMEbus and I/O data

transfers for maximum performance, parallel real time operation and responsiveness.

The EAGLE modules are installed on the CPU board via the FLXi (FORCE Local eXpansion interface). This

provides a full 32-bit interface between the base board and the EAGLE module I/O subsystem, providing

a range of I/O options.

Four multiprotocol serial I/O channels, a parallel I/O channel and a Real Time Clock with on-board battery

backup are installed on the base board which, in combination with EAGLE modules, make the CPU board

a true single board computer system.

A broad range of operating systems and kernels is available for the CPU board. However, as with all

FORCE COMPUTERS' CPU cards, VMEPROM firmware is provided with the board at no extra cost.

VMEPROM is a Real Time Kernel and is installed on the CPU board in the two16-bit wide EPROM sockets,

which results in a 32-bit wide System EPROM area. This ensures that the board is supplied ready to use.

SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS

1-2

Figure 1-1: Photo of the CPU Board

SECTION 1 INTRODUCTION

1-3

Figure 1-2: Block Diagram of the CPU Board

SYS68K/CPU-40/41 USER'S MANUAL FORCE COMPUTERS

1-4

1.1 Features of the CPU 3Board

68040 microprocessor: 25.0 MHz on CPU-40B/41B/x

68040 microprocessor: 33.0 MHz on CPU-40D/41D/x

Shared DRAM Module: 4 Mbyte DRAM with Burst Read/Write and Parity Generation and

Checking (DRM-01/4)

16 Mbyte DRAM with Burst Read/Write and Parity Generation and

Checking (DRM-01/16)

Shared SRAM Module: 4 Mbyte SRAM with Burst Read/Write (SRM-01/4)

8 Mbyte SRAM with Burst Read/Write (SRM-01/8)

32-bit high speed DMA controller for data transfers to/from the shared RAM, VMEbus memory and

EAGLE modules; DMA controller is installed in the FGA-002.

Two system EPROM devices supporting 40-pin devices. Access from the 68040 using a 32-bit data

path

One boot EPROM for local booting, initialization of the I/O chips and configuration of the FGA-002

128 Kbyte SRAM with on-board battery backup

128 Kbyte FLASH EPROM

FLXi interface for installation of one EAGLE module

Four Serial I/O interfaces, configurable as RS232/RS422/RS485, available on the front panel

8-bit parallel interface with 4-bit handshake

Two 24-bit timers with 5-bit prescaler

One 8-bit timer

Real Time Clock with calendar and on-board battery backup

Full 32-bit VMEbus master/slave interface, supporting the following data transfer types:

A32, A24, A16 : D8, D16, D32 - Master

A32, A24 : D8, D16, D32 - Slave

UAT, RMW, ADO

FORCE Message Broadcast (FMB), two channels

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