Epson S1C31D50 Manual del propietario

Seiko Epson Corporation

S1C31D50TECHNICAL MANUAL

(Rev. 1.00)

CMOS 32-BIT SINGLE CHIP MICROCONTROLLER

S1C31D50

Technical Manual

Rev. 1.00

Seiko Epson Corporation

S1C31D50TECHNICAL MANUAL

(Rev. 1.00)

Evaluation board/kit and Development tool important notice

1. This evaluation board/kit or development tool is designed for use for engineering evaluation,

demonstration, or development purposes only. Do not use it for other purposes. It is not

intended to meet the requirements of design for finished products.

2. This evaluation board/kit or development tool is intended for use by an electronics engineer

and is not a consumer product. The user should use it properly and in a safe manner. Seiko

Epson dose not assume any responsibility or liability of any kind of damage and/or fire coursed

by the use of it. The user should cease to use it when any abnormal issue occurs even during

proper and safe use.

3. The part used for this evaluation board/kit or development tool may be changed without any

notice.

NOTICE

No part of this material may be reproduced or duplicated in any form or by any means without the

written permission of Seiko Epson. Seiko Epson reserves the right to make changes to this material

without notice. Seiko Epson does not assume any liability of any kind arising out of any inaccuracies

contained in this material or due to its application or use in any product or circuit and, further, there

is no representation that this material is applicable to products requiring high level reliability, such

as, medical products. Moreover, no license to any intellectual property rights is granted by

implication or otherwise, and there is no representation or warranty that anything made in

accordance with this material will be free from any patent or copyright infringement of a third party.

When exporting the products or technology described in this material, you should comply with the

applicable export control laws and regulations and follow the procedures required by such laws and

regulations. You are requested not to use, to resell, to export and/or to otherwise dispose of the

products (and any technical information furnished, if any) for the development and/or manufacture

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All brands or product names mentioned herein are trademarks and/or registered trademarks of

their respective companies.

Seiko Epson Corporation

S1C31D50TECHNICAL MANUAL

(Rev. 1.00)

Preface

This is a technical manual for designers and programmers who develop a product using the

S1C31D50. This document describes the functions of the IC, embedded peripheral circuit operations,

and their control methods.

Notational conventions and symbols in this manual

Peripheral circuit chapters do not provide control register addresses. Refer to “Peripheral Circuit

Area” in the “Memory and Bus” chapter or “List of Peripheral Circuit Control Registers” in the

Appendix.

In this manual, the register and control bit names are described as shown below to distinguish

from signal and pin names.

XXX register:

Represents a register including its all bits.

XXX.YYY bit:

Represents the one control bit YYY in the XXX register.

XXX.ZZZ[1:0] bits:

Represents the two control bits ZZZ1 and ZZZ0 in the XXX register

Initial:

Value set at initialization

Reset

Initialization condition. The initialization condition depends on the reset group (H0, H1, or

S0). For more information on the reset groups, refer to “Initialization Conditions (Reset

Groups)” in the “Power Supply, Reset, and Clocks” chapter.

R/W:

R =

Read only bit

W =

Write only bit

WP =

Write only bit with a write protection using the SYSPROT.PROT[15:0] bits

R/W =

Read/write bit

R/WP =

Read/write bit with a write protection using the SYSPROT.PROT[15:0] bits

(reserved): Reserved bit. Do not alter from the initial value.

Control bit read/write values

This manual describes control bit values in a hexadecimal notation except for one-bit values (and

except when decimal or binary notation is required in terms of explanation). The values are

described as shown below according to the control bit width.

Bit

0 or 1

to 4 bits

0x0 to 0xf

5 to 8 bits

0x00 to 0xff

9 to 12 bits

0x000 to 0xfff

13 to 16 bits

0x0000 to 0xffff

Decimal

0 to 9999...

Binary

0b0000... to 0b1111...

Channel number

Multiple channels may be implemented in some peripheral circuits (e.g., 16-bit timer, etc.). The

peripheral circuit chapters use ‘n’ as the value that represents the channel number in the register

and pin names regard- less of the number of channel actually implemented. Normally, the

descriptions are applied to all channels. If there is a channel that has different functions from others,

the channel number is specified clearly. Example) T16_nCTL register of the 16-bit timer

If one channel is implemented (Ch.0 only): T16_nCTL = T16_0CTL only

If two channels are implemented (Ch.0 and Ch.1): T16_nCTL = T16_0CTL and T16_1CTL

For the number of channels implemented in the peripheral circuits of this IC, refer to “Features” in

the “Overview” chapter.

Low power mode

This manual describes the low power modes as HALT mode and SLEEP mode. These terms refer

to sleep mode and deep sleep mode in the Cortex®-M0+ processor, respectively.

Seiko Epson Corporation 
S1C31D50TECHNICAL MANUAL 
(Rev. 1.00) 
 
 
Overview ________________________________________________________ 1-1 
1. Features___________________________________________________________ 1-1 
2. Block Diagram ______________________________________________________ 1-4 
3. 
Pins
_______________________________________________________________ 1-5 
3.1. Pin Configuration Diagram________________________________________________ 1-5 
3.2. PinDescriptions ________________________________________________________ 1-9 
Power Supply, Reset, and Clocks _____________________________________ 2-1 
1. Power Generator (PWGA)_____________________________________________ 2-1 
1.1. Overview______________________________________________________________ 2-1 
1.2. 
Pins
 __________________________________________________________________ 2-2 
1.3. VD1 Regulator Operation Mode ___________________________________________ 2-2 
1.4. VD1 Regulator Voltage Mode _____________________________________________ 2-3 
2. System Reset Controller (SRC) _________________________________________ 2-4 
2.1. Overview______________________________________________________________ 2-4 
2.2. Input Pin ______________________________________________________________ 2-4 
2.3. Reset Sources __________________________________________________________ 2-5 
2.4. Initialization Conditions(Reset Groups) ______________________________________ 2-6 
3. Clock Generator (CLG)________________________________________________ 2-7 
3.1. Overview______________________________________________________________ 2-7 
3.2. Input/Output Pins ______________________________________________________ 2-8 
3.3. Clock Sources __________________________________________________________ 2-9 
3.4. Operations ___________________________________________________________ 2-12 
4. Operating Mode ___________________________________________________ 2-18 
4.1. Initial Boot Sequence ___________________________________________________ 2-18 
4.2. Transition between Operating Modes______________________________________ 2-18 
5. Interrupts ________________________________________________________ 2-20 
6. Control Registers ___________________________________________________ 2-21 
CPU AND DEBUGGER ______________________________________________ 3-1 
1. Overview __________________________________________________________ 3-1 
2. CPU Core __________________________________________________________ 3-1 
3. Debugger__________________________________________________________ 3-1 
3.1. List of debugger input/output pins _________________________________________ 3-1 
3.2. External Connection _____________________________________________________ 3-1 
Memory and Bus__________________________________________________ 4-1 
1. Overview __________________________________________________________ 4-1 
2. Bus Access Cycle ____________________________________________________ 4-2 
3. Flash Memory ______________________________________________________ 4-3 
3.1. Flash Memory Pin _______________________________________________________ 4-3 
3.2. Flash Bus Access Cycle Setting _____________________________________________ 4-3 
3.3. Flash Programming ______________________________________________________ 4-3 

Seiko Epson Corporation 
S1C31D50TECHNICAL MANUAL 
(Rev. 1.00) 
 
 
4. RAM______________________________________________________________ 4-3 
5. Peripheral Circuit Control Registers _____________________________________ 4-4 
5.1. System-Protect Function _________________________________________________ 4-4 
6. Instruction Cache ___________________________________________________ 4-4 
7. Memory Mapped Access Area For External Flash Memory __________________ 4-4 
8. Control Registers ____________________________________________________ 4-5 
Interrupt ________________________________________________________ 5-1 
1. Overview __________________________________________________________ 5-1 
2. Vector Table________________________________________________________ 5-2 
2.1. Vector Table Offset Address (VTOR) _________________________________________ 5-5 
2.2. Priority of Interrupts_____________________________________________________ 5-5 
3. Peripheral Circuit Interrupt Control _____________________________________ 5-5 
4. 
NMI
 ______________________________________________________________ 5-5 
DMA Controller (DMAC) ____________________________________________ 6-1 
1. Overview __________________________________________________________ 6-1 
2. Operations_________________________________________________________ 6-2 
2.1. 
Initialization
____________________________________________________________ 6-2 
3. 
Priority
 ____________________________________________________________ 6-2 
4. Data Structure______________________________________________________ 6-2 
4.1. Transfer Source End Pointer _______________________________________________ 6-4 
4.2. Transfer Destination End Pointer ___________________________________________ 6-4 
4.3. Control Data ___________________________________________________________ 6-4 
5. DMA Transfer Mode _________________________________________________ 6-6 
5.1. Basic Transfer __________________________________________________________ 6-6 
5.2. Auto-Request Transfer ___________________________________________________ 6-6 
5.3. Ping-Pong Transfer ______________________________________________________ 6-7 
5.4. Memory Scatter-Gather Transfer __________________________________________ 6-8 
5.5. Peripheral Scatter-Gather Transfer ________________________________________ 6-11 
6. DMA Transfer Cycle_________________________________________________ 6-12 
7. Interrupts ________________________________________________________ 6-12 
8. Control Registers ___________________________________________________ 6-13 
I/O Ports (PPORT) _________________________________________________ 7-1 
1. Overview __________________________________________________________ 7-1 
2. I/O Cell Structure and Functions _______________________________________ 7-2 
2.1. Schmitt Input __________________________________________________________ 7-2 
2.2. Over Voltage Tolerant Fail-Safe Type I/O Cell _________________________________ 7-2 
2.3. Pull-Up/Pull-Down ______________________________________________________ 7-2 
2.4. CMOS Output and High Impedance State ___________________________________ 7-3 
3. Clock Settings ______________________________________________________ 7-3 
3.1. PPORT Operating Clock __________________________________________________ 7-3 
3.2. Clock Supply in SLEEP Mode_______________________________________________ 7-3 

Seiko Epson Corporation 
S1C31D50TECHNICAL MANUAL 
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3.3. Clock Supply During Debugging ____________________________________________ 7-3 
4. 
Operations
 _________________________________________________________ 7-4 
4.1. 
Initialization
____________________________________________________________ 7-4 
4.2. Port Input/Output Control________________________________________________ 7-6 
5. Interrupts _________________________________________________________ 7-7 
6. Control Registers ____________________________________________________ 7-8 
7. Control Register and Port Function Configuration of this IC __________________ 7-14 
7.1. P0 Port Group_________________________________________________________ 7-14 
7.2. P1 Port Group _________________________________________________________ 7-15 
7.3. P2 Port Group _________________________________________________________ 7-16 
7.4. P3 Port Group _________________________________________________________ 7-17 
7.5. P4 Port Group _________________________________________________________ 7-18 
7.6. P5 Port Group _________________________________________________________ 7-19 
7.7. P6 Port Group _________________________________________________________ 7-20 
7.8. P7 Port Group _________________________________________________________ 7-21 
7.9. P8 Port Group _________________________________________________________ 7-22 
7.10. P9 Port Group _________________________________________________________ 7-23 
7.11. PA Port Group_________________________________________________________ 7-24 
7.12. PD Port Group_________________________________________________________ 7-25 
7.13. Common Registers between Port Groups ___________________________________ 7-26 
Universal Port Multiplexer (UPMUX)__________________________________ 8-1 
1. Overview __________________________________________________________ 8-1 
2. Peripheral Circuit I/O Function Assignment _______________________________ 8-1 
3. Control Registers ____________________________________________________ 8-2 
Watchdog Timer (WDT2)____________________________________________ 9-1 
1. Overview __________________________________________________________ 9-1 
2. Clock Settings ______________________________________________________ 9-1 
2.1. WDT2 Operating Clock___________________________________________________ 9-1 
2.2. Clock Supply in DEBUG Mode _____________________________________________ 9-1 
3. Operations_________________________________________________________ 9-2 
3.1. WDT2 Control __________________________________________________________ 9-2 
3.2. Operations in HALT and SLEEP Modes _______________________________________ 9-3 
4. Control Registers____________________________________________________ 9-4 
Real-Time Clock (RTCA) __________________________________________ 10-1 
1. Overview _______________________________________________________ 10-1 
2. Output Pin and External Connection _________________________________ 10-1 
2.1. Output Pin____________________________________________________________ 10-1 
3. Clock Settings ___________________________________________________ 10-2 
3.1. RTCA Operating Clock __________________________________________________ 10-2 
3.2. Theoretical Regulation Function __________________________________________ 10-2 
4. Operations______________________________________________________ 10-4 

Seiko Epson Corporation 
S1C31D50TECHNICAL MANUAL 
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4.1. RTCA Control__________________________________________________________ 10-4 
4.2. Real-Time Clock Counter Operations ______________________________________ 10-5 
4.3. Stopwatch Control _____________________________________________________ 10-5 
4.4. Stopwatch Count-up Pattern_____________________________________________ 10-6 
5. Interrupts ______________________________________________________ 10-7 
6. Control Registers _________________________________________________ 10-8 
Supply Voltage Detector (SVD3)___________________________________ 11-1 
1. Overview _______________________________________________________ 11-1 
2. Input Pins and External Connection __________________________________ 11-2 
2.1. Input Pins ____________________________________________________________ 11-2 
2.2. External Connection ____________________________________________________ 11-2 
3. Clock Settings ___________________________________________________ 11-3 
3.1. SVD3 Operating Clock __________________________________________________ 11-3 
3.2. Clock Supply in SLEEP Mode______________________________________________ 11-3 
3.3. Clock Supply in DEBUG Mode ____________________________________________ 11-3 
4. Operations______________________________________________________ 11-4 
4.1. SVD3 Control__________________________________________________________ 11-4 
4.2. SVD3Operations_______________________________________________________ 11-4 
5. SVD3 Interrupt and Reset __________________________________________ 11-6 
5.1. SVD3 Interrupt ________________________________________________________ 11-6 
5.2. SVD3 Reset ___________________________________________________________ 11-6 
6. Control Registers _________________________________________________ 11-7 
16-bit Timers (T16) _____________________________________________ 12-1 
1. Overview _______________________________________________________ 12-1 
2. Input Pin _______________________________________________________ 12-1 
3. Clock Settings ___________________________________________________ 12-2 
3.1. T16 Operating Clock____________________________________________________ 12-2 
3.2. Clock Supply in SLEEP Mode______________________________________________ 12-2 
3.3. Clock Supply During Debugging ___________________________________________ 12-2 
3.4. Event Counter Clock ____________________________________________________ 12-2 
4. 
Operations
 ______________________________________________________ 12-3 
4.1. 
Initialization
___________________________________________________________ 12-3 
4.2. Counter Underflow ____________________________________________________ 12-3 
4.3. Operations in Repeat Mode _____________________________________________ 12-3 
4.4. Operations in One-shot Mode____________________________________________ 12-4 
4.5. Counter Value Read ____________________________________________________ 12-4 
5. Interrupt _______________________________________________________ 12-4 
6. Control Registers _________________________________________________ 12-5 
UART (UART3)__________________________________________________ 13-1 
1. Overview _______________________________________________________ 13-1 
2. Input/Output Pins and External Connections __________________________ 13-2 
2.1. List of Input/Output Pins ________________________________________________ 13-2 
2.2. ExternalConnections ___________________________________________________ 13-3 

Seiko Epson Corporation 
S1C31D50TECHNICAL MANUAL 
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2.3. Input Pin Pull-Up Function _______________________________________________ 13-3 
2.4. Output Pin Open-Drain Output Function____________________________________ 13-3 
2.5. Input/Output Signal Inverting Function_____________________________________ 13-3 
3. Clock Settings ___________________________________________________ 13-4 
3.1. UART3 Operating Clock _________________________________________________ 13-4 
3.2. Clock Supply in SLEEP Mode______________________________________________ 13-4 
3.3. Clock Supply During Debugging ___________________________________________ 13-4 
3.4. Baud Rate Generator ___________________________________________________ 13-4 
4. Data Format ____________________________________________________ 13-5 
5. Operations______________________________________________________ 13-6 
5.1. Initialization __________________________________________________________ 13-6 
5.2. Data Transmission______________________________________________________ 13-6 
5.3. Data Reception________________________________________________________ 13-8 
5.4. IrDA Interface_________________________________________________________ 13-9 
5.5. Carrier Modulation____________________________________________________ 13-10 
6. Receive Errors __________________________________________________ 13-11 
6.1. Framing Error ________________________________________________________ 13-11 
6.2. Parity Error __________________________________________________________ 13-11 
6.3. OverrunError ________________________________________________________ 13-11 
7. Interrupts _____________________________________________________ 13-12 
8. DMA Transfer Requests___________________________________________ 13-12 
9. Control Registers ________________________________________________ 13-13 
Synchronous Serial Interface (SPIA) ________________________________ 14-1 
1. Overview _______________________________________________________ 14-1 
2. Input/Output Pins and External Connections __________________________ 14-2 
2.1. List of Input/Output Pins ________________________________________________ 14-2 
2.2. ExternalConnections ___________________________________________________ 14-2 
2.3. Pin Functions in Master Mode and Slave Mode ______________________________ 14-3 
2.4. Input Pin Pull-Up/Pull-Down Function _____________________________________ 14-3 
3. Clock Settings ___________________________________________________ 14-4 
3.1. SPIA Operating Clock ___________________________________________________ 14-4 
3.2. Clock Supply During Debugging ___________________________________________ 14-5 
3.3. SPI Clock (SPICLKn) Phase and Polarity _____________________________________ 14-5 
4. Data Format ____________________________________________________ 14-5 
5. Operations______________________________________________________ 14-6 
5.1. Initialization __________________________________________________________ 14-6 
5.2. Data Transmission in Master Mode________________________________________ 14-6 
5.3. Data Reception in Master Mode__________________________________________ 14-9 
5.4. Terminating Data Transfer in Master Mode ________________________________ 14-11 
5.5. Data Transfer in Slave Mode ____________________________________________ 14-11 
5.6. Terminating Data Transfer in Slave Mode __________________________________ 14-12 
6. Interrupts _____________________________________________________ 14-13 
7. DMA Transfer Requests___________________________________________ 14-14 

Seiko Epson Corporation 
S1C31D50TECHNICAL MANUAL 
(Rev. 1.00) 
 
 
8. Control Registers ________________________________________________ 14-15 
Quad Synchronous Serial Interface (QSPI) ___________________________ 15-1 
1. Overview _______________________________________________________ 15-1 
2. Input/Output Pins and External Connections __________________________ 15-2 
2.1. List of Input/Output Pins ________________________________________________ 15-2 
2.2. ExternalConnections ___________________________________________________ 15-2 
2.3. Pin Functions in Master Mode and Slave Mode ______________________________ 15-6 
2.4. Input Pin Pull-Up/Pull-Down Function _____________________________________ 15-6 
3. Clock Settings ___________________________________________________ 15-7 
3.1. QSPI Operating Clock ___________________________________________________ 15-7 
3.2. Clock Supply During Debugging ___________________________________________ 15-7 
3.3. QSPI Clock (QSPICLKn) Phase and Polarity___________________________________ 15-8 
4. Data Format ____________________________________________________ 15-8 
5. 
Operations
 _____________________________________________________ 15-10 
5.1. Register Access Mode _________________________________________________ 15-10 
5.2. Memory Mapped Access Mode _________________________________________ 15-10 
5.3. 
Initialization
__________________________________________________________ 15-12 
5.4. Data Transmission in Master Mode_______________________________________ 15-13 
5.5. Data Reception in Register Access Master Mode ___________________________ 15-15 
5.6. Data Reception in Memory Mapped Access Mode __________________________ 15-18 
5.7. Terminating Memory Mapped Access Operations ___________________________ 15-27 
5.8. Terminating Data Transfer in Master Mode ________________________________ 15-27 
5.9. Data Transfer in Slave Mode ____________________________________________ 15-28 
5.10. Terminating Data Transfer in Slave Mode ________________________________ 15-29 
6. Interrupts _____________________________________________________ 15-30 
7. DMA Transfer Requests___________________________________________ 15-32 
8. Control Registers ________________________________________________ 15-33 
I2C (I2C) ______________________________________________________ 16-1 
1. Overview _______________________________________________________ 16-1 
2. Input/Output Pins and External Connections __________________________ 16-2 
2.1. List of Input/Output Pins ________________________________________________ 16-2 
2.2. ExternalConnections ___________________________________________________ 16-2 
3. Clock Settings ___________________________________________________ 16-3 
3.1. I2C Operating Clock ____________________________________________________ 16-3 
3.2. Clock Supply During Debugging ___________________________________________ 16-3 
3.3. Baud Rate Generator ___________________________________________________ 16-4 
4. Operations______________________________________________________ 16-5 
4.1. Initialization __________________________________________________________ 16-5 
4.2. Data Transmission in Master Mode________________________________________ 16-5 
4.3. Data Reception in Master Mode__________________________________________ 16-8 
4.4. 10-bit Addressing in Master Mode _______________________________________ 16-11 
4.5. Data Transmission in Slave Mode_________________________________________ 16-12 
4.6. Data Reception in Slave Mode __________________________________________ 16-14 
4.7. Slave Operations in 10-bit Address Mode __________________________________ 16-15 
4.8. Automatic Bus Clearing Operation________________________________________ 16-16 

Seiko Epson Corporation

S1C31D50TECHNICAL MANUAL

(Rev. 1.00)

16.4.9. Error Detection_______________________________________________________ 16-17

16.5. Interrupts _____________________________________________________ 16-18

16.6. DMA Transfer Requests___________________________________________ 16-20

16.7. Control Registers ________________________________________________ 16-21

17. 16-bit PWM Timers (T16B) _______________________________________ 17-1

17.1. Overview _______________________________________________________ 17-1

17.2. Input/Output Pins________________________________________________ 17-2

17.3. Clock Settings ___________________________________________________ 17-3

17.3.1. T16B Operating Clock___________________________________________________ 17-3

17.3.2. Clock Supply in SLEEP Mode______________________________________________ 17-3

17.3.3. Clock Supply During Debugging ___________________________________________ 17-3

17.3.4. Event Counter Clock ____________________________________________________ 17-3

17.4.

Operations

______________________________________________________ 17-4

17.4.1.

Initialization

___________________________________________________________ 17-4

17.4.2. Counter Block Operations _______________________________________________ 17-5

17.4.3. Comparator/Capture Block Operations ____________________________________ 17-8

17.4.4. TOUT Output Control __________________________________________________ 17-18

17.5. Interrupt ______________________________________________________ 17-24

17.6. DMA Transfer Requests___________________________________________ 17-24

17.7. Control Registers ________________________________________________ 17-25

18. IR Remote Controller (REMC3) ____________________________________ 18-1

18.1. Overview _______________________________________________________ 18-1

18.2. Output Pins and External Connections ________________________________ 18-2

18.2.1. List of Output Pins _____________________________________________________ 18-2

18.2.2. ExternalConnections ___________________________________________________ 18-2

18.3. Clock Settings ___________________________________________________ 18-2

18.3.1. REMC3 Operating Clock_________________________________________________ 18-2

18.3.2. Clock Supply in SLEEP Mode______________________________________________ 18-2

18.3.3. Clock Supply During Debugging ___________________________________________ 18-3

18.4.

Operations

______________________________________________________ 18-3

18.4.1.

Initialization

___________________________________________________________ 18-3

18.4.2. Data Transmission Procedures ____________________________________________ 18-3

18.4.3. REMO Output Waveform________________________________________________ 18-4

18.4.4. Continuous Data Transmission and Compare Buffers __________________________ 18-6

18.5. Interrupts ______________________________________________________ 18-7

18.6. ApplicationExample:DrivingELLamp_________________________________ 18-7

18.7. Control Registers _________________________________________________ 18-8

19. 12-bitA/D Converter (ADC12A)____________________________________ 19-1

19.1. Overview _______________________________________________________ 19-1

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