Epson S1R72V17 Manual de instrucciones
Rev. 1.0
S1R72V17
CPU Connection Guide
NOTICE
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©SEIKO EPSON CORPORATION 2008, All rights reserved.
Scope
This document applies to the S1R72V17 USB2.0 host/device controller LSI.
S1R72V17 CPU Connection Guide EPSON i
(Rev. 1.0)
Table of Contents
1. Introduction....................................................................................................................................... 1
1.1 Overview..................................................................................................................................... 1
1.2 Related Documents .................................................................................................................... 1
2. Connection Example with Standard CPU ....................................................................................... 2
3. Endian Settings for 16-bit Bus Width Connection ......................................................................... 4
3.1 Connection to Big-endian CPU................................................................................................... 4
3.2 Connection to Little-endian CPU ................................................................................................ 7
4. CPUIF Verification Procedure ........................................................................................................ 10
5. Connection Example with FreeScale iMX21 ................................................................................. 14
5.1 Connection Example ................................................................................................................ 14
5.2 iMX21 Bus Cycle Setting Example ........................................................................................... 16
5.3 Checking S1R72V17 AC Spec and iMX21 Bus Cycle .............................................................. 18
1. Introduction
S1R72V17 CPU Connection Guide EPSON 1
(Rev. 1.0)
1. Introduction
1.1 Overview
This document contains information required for actual use of the S1R72V17 by the customer,
focusing on the details necessary to connect the S1R72V17 to the control CPU.
This document describes typical connection methods. No guarantees are made regarding the
suitability of these methods. The connection methods must be modified to suit specific customer
system configurations.
The contents of this document are subject to change without notice.
1.2 Related Documents
•S1R72V17 Technical Manual (Hardware Specifications)
2. Connection Example with Standard CPU
2 EPSON S1R72V17 CPU Connection Guide
(Rev. 1.0)
2. Connection Example with Standard CPU
This section illustrates a typical connection with a standard CPU.
1) 16-bit bus, Strobe mode connection example
Set CPU_Config register (0x075h address) BusMode bit to “0” and Bus8x16 bit to “0.”
16bit Strobe mode
CPU S1R72V17
IOVDD CVDD
Address[8:1] CA[8:1]
XBEL(CA[0])
DATA[15:0] CD[15:0]
XCS XCS
XRD XRD
XWRH XWRH(XBEH)
XWRL XWRL(XWR)
XDREQ
X
DREQ *1
XDACK
X
DACK *2
XINT
X
INT
<When DMA is not used>
*1: Open
*2: Fixed at High or Low
1.65 V to 3.6 V
Fig. 2-1 16-bit bus, Strobe mode connection example
2. Connection Example with Standard CPU
S1R72V17 CPU Connection Guide EPSON 3
(Rev. 1.0)
2) 16-bit bus, BE mode connection example
Set CPU_Config register (0x075h address) BusMode bit to “1” and Bus8x16 bit to “0.”
16bit BE mode
CPU S1R72V17
IOVDD CVDD
Address[8:1] CA[8:1]
XBEL XBEL(CA[0])
DATA[15:0] CD[15:0]
XCS XCS
XRD XRD
XBEH XWRH(XBEH)
XWR XWRL(XWR)
XDREQ
X
DREQ *1
XDACK
X
DACK *2
XINT
X
INT
<When DMA is not used>
*1: Open
*2: Fixed at High or Low
1.65 V to 3.6 V
Fig. 2-2 16-bit bus, BE mode connection example
3) 8-bit bus mode connection example
Set CPU_Config register (0x075h address) BusMode bit to “0” and Bus8x16 bit to “1.”
8bit mode
CPU S1R72V17
IOVDD CVDD
Address[8:1] CA[8:1]
Address[0] XBEL(CA[0])
CD[15:8]
DATA[7:0] CD[7:0]
XCS XCS
XRD XRD
XWRH(XBEH)
XWR XWRL(XWR)
XDREQ
X
DREQ *1
XDACK
X
DACK *2
XINT
X
INT
<When DMA is not used>
*1: Open
*2: Fixed at High or Low
1.65 V to 3.6 V
Fig. 2-3 8-bit bus mode connection example
3. Endian Settings for 16-bit Bus Width Connection
4 EPSON S1R72V17 CPU Connection Guide
(Rev. 1.0)
3. Endian Settings for 16-bit Bus Width Connection
This section describes endian settings when connecting to a CPU with a 16-bit bus width.
The discussion of the S1R72V17 registers divides them into the following three types. For register details,
refer to the S1R72V17 Technical Manual.
1) Word register: Registers with _H/_L/_HH/_HL/_LH/_LL at the end of the register name
2) Byte register: Registers not corresponding to Word or FIFO registers
3) FIFO register: RAM_Rd_00 to _1F/RAM_WrDoor_0,1/FIFO_Rd_0,1/FIFO_Wr_0,1/
FIFO_ByteRd registers
3.1 Connection to Big-endian CPU
Access is normally in the mode with “0” set in the CPU_Config register (0x075h address)
CPU_Endian bit.
1) Access to Word register
The S1R72V17 connects the D[15:8] bus to the first byte of the Word register and the D[7:0]
bus to the last byte of the Word register.
The example below illustrates the writing and reading of 0x1234h data to/from the Word register.
Writing: The data (12h) in the CPU memory even-number address is saved to the first byte
of the S1R72V17 Word register.
Reading: The first byte data (12h) of the S1R72V17 Word register is saved to the
even-number address in CPU memory.
CPU
Data
・・・・
・・・・
12h
Even-number address
34h
Odd-number address
Data in CPU memory
・・・・
・・・・
Higher byte [15:8] Lower byte [7:0]
12h 34h CPU register
D[15:8] D[7:0] CPU data bus
D[15:0] bus connected unchanged
S1R72V17 D[15:8] D[7:0] V17 data bus
12h 34h V17 Word register
Higher byte [15:8] Lower byte [7:0]
_H, _HH, _LH registers _L, _HL, _LL registers
Fig. 3-1 Access to Word registers (big-endian CPU)
3. Endian Settings for 16-bit Bus Width Connection
S1R72V17 CPU Connection Guide EPSON 5
(Rev. 1.0)
2) Access to Byte register
The S1R72V17 connects the D[15:8] bus to the even-number address register and the D[7:0] bus
to the odd-number address register when the CPU_Endian bit is set to “0.”
The example below illustrates the writing and reading of F1h to/from the Byte register
even-number address register and of F2h to/from the Byte register odd-number address register.
Writing: The data (F1h) in the CPU memory even-number address is saved to the
S1R72V17 even-number address register.
Reading: The S1R72V17 even-number address register data (F1h) is saved to the
even-number address in CPU memory.
CPU
Data
・・・・
・・・・
F1h
Even-number address
F2h
Odd-number address
Data in CPU memory
・・・・
・・・・
Higher byte [15:8] Lower byte [7:0]
F1h F2h CPU register
D[15:8] D[7:0] CPU data bus
D[15:0] bus connected unchanged
S1R72V17 D[15:8] D[7:0] V17 data bus
F2h F1h V17 Byte register
Odd-number address Even-number address
re
g
ister register
Fig. 3-2 Access to Byte registers (big-endian CPU)
3. Endian Settings for 16-bit Bus Width Connection
6 EPSON S1R72V17 CPU Connection Guide
(Rev. 1.0)
3) Access to FIFO register
The S1R72V17 connects the D[15:8] bus to the even-number address register and the D[7:0] bus
to the odd-number address register when the CPU_Endian bit is set to “0.”
The example below illustrates transmission from the USB bus in the sequence C1h/C2h and
receiving in the sequence C1h/C2h.
Writing: The data (C1h) in the CPU memory even-number address is sent from the USB
bus as the first data.
Reading: The first data received from the USB bus (C1h) is saved to the even-number
address in CPU memory.
CPU
Data
・・・・
・・・・
C1h
Even-number address
C2h
Odd-number address
Data in CPU memory
・・・・
・・・・
Higher byte [15:8] Lower byte [7:0]
C1h C2h CPU register
D[15:8] D[7:0] CPU data bus
D[15:0] bus connected unchanged
S1R72V17 D[15:8] D[7:0] V17 data bus
C2h C1h V17 Byte register
Odd-number address Even-number address
re
g
ister register
Data[15:8] Data[7:0]
・・・・ ・・・・ V17 FIFO data
・・・・ ・・・・
(2) C2h (1) C1h Sent via USB bus in order (1), (2).
(4) ・・・・ (3) ・・・・
・・・・ ・・・・
・・・・ ・・・・
Fig. 3-3 Access to FIFO registers (big-endian CPU)
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