Dynamic Engineering PMC-BiSerial-III HW2 Manual de usuario

DYNAMIC ENGINEERING

150 DuBois, Suite 3 Santa Cruz, CA 95060

(831) 457-8891 Fax (831) 457-4793

www.dyneng.com

[email protected]

Est. 1988

User Manual

PMC-BiSerial-III HW2

32 channel

Bi-directional Manchester, SDLC and

Asynchronous Interface

PMC Module

Revision A

Corresponding Hardware: Revision C

10-2005-0503

Corresponding Firmware: Revision B

Embedded Solutions Page 2 of 50

PMC-BiSerial-III HW2

Bi-Directional Serial Data Interface

PMC Module

Dynamic Engineering

150 DuBois, Suite 3

Santa Cruz, CA 95060

(831) 457-8891

FAX: (831) 457-4793

This document contains information of

proprietary interest to Dynamic Engineering. It

has been supplied in confidence and the

recipient, by accepting this material, agrees that

the subject matter will not be copied or

reproduced, in whole or in part, nor its contents

revealed in any manner or to any person except

to meet the purpose for which it was delivered.

Dynamic Engineering has made every effort to

ensure that this manual is accurate and

complete. Still, the compan

reserves the ri

ht to

make improvements or changes in the product

described in this document at any time and

without notice. Furthermore, D

namic

Engineering assumes no liability arising out of

the application or use of the device described

herein.

The electronic equipment described herein

enerates, uses, and can radiate radio frequenc

energy. Operation of this equipment in a

residential area is likely to cause radio

interference, in which case the user, at his own

expense, will be required to take whatever

measures may be required to correct the

interference.

Dynamic Engineering’s products are not

authorized for use as critical components in life

support devices or systems without the express

written approval of the president of Dynamic

Engineering.

This product has been designed to operate with

PMC Module carriers and compatible user-

provided equipment. Connection of incompatible

hardware is likely to cause serious damage.

Other trademarks and registered trademarks are

owned by their respective manufactures.

Revised September 25, 2007.

Embedded Solutions Page 3 of 50

Table of Contents

PRODUCT DESCRIPTION 6

THEORY OF OPERATION 11

ADDRESS MAP 14

PROGRAMMING 16

BIS3_BASE 17

BIS3_ID 18

BIS3_START_SET 18

BIS3_START_RDBK 18

BIS3_START_CLR 19

BIS3_IO_DATA 20

BIS3_IO_DIR 20

BIS3_IO_TERM 21

BIS3_IO_MUX 21

BIS3_IO_UCNTL 22

BIS3_IO_RDBK 22

BIS3_IO_RDBKUPR 23

BIS3_STAT_FIFO 23

BIS3_PLL_CMD, PLL_RDBK 24

BIS3_SM_CNTL7-0 25

BIS3_SDLC_CNTL5-0 28

BIS3_ASYNC_CNTL11-0 30

BIS3_CHAN_MODE 32

BIS3_INT_STAT 33

BIS3_I2OAR 33

BIS3_SM_MEM31-0 34

Mode Resource Mapping 39

Interrupts 40

Loop-back 41

PMC PCI PN1 INTERFACE PIN ASSIGNMENT 42

PMC PCI PN2 INTERFACE PIN ASSIGNMENT 43

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BISERIAL III FRONT PANEL I/O PIN ASSIGNMENT 44

APPLICATIONS GUIDE 45

Interfacing 45

CONSTRUCTION AND RELIABILITY 46

THERMAL CONSIDERATIONS 46

WARRANTY AND REPAIR 47

SERVICE POLICY 47

OUT OF WARRANTY REPAIRS 47

FOR SERVICE CONTACT: 47

SPECIFICATIONS 48

ORDER INFORMATION 50

SCHEMATICS 50

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List of Figures

FIGURE 1 PMC BISERIAL-III BASE BLOCK DIAGRAM 6

FIGURE 2 PMC BISERIAL-III-HW2 P2P BLOCK DIAGRAM 7

FIGURE 3 PMC BISERIAL-III-HW2 SDLC BLOCK DIAGRAM 8

FIGURE 4 PMC BISERIAL-III-HW2 ASYNC BLOCK DIAGRAM 9

FIGURE 5 PMC BISERIAL III HW2 MANCHESTER TIMING DIAGRAM 12

FIGURE 6 PMC BISERIAL-II I-HW2 INTERNAL ADDRESS MAP 15

FIGURE 7 PMC BISERIAL-III BASE CONTROL REGISTER BIT MAP 17

FIGURE 8 PMC BISERIAL-III DESIGN ID REGISTER BIT MAP 18

FIGURE 9 PMC BISERIAL-III START SET REGISTER 18

FIGURE 10 PMC BISERIAL-III START CLEAR REGISTER 19

FIGURE 11 PMC BISERIAL-III PARALLEL OUTPUT DATA BIT MAP 20

FIGURE 12 PMC BISERIAL-III DIRECTION CONTROL PORT 20

FIGURE 13 PMC BISERIAL-III TERMINATION CONTROL PORT 21

FIGURE 14 PMC BISERIAL-III MUX CONTROL PORT 21

FIGURE 15 PMC BISERIAL-III UPPER CONTROL PORT 22

FIGURE 16 PMC BISERIAL-III I/O READBACK PORT 22

FIGURE 17 PMC BISERIAL-III I/O READBACK PORT 23

FIGURE 18 PMC BISERIAL-III SWITCH PORT 23

FIGURE 19 PMC BISERIAL-III PLL CONTROL 24

FIGURE 20 PMC BISERIAL-III STATE MACHINE CONTROL REGISTERS 25

FIGURE 21 PMC BISERIAL-III SDLC CONTROL REGISTERS 28

FIGURE 22 PMC BISERIAL-III SDLC CONTROL REGISTERS 30

FIGURE 23 PMC BISERIAL-III CHANNEL MODE CONTROL REGISTER 32

FIGURE 24 PMC BISERIAL-III INTERRUPT STATUS REGISTER 33

FIGURE 25 PMC BISERIAL-III I2O ADDRESS REGISTER 33

FIGURE 26 PMC BISERIAL-III PN1 INTERFACE 42

FIGURE 27 PMC BISERIAL-III PN2 INTERFACE 43

FIGURE 28 PMC BISERIAL-III FRONT PANEL INTERFACE 44

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Product Description

The PMC BiSerial-III-HW2 is part of the PMC Module family of modular I/O components

by Dynamic Engineering. The PMC BiSerial-III is capable of providing multiple serial

protocols. The HW2 protocol implemented provides 8 Manchester encoded inputs and

outputs and 6 additional blocks that can each be configured as either one full-duplex

SDLC I/O or two full-duplex asynchronous (UART) I/O.

Other custom interfaces are available. We will redesign the state machines and create

a custom interface protocol. That protocol will then be offered as a “standard” special

order product. Please see our web page for current protocols offered. Please contact

Dynamic Engineering with your custom application.

485/LVDS buffers

termination

PCI IF

FIFO B

128K x 32

FIFO A

128K x 32

State

Machine

State

Machine

Data Flow

Control

PLL

FIGURE 1 PMC BISERIAL-III BASE BLOCK DIAGRAM

Embedded Solutions Page 7 of 50

The standard configuration shown in Figure 1 makes use of two external (to the Xilinx)

FIFOs. The FIFOs can be as large as 128K deep x 32 bits wide. Some designs do not

require so much memory, and are more efficiently implemented using the Xilinx internal

memory.

FIGURE 2 PMC BISERIAL-III-HW2 P2P BLOCK DIAGRAM

The HW2 implementation has 32 – Dual Port RAM (DPR) blocks implemented using

the Xilinx internal block RAM. Each channel has one or more associated DPRs

depending on which mode is active. Each DPR is configured to have a 32-bit port on

the PCI side, and a 16-bit port on the I/O side.

The lower eight channels are configured with the point-to-point interface that was used

on the HW1. In this mode when operating in the bidirectional mode the DPR is split in

half to provide both transmit, and receive buffers. In the unidirectional mode the full

DPR can be used for transmit or receive data.

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The data rates are programmable to either 400 KHz or 5 MHz. Usually the 5 MHz rate

is used in the unidirectional mode and the 400 KHz in the bidirectional mode. The data

is Manchester encoded. The hardware uses a higher rate clock to separate the clock

and data embedded within the Manchester data stream.

The remaining 24 channels are divided into six four-channel blocks that can each be

configured as either one full-duplex SDLC interface or two full-duplex asynchronous

interfaces.

The SDLC interface uses programmable PLL clock A as its reference frequency with

clock and data in and out comprising the four I/O lines of the channel block. The four

DPRs are partitioned into two blocks each for transmit and receive circular buffers that

have independently specified start and stop addresses and separate transmit and

receive interrupts.

FIGURE 3 PMC BISERIAL-III-HW2 SDLC BLOCK DIAGRAM

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Each asynchronous interface uses either programmable PLL clock B or a fixed 5 MHz

as its 16x reference frequency with data in and out using two of the four I/O lines of the

channel block. Two DPRs are used for each asynchronous interface, one each for

transmit and receive circular buffers that have independently specified start and stop

addresses.

FIGURE 4 PMC BISERIAL-III-HW2 ASYNC BLOCK DIAGRAM

The two asynchronous interfaces in a channel block are independently configurable

and each have separate receive and transmit interrupts.

All the data I/O lines on the HW2 are programmable to be register controlled or state-

machine controlled. Any or all of the bits can be used as a parallel port instead of being

dedicated to a specific I/O protocol. Thirty-four differential I/O are provided at the front

bezel (32 of the 34 at Pn4) for the serial signals. The drivers and receivers conform to

the RS-485 specification (exceeds RS-422 specification). The RS-485 input signals are

selectively terminated with 100Ω. The termination resistors are in two-element

Embedded Solutions Page 10 of 50

packages to allow flexible termination options for custom formats and protocols.

Optional pullup/pulldown resistor packs can also be installed to provide a logic ‘1’ on

undriven lines. The terminations and transceivers are programmable through the Xilinx

device to provide the proper mix of outputs and inputs and terminations needed for a

specific protocol implementation. The terminations are programmable for all I/O.

All configuration registers support read and write operations for maximum software

convenience, and all addresses are long word aligned.

The PMC BiSerial-III conforms to the PMC and CMC draft standards. This guarantees

compatibility with multiple PMC Carrier boards. Because the PMC may be mounted on

different form factors, while maintaining plug and software compatibility, system

prototyping may be done on one PMC Carrier board, with final system implementation

uses a different one.

The PMC BiSerial-III uses a 10 mm inter-board spacing for the front panel, standoffs,

and PMC connectors. The 10 mm height is the "standard" height and will work in most

systems with most carriers. If your carrier has non-standard connectors (height) to

mate with the PMC BiSerial-III, please let us know. We may be able to do a special

build with a different height connector to compensate.

Interrupts are supported by the PMC BiSerial-III-HW2. An interrupt can be configured to

occur at the end of a transmitted packet or message. An interrupt will be set at the end

of a received packet or message. All interrupts are individually maskable, and a master

interrupt enable is also provided to disable all interrupts simultaneously. The current

status is available for the state-machines making it possible to operate in a polled

mode. I2O interrupt processing is also available.

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