Digital Equipment MS11-BC Manual de usuario

PDP-11/45

MS11

semiconductor

memory

systems

maintenance

manual

13-0

(

ro r

5:.

f.f(JJc/(b

PDp

11/45

MS11 semiconductor

memory systems

maintenance

manual

DEC-II-HMSB-D

digital equipment corporation · maynard. massachusetts

1st Edition April 1972

2nd Printing (Rev) August 1972

3rd Printing

January

1973

The material in

this

manual is

for

information-

purposes and is subject

change

without

notice.

The

following are trademarks

Digital

Equipment

Corporation, Maynard, Massachusetts:

DEC

FLIP CHIP

DIGITAL

PDP

FOCAL

COMPUTER LAB

CONTENTS

CHAPTER 1 SYSTEM DESCRIPTION

1.1

Introduction

. . . . . .

.......

1.2 M8111 Bipolar Memory Matrix Module

1.3 G401

MaS

Memory Matrix Module

1.4

M8ll0

Semiconductor Memory Control Module

1.4.1 Memory Address Multiplexing

1.4.2 Write and Read Data Registers

1.4.3 Timing and Control

1.4.4 Refresh Logic

1.4.5 Parity Control

1.4.6 Diagnostic Logic

1.5 System Specifications

1.6 Semiconductor Memory System Configurations

CHAPTER 2 MEMORY SYSTEM INTERFACE OPERATIONS

2.1

2.2

2.2.1

2.2.2

2.2.3

2~2.4

2.3

2.3.1

2.3.2

2.4

2.4.1

2.4.2

2.5

2.6

2.6.1

2.6.2

2.6.3

2.6.4

Introduction

Basic Memory Access Operations

Data

(DATI) Cycle . . . .

Data In, Pause (DATIP) Cycle

Data

Out

(DATa)

Operation

Data

Out, Byte (DATOB) Cycle

Fastbus Interface

Fastbus

DATa

Cycle

Fastbus DATI Cycle

Unibus Interface

Unibus

DATa

Cycle

Unibus DATI Cycle

Memory Bus

Semiconductor Memory Addressing

Address Decoding

the

M8ll

0 Control

Address Mapping

the

M8ll

0 Control

MaS

Memory Matrix Module Address Decoding

Bipolar Memory Matrix Module Address Decoding

CHAPTER 3 LOGIC DESCRIPTION

3.1

3.2

3.2.1

3.2.2

3.3

3.3.1

3.3.1.1

Introduction

.............

G40l

MaS

Memory Matrix Module Logic

MaS

Memory Writing . . . . . . . . . .

MOS

:Memorj Reading

M8lll

Bipolar Memory Matrix Module Logic

Memory Matrix Control

Address Buffer

iii

Page

1-1

1-2

1-3

1-4

1-5

1-6

2-1

2-2

2-4

2-5

2-7

2-8

2-10

2-11

2-12

3-1

3-2

3-4

3.3.1.2

3.3.1.3

3.3.2

3.4

3.4.1

3.4.2

3.4.3

3.4.3.1

3.4.3.2

3.4.3.3

3.4.4

3.4.5

3.4.6

3.4.7

3.4.7.1

3.4.7.2

3.4.7.3

3.4.8

3.4.8.1

3.4.8.2

3.4.8.3

CONTENTS (Cont)

Data Inversion

and

Write Pulse

Fanout

Logic

Address Examination Logic . . . . . . . . .

Bipolar Matrix

..............

M8110

Semiconductor

Memory Control Module

Memory Selection Logic

Unibus Interface (SMeH)

Address Multiplexing (SMCC)

Unibus Address Multiplexing

Fastbus Address Multiplexing

Refresh Address Multiplexing

Data Multiplexing (SMCD)

Data

Output

(SMCE)

M8ll0

Control

Logic

Diagnostic Logic

Diagnostic Address Decoding

Diagnostic Parity Registers

Diagnostic Parity Register

Functions

Refresh Logic . . . . . . . . . . . .

Normal Refresh Cycle

......

Refresh Cycle

Intervention

During Single-Step Mode

Refresh Cycle During Power-Down Periods

CHAPTER 4 CALIBRATION AND MAINTENANCE

4.1

4.2

4.2.1

4.2.2

4.2.3

4.3

4.3.1

4.3.1.1

4.3.2

4.3.2.1

4.4

4.5

4.5.1

Introduction

Semiconductor Memory System Precalibration Procedures

Memory Cycling Program

Test

Equipment

Required

Calibration

Setup

....

Memory System Calibration

MOS

Memory System Calibration

Address

Set

Up, Precharge, CENABLE, and Access

Ready

Timing

Adjustments

Bipolar Memory System Calibration

Address

Set

Up, Precharge, and Access Ready Timing

Adjustments

Semiconductor Memory System Diagnostics

Memory Matrix Module Structure

.....

Isolation

Malfunctions

Module

Component

APPENDIX A APPLICATION

MOSFETS IN IC RANDOM ACCESS MEMORIES

A.1

A.2

A.3

Introduction

The MOSFET

The MOSFET as a Memory

Page

3-6

3-7

3-8

3-11

3-14

3-16

3-17

3-18

3-19

3-44

3-45

3-47

3-49

3-50

4-1

4-2

4-3

4-4

4-5

A-I

A-2

f"",

CONTENTS (Cont)

Page

APPENDIX B INTEGRATED CIRCUIT DESCRIPTIONS

Figure No.

1-1

1-2

2-1

2-2

2-3

2-4

2-5

2-6

2-7

2-8

2-9

3-1

3-2

3-3

3-4

3-5

3-6

3-7

3-8

3-9

3-10

3-11

3-12

3-13

3-14

3-15

3-16

3-17

4-1

1103 Random Access 1024-Bit Memory

.....

3207 Quad 3-Input NAND

TTL/MaS

Lever Shifter

3404 High Speed Hex Latch

74200 Bipolar 256-Bit Random Access Memory

75107/7

08 Dual-Line Receivers

.....

8242 Exclusive-NOR 4-Bit Digital Comparator .

ILLUSTRATIONS

Title

Semiconductor Memory System, Block Diagram

Semiconductor Memory Control Module, Block Diagram

Semiconductor Memory Configuration within PDP-l 1/45 Systems

Semiconductor Memory System Interfaces

Fastbus Interface

...................

Unibus Interface

B-3

B-5

B-7

B-9

B-ll

B-13

Page

1-1

1-3

2-2

2-3

2-6

2-9

Semiconductor Memory Bus, Simplified Block Diagram 2-10

Semiconductor Memory Address Examination

2-11

Semiconductor Memory Address Mapping 2-12

MaS

Memory Matrix Address Examination 2-13

Bipolar Memory Matrix Addressing . 2-14

MaS

Memory Matrix, Block Diagram . . . 3-3

Bipolar Memory Matrix

. . . . . . . . 3-5

M8110 Semiconductor Memory Control Module, Block Diagram 3-9

Simplified Memory Address Decode (SMCF)

........

3-13

Fastbus Address Multiplexing

<14:

11>

Required E67 Jumpers 3-15

MAD

Multiplexing, Required E86 Jumpers . . . . . . . . . 3-15

Unibus Address Multiplexing

04:

11>

Required E78 Jumpers 3-15

Unibus

DATa

Logic Flow 3-20

Fastbus

DATa

Logic Flow 3-27

Unibus DATI Logic Flow . 3-34

Fastbus DATI Logic Flow 3-37

Unibus

DATa

Timing

(MOS

Memory) 3-39

Fastbus

DATa

Timing

(MaS

Memory) 3-40

Unibus DATI Timing (MOS Memory) 3-41

Fastbus DATI Timing

(MaS

Memory) 3-42

Diagnostic Logic Parity Checking and Control 3-43

Nonnal

MOS

Refresh Cycle

Ti.111ing

. . . . . . 3-48

M8110 Timing and Termination Delay Adjustment for

MaS

Memory

(Logic Drawing SMCA)

........................

4-4

4-2

4-3

4-4

A-I

A-2

A-3

Table No.

1-1

1-2

2-1

2-2

2-3

3-1

3-2

3-3

3-4

3-5

3-6

3-7

3-8

3-9

3-10

3-11

3-12

4-1

ILLUSTRATIONS

(Cont)

M8110 Timing and Termination Delay

Adjustment

for Bipolar

Memory (Logic Drawing SMCA)

..............

G401YA

MOS Memory Matrix

Module-Relationship

ofICs

Bits

M8111 Bipolar Memory Matrix

Module-Relationship

ICs

Bits

Physical

Structure

a MOSFET .

Drain Characteristics

a MOSFET

Basic

Dynamic

MOS Storage Cell .

TABLES

Title

MOS

Memory

System Configuration

Bipolar Memory System Configuration

Fastbus/M8110

Interface and

Control

Signals

Fastbus

and

Unibus Control Bit

States

Unibus/M8110 Interface

Information

and

Control

Signals

MOS

Matrix Selected Address Configuration

16K)

MOS

Matrix

Control

Level

Generation

and

Selected Memory Address

Block

4K)

...............

Expanded

M811l

Memory Address

Allocation

.....

Address

Bit

MAD BitTranslation

Bipolar Matrix Selected Address Configuration

16K)

Address Decoding for Memory Circuit Enabling

Fastbus/Unibus

Memory Address (Assign and Decode)

MOS/Bipo1ar Module Addressing

.....

MOS/Bipolar Memory Addressing

....

MUltiplexed Address

Inputs

MAD (SMCC)

Diagnostic

Parity

Control

States

Parity Diagnostic Register

Bit

Identity

and

Function

Semiconductor

Memory

Adjustments

Page

4-5

4-7

4-9

A-I

A-2

A-3

Page

1-6

2-4

2-5

2-7

3-2

3-5

3-6

3-7

3-8

3-12

3-13

3-17

3-45

. 3-45

4-2

/.J

(

INTRODUCTION

This manual describes the

MSll

options that constitute the

PDP-ll/45

Semiconductor Memory System. Its pri-

mary purpose

provide information for

DEC

Field Service representatives and customer personnel, with

simi-

lar PDP-l1/45 training, to perform on-site maintenance

the

MSll

options. The information

presented in

four chapters.

Chapter 1 describes the

Semiconductor Memory System structure.

also provides module specifications

and system configuration information.

Chapter 2 describes semiconductor memory system access operations, interfacing, and addressing.

Chapter 3 provides a detailed analysis

semiconductor memory logic operation.

Chapter 4 presents the procedures required for semiconductor memory calibration and maintenance.

All descriptions assume

that

the reader

familiar with basic digital computer theory and the operating character-

istics

bipolar and metal-oxide semiconductor (MaS) digital integrated circuits. Because

the many recent

ad-

vances in

MaS

technology concerning memory system applications, Appendix A contains a description

MaS

memory circuit theory.

Data, address, and control signals relevant to semiconductor memory operation are transmitted on the Unibus or

the

PDP-ll/45

Fastbus. This manual references the data, address, and control lines

that

interface the semicon-

ductor memory system with otherPDP-l1/45 units, according to the conventions established for Unibus and

PDP-l 1/45 signal mnemonics.

For

example, SAPJ PA (17:06) H refers to the

physical-address (PA) inputs,

named PA17 through PA06, which are generated

shown on drawing SAPJ. The prefix SAPJ indicates sheet J

the

SAP

module schematic. Complete details on data, address, and control signal origin and derivation

are

pro-

vided in the following related manuals:

PDP-l 1/45 System Maintenance Manual

Central Processor Maintenance Manual

Memory Management Unit Maintenance Manual

PDP-II Unibus Interface Manual (Second Edition)

vii

DEC-II-H45B-D

DEC-II-HKBB-D

DEC-II-HKTB-D

DEC-II-HIAB-D

;...

(

CHAPTER

SYSTEM

DESCRIPTION

1.1

INTRODUCTION

Digital Equipment Corporation's MSl1 Semiconductor Memory Systems for the PDP-I 1/45 System are high-

speed random-access memories available in two basic solid-state types: bipolar (TTL) and metal-oxide semi-

conductor (MOS). The distinction between bipolar and

MOS

memory systems

made

the specific

MSI

com-

ponents used to form the memory storage matrices. Both forms

semiconductor memory matrices operate

under the control

the

M8lI

0 Semiconductor Memory Control module. The

M811

0 can control either four

1024-word M8111 Bipolar Memory Matrix modules or four 4096-word

G40l

MOS

Memory Matrix modules

(Figure 1-1). One bipolar memory system provides storage for 4096 16-bit words, and one

MOS

memory

sys-

tem provides storage for 16,384 16-bit words. Both forms

semiconductor memory are available with

with-

out

byte parity.

SEM ICONDUCTOR

MEMORY

CONTROL

Me110

CPU

FAST BUS

DIRECT

ACCESS

DEVICES

UNIBUS

11-1316

Figure

1-1

Semiconductor Memory System, Block Diagram

1-1

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