Digilent Eclypse Z7 Guía rápida de usuario

Eclypse Z7 Hardware Reference Manual

The Eclypse Z7 is a powerful prototyping platform, featuring Xilinx's Zynq-7000 APSoC.

Two SYZYGY interface connectors are featured, enabling high speed modular systems.

Eclypse is designed to enable high speed analog data capture and analysis right out of

the box. It is a platform for research and rapid prototyping of test and measurement

applications, potentially including software defined radio, ultrasound, other medical

devices, and much more. As a host board for Zmods, applications for the Eclypse can

vary significantly between system configurations.

Petalinux is supported out of the box. Pre-built Linux images are accompanied by a

software API for bulk data transfer. This system allows new users to get started without

touching hardware until desired. The software supports a variety of common

programming languages, including Python, C/C++, and more. Digilent offers fully open

and customizable hardware designs, Linux images, and Linux software applications.

Features

•Zynq-7000 APSoC (XC7Z020-1CLG484C)

o667 MHz dual-core Cortex-A9 processor

oDDR3L memory controller with 8 DMA channels and 4 High Performance AXI3

Slave ports

oHigh-bandwidth peripheral controllers: 1G Ethernet, USB 2.0, SDIO

oLow-bandwidth peripheral controllers: SPI, UART, CAN, I2C

oProgrammable from JTAG, Quad-SPI flash, and microSD card

oProgrammable logic equivalent to Artix-7 FPGA

•Memory

o1 GiB DDR3L with 32-bit bus @ 1066 MT/s

o16 MB Quad-SPI Flash with factory programmed 128-bit random number and 48-

bit globally unique EUI-48/64™ compatible identifier

omicroSD card slot

•Power

oPowered from external 12V 5A supply

oPlatform MCU for configuration of adjustable power supplies and temperature

management

•USB and Ethernet

oGigabit Ethernet PHY

oUSB-JTAG programming circuitry

oUSB-UART bridge

oUSB micro AB port with USB 2.0 PHY with Host/Device/OTG capabilities

•Zmod Ports

o2 ports following the SYZYGY Standard interface specification

oCompatible with a variety of SYZYGY pods, allowing for a wide variety of

applications

oDedicated differential clocks for input and output

o8 differential I/Os per port

o16 single-ended I/Os per port

oDNA interfaces connected to Platform MCU allowing for various auto-negotiated

power supply configurations

•Pmod Ports

o2 twelve-pin ports for a total of 16 FPGA-connected I/Os

oHigh speed voltage translation and protection circuitry

•User GPIO

o2 push-buttons

o2 RGB LEDs

Eclypse Z7 Callout Diagram

Callout

Description

Callout

Description

Callout

Description

Board Indicator

LEDs (LD4)

SYZYGY Ports

Reset Buttons

(underside of board)

Header for Case

Power Switch

Pmod Ports

microSD Card Slot

Power Switch

User Buttons and

LEDs

USB JTAG/UART Port

FPGA Fan Header

DDR3L Memory

Ethernet Port

Zynq-7000 SoC

and FPGA Fan

Case Fan Header

USB AB

Host/Device/OTG Port

External JTAG Port

Programming Mode

Select Jumper

Power Supply

Connector

Purchasing Options

The Eclypse Z7 includes an FPGA fan to dissipate extra heat generated from running

complex fast-switching designs. A USB A to Micro B programming cable, a USB A to

Micro A cable, and a 12V 5A power supply, are included with the Eclypse Z7.

An Eclypse Z7 Enclosure Kit may optionally be added on, which provides a sturdy case

for the Eclypse platform. The Enclosure Kit includes a case fan for additional cooling,

and exposes the connectors of loaded Zmod ADCs and DACs, as well as the Eclypse

Z7's Pmod expansion connectors, power switch, status LEDs, and more.

For more information on purchasing an Eclypse Z7, see the Eclypse Z7 Product Page.

Digilent Zmods may also be purchased individually or bundled with the Eclypse Z7.

Expansion connectors such as these, or other SYZYGY modules, are required to fully

leverage the high-speed I/O capabilities of the Eclypse platform.

Software Support

Zynq platforms are well-suited to be embedded Linux targets, and the Eclypse Z7 is no

exception. Digilent provides software examples targeting custom Petalinux projects,

including support for each Digilent Zmod for high-speed I/O capabilities.

The Eclypse Z7 is fully compatible with Xilinx’s high-performance Vivado ® Design

Suite. This tool set melds FPGA logic design and embedded ARM software

development into an easy to use, intuitive design flow. It can be used for designing

systems of any complexity, from a complete operating system running multiple server

applications, down to a simple bare-metal program that controls some LEDs. It is also

possible to treat the Zynq AP SoC as a standalone FPGA for those not interested in

using the processor in their design. The Eclypse Z7 is supported under Vivado's free

WebPACK™ license, which means the software is completely free to use, including the

Logic Analyzer and High-level Synthesis (HLS) features. The Logic Analyzer assists

with debugging logic that is running in hardware, and the HLS tool allows C code to be

directly compiled into HDL.

Digilent currently does not provide hardware platforms or examples for Xilinx's Vitis

Unified Software Platform, however Vitis support is planned for the near future.

Design resources, example projects, and tutorials are available for download at

the Eclypse Z7 Resource Center.

Zynq APSoC Architecture

The Zynq APSoC is divided into two distinct subsystems: The Processing System (PS)

and the Programmable Logic (PL). The figure below shows an overview of the Zynq

APSoC architecture, with the PS colored light green and the PL in yellow. Note that the

PCIe Gen2 controller and Multi-gigabit transceivers are not available on the Zynq-7020

device.

The PL is nearly identical to a Xilinx 7-series Artix FPGA, except that it contains several

dedicated ports and buses that tightly couple it to the PS. The PL also does not contain

the same configuration hardware as a typical 7-series FPGA, and it must be configured

either directly by the processor or via the JTAG port.

The PS consists of many components, including the Application Processing Unit (APU,

which includes 2 Cortex-A9 processors), Advanced Microcontroller Bus Architecture

(AMBA) Interconnect, DDR3 Memory controller, and various peripheral controllers with

their inputs and outputs multiplexed to 54 dedicated pins (called Multiplexed I/O, or MIO

pins). Peripheral controllers that do not have their inputs and outputs connected to MIO

pins can instead route their I/O through the PL, via the Extended-MIO (EMIO) interface.

The peripheral controllers are connected to the processors as slaves via the AMBA

interconnect, and contain readable/writable control registers that are addressable in the

processors’ memory space. The programmable logic is also connected to the

interconnect as a slave, and designs can implement multiple cores in the FPGA fabric

that each also contain addressable control registers. Furthermore, cores implemented in

the PL can trigger interrupts to the processors and perform DMA accesses to DDR3

memory.

There are many aspects of the Zynq APSoC architecture that are beyond the scope of

this document. For a complete and thorough description, refer to the Zynq Technical

Reference manual.

The tables in the dropdowns below depict the external components connected to the

MIO pins of the Eclypse Z7. The Vivado board files found on the Eclypse Z7 Resource

Center can be used to properly configure the PS to work with these peripherals. It is

also possible to use the example projects found on the resource center as a starting

point for custom designs.

MIO 0-15 : Bank 500

MIO 500 3.3 V

Peripherals

GPIO

SPI Flash

ENET 0

SYZYGY

UART 0

0 (N/C)

DQ0

DQ1

DQ2

DQ3

SCLK

7 (N/A)

SCLK FB

Ethernet Reset

10 (N/A)

11 (N/A)

DNA SCL (I2C 0)

DNA SDA (I2C 0)

UART Input

UART Output

MIO 16-53 : Bank 501

MIO 501 1.8V

Peripherals

ENET 0

USB 0

SD 0

TXCK

TXD0

TXD1

TXD2

TXD3

TXCTL

RXCK

RXD0

RXD1

RXD2

RXD3

RXCTL

DATA4

DIR

STP

NXT

DATA0

DATA1

DATA2

DATA3

CLK

DATA5

DATA6

DATA7

CCLK

CMD

USB Reset

Ethernet Interrupt (GPIO)

USB Overcurrent (GPIO)

50 (N/C)

51 (N/C)

MDC

MDIO

Functional Description

1. Power Supplies

The Eclypse Z7 power circuitry was carefully designed to meet the requirements of the

Zynq-7000 and all peripherals while providing the flexibility needed to power a variety of

different configurations of Zmod/SYZYGY modules.

An overview of the power circuit is shown in Figure 1.1.

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