Digilent NetFPGA-SUME Manual de usuario

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NetFPGA-SUME™ Reference Manual

RevisedApril11,2016

ThismanualappliestotheNetFPGA-SUMErev.C

DOC#: 502-301

Other product and company names mentioned may be trademarks of their respective owners.

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Overview

FPGA, the NetFPGA-SUME is an ideal

platform for high-performance and

high-density networking design.

32 GTH serial transceivers have been

used to provide access to 8 lanes of

end-point PCI-E (Gen3 x8), 4 SFP+

(10Gbps) ports, 2 SATA-III ports

(6Gbps), and 18 data-rate-adjustable

GTH ports through a HPC-FMC

connector and a QTH connector.

Wide high-speed memory interfaces in the form of three 72 MBit QDRII+ SRAMs with 36 bit buses and two 4GB

DDR3 SODIMMs with 64 bit buses provide an ideal memory solution for common networking applications.

FPGA

Xilinx Virtex-7 XC7V690T FFG1761-3

Memory

Two 4GB DDR3 SODIMMs (MT8KTF51264Hz-

1G9E1)

64 bit wide buses clocked at

850 MHz (1700 mbps)

Three 72Mbit QDRII+ SRAMs

(CY7C25652KV18-500BZXC)

36 bit wide buses clocked at

500 MHz (1000 mbps)

Storage

Two SATA III ports (6 gbps via GTH

transceivers)

Micro-SD Card Slot

Two 512Mbit Micron StrataFlash parallel flash

modules (PC28F512G18A)

For bitfile storage only

Communication Interfaces

PCI-E Gen3 x8 supporting 8Gbps/lane

Four SFP+ interfaces supporting 10Gbps

Four globally unique MAC addresses

USB-UART

I2C Pmod port

Expansion Connectors

QTH Connector (8 GTH transceivers)

One HPC FMC Connector (10 GTH transceivers

and 68 User I/Os)

One 12-pin Pmod port (8 User I/Os)

Programming

Micro USB Connector for JTAG programming and

debugging (shared with USB-UART interface)

Xilinx CPLD XC2C512 for FPGA configuration from

parallel flash

Power Management

Two Linear Technology Power System Managers

(LTC2974)

Provide current measuring on all major

power rails

Other Features

User LEDs and Push Buttons

PROG Push Button for manual FPGA Reset

FPGA Configuration LEDs

I2C Mux (PCA9548A) for controlling all onboard

I2C buses

The NetFPGA-SUME board.

Features include:

NetFPGA-SUME™ Reference Manual

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Figure 1. NetFPGA-SUME component callouts.

The NetFPGA-SUME is compatible with Xilinx's new high-performance Vivado® Design Suite as well as the ISE®

toolset, which includes ChipScope™ and EDK. The Virtex-7 XC7V690T FPGA is not a WebPack device, which means

full licenses will need to be acquired for these tools in order to build designs that target the NetFPGA-SUME.

Licensing information for Vivado can be found here. Academic institutes can make a request to the Xilinx

University Program for a donation of full Vivado licenses here.

A simplified block diagram that depicts the major features of the NetFPGA-SUME is displayed in Fig. 2.

NetFPGA-SUME™ Reference Manual

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FIgure 2. NetFPGA-SUME block diagram.

1 NetFPGAOrganization

This board is supported by reference designs and IP created by the NetFPGA organization. For more information on

the NetFPGA organization, go here.

2 Power

2.1 InputSupply

The NetFPGA-SUME receives power via a 2 x 4 pin PCI Express Auxiliary Power Connector. The 2x4 pin PCI Express

Auxiliary Power receptacle (header J14) can accept both 2x3 and 2x4 pin PCI Express Auxiliary Power Plugs found

on a standard ATX power supply. When installed on a PC motherboard, you can plug the 2x3 or 2x4 pin PCI Express

power supply connector directly into header J14. When used in standalone mode (without a PC motherboard),

NetFPGA-SUME™ Reference Manual

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pins 15 and 16 of the main 20 pin connector of the standard ATX power supply must be shorted together, as

shown in Figure 3. If these pins aren't shorted together then the power supply will not turn on.

Figure 3. Pin 15 and 16 of Standard ATX power supply shorted together.

According to Revision 1.0 of the PCI Express 225 W/300 W High Power Card Electromechanical Specification, the

2x3 pin plug is guaranteed to deliver up to 75 watts of power, while the 2x4 pin plug is guaranteed to deliver up to

150 watts of power. While the board may be powered by either a 2x3 pin or a 2x4 pin PCI Express Auxiliary Power

plug, due to the potential for high power consumption, Digilent recommends using a 2x4 pin plug to provide power

whenever possible.

Figure 4. Power connector (J14).

Figure 4 describes pin-out of the power connector (header J14) when a 2x4 pin or a 2x3 pin plug is used. The

Sense0 and Sense1 pins are to be connected to GND when power is present, and left floating otherwise. Since the

2x3 pin plug does not include a Sense1 pin, it's possible to determine what type of plug is present, and thus how

much power can be consumed.

The FPGA logic can determine whether or not a 2x4 pin is present by enabling an internal pull-up on pin AW42 and

then checking the state of that pin. If logic '0' is seen on AW42, then a 2x4 plug is connected and up to 150 watts of

power can be drawn. If logic '1' is on AW42, then a 2x3 plug is connected, and the board's power consumption

should be limited to 75 watts or less.

2.2 PowerSupplyTopology

The high performance Virtex-7 FPGA, QDRII+ memories, and DDR3 memories featured on the NetFPGA-SUME

require several different supply voltages (supply rails) in order to function. These components also require that the

supply rails are sequenced on and off in a particular order. Table 1 lists the various supply rails, their nominal

voltages, and rated output currents.

NetFPGA-SUME™ Reference Manual

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Supply Rail

Nominal Voltage

Rated Output Current

VCC1V0

1.0V

40A

VCC1V8

1.8V

15A

VCC2V0

2.0V

MGTAVCC

1.0V

MGTAVTT

1.2V

VCC3V3

3.3V

15A

VCC1V5

1.5V

15A

MGTVAUX

1.8V

DDRVTT

0.75V

+/- 3A

QDRVTT

0.75V

+/- 3A

Table 1. Supply rails, voltages, and currents.

These supply rails are derived from the 12V input (VCC12V0, comes from header J14) using eight high efficiency

switching regulators and one low drop out (LDO) linear regulator from Linear Technology. Since both the DDR3 and

QDRII+ I/O supplies are powered from the VCC1V5 rail, two ferrite beads are also included to prevent high speed

switching noise caused by one memory from affecting the other. Figure 6 shows how the various supplies are

derived from the input.

A Linear Technology LTC6909 is used to generate six out of phase 302 KHz clocks. Each clock is 60 degrees out of

phase with any of the other clock outputs (see Fig. 5). These out of phase clocks are used as the input clocks for the

regulators that produce the high power output supply rails (VCC1V0, VCC1V5, VCC1V8, VCC3V3, and MGTAVCC).

The LTC3839, which produces the VCC1V0 supply rail, is a dual phase converter that directly utilizes the OUT1 clock

and indirectly utilizes the OUT4 clock. The use of out of phase clocks reduces the input RMS ripple current.

Figure 5. LTC6909 clock output phase relationship.

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Page 6of 18

Figure 6. Regulator topology.

2.3 PowerSequencingandSupervising

The components on the NetFPGA-SUME require that the supply voltages be sequenced on and off in a particular

order. The NetFPGA-SUME utilizes two Linear Technology LTC2974s to ensure that these sequencing requirements

are met. Each LTC2974 supports "cascade sequence ON with time-based sequence off" and can monitor the input

voltage, four output voltages, four output currents, and four external temperatures using a 16-bit ADC.

NetFPGA-SUME™ Reference Manual

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Page 7of 18

Additionally, the LTC2974 can margin and trim up to four output voltages using a 10-bit DAC, allowing for more

precise output voltages.

Figure 7. LTC2974 sequencer and supervisor.

Figure 7 depicts the connections between the two LTC2974s, as well as the signals that are used to control the

power on and off sequence. When the input voltage (VCC12V0) exceeds 10 volts, the LTC2974s will perform a

power on sequence when the power switch (SW1) is placed in the "ON" position. When a power on sequence is

performed, the rails come up in the following order:

1. VCC1V0

2. VCC1V8

3. VCC2V0

4. MGTAVCC

5. MGTAVTT

6. VCC3V3

7. VCC1V5, QDRVTT, and DDRVTT

8. MGTVAUX

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When the input voltage falls below 9 volts, or the power switch transitions to the "OFF" position, the LTC2974s

perform a time-based off sequence and the rails come down in the following order:

1. MGTVAUX

2. VCC1V5, QDRVTT, and DDRVTT

3. VCC3V3

4. MGTAVTT

5. MGTAVCC

6. VCC2V0

7. VCC1V8

8. VCC1V0

Figure 8. Power ON/OFF sequence.

The LTC2974s constantly monitor the output voltage, current, and temperature associated with each channel

(supply rail). This information, referred to as telemetry data, is used to determine the on status of each supply rail,

as well as monitor for fault and warning conditions. When a fault or a warning occurs, the FPGA application may be

notified via an interrupt that is signaled by the LTC2974's ALERTB, AUXFAULTB, or FAULTB1 pins. The FPGA

application may then read (using I2C) one or more of the LTC2974 status registers (defined in the datasheet) to

determine the source of the fault or the warning. The output voltage, current, power, and temperature associated

with any channel may also be read using the applicable PMBUS (I2C) commands, which are defined in the LTC2974

datasheet.

In order to generate faults and warnings, each channel of the LTC2974 must be configured with a nominal output

voltage, under voltage warning limit, over voltage fault limit, under current warning limit, over current warning

limit, over current fault limit, under current fault limit, under temperature warning limit, under temperature fault

limit, and over temperature fault limit. Tables 2 and 3 describe the voltage and current limits as pre-configured by

Digilent during the manufacturing process.

Supply

Rail

Under Voltage

Fault Limit

Under Voltage

Warning Limit

Nominal

Voltage

Overvoltage

Warning Limit

Overvoltage Fault

Limit

VCC1V0

0.9V

0.925V

1.0V

1.075V

1.1V

VCC1V8

1.62V

1.665V

1.8V

1.935V

1.98V

VCC2V0

1.8V

1.85V

2.0V

2.15V

2.2V

MGTAVCC

0.9V

0.925V

1.0V

1.075V

1.1V

MGTAVTT

1.08V

1.11V

1.2V

1.29V

1.32V

VCC3V3

2.97V

3.0525V

3.3V

3.5475V

3.63V

VCC1V5

1.35V

1.3875V

1.5V

1.6125V

1.65V

MGTVAUX

1.62V

1.665V

1.8V

1.935V

1.98V

DDRVTT

N/A

0.75V

N/A

QDRVTT

N/A

0.75V

N/A

Table 2. Voltage fault and warning limits.

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Page 9of 18

Note: the DDRVTT and QDRVTT rails are not directly monitored by the LTC2974s.

Supply Rail

Undercurrent Fault Limit

Rated Current

Overcurrent Warning Limit

Overcurrent Fault Limit

VCC1V0

-1A

40A

44A

VCC1V8

-2A

15A

15.5A

VCC2V0

-1A

MGTAVCC

-1A

8.5A

MGTAVTT

-1A

3.1992A

VCC3V3

-1A

15A

15.5A

VCC1V5

-1A

15A

15.5A

MGTVAUX

-1A

1.0996A

DDRVTT

N/A

QDRVTT

N/A

Table 3. Current fault and warning limits

Note: the DDRVTT and QDRVTT rails are not directly monitored by the LTC2974s.

2.4 FaultandWarningInterruptSources

When the LTC2974 detects a fault or a warning condition it may signal an interrupt by driving the ALERTB,

AUXFAULTB, or FAULTB1 pins.

The ALERTB pin of the LTC2974 is an open drain output that is driven low whenever a fault or warning occurs. The

ALERTB pins of the two LTC2974s (IC43 and IC44) are connected in a wire-and fashion via the PCON_ALERT_B net

to pin J41 of the FPGA (IC12), as shown in Fig. 9. Enabling the internal pull-up on pin J41 will allow the FPGA

application to use this pin as an interrupt when any of the following situations occur:

Output overvoltage or under voltage fault/warning

Output over current or under current fault/warning

Over temperature fault/warning

Channel output voltage has not reached or exceeded the under voltage fault limit set for that channel

within TON_MAX_FAULT_LIMIT milliseconds (set to 15ms) of the output being enabled

When any of the above faults occur, the PCON_ALERT_B net will be driven low until the fault condition has been

removed and the CLEAR_FAULTS command has been sent to both of the LTC2974s (IC43 and IC44).

Figure 9. ALERTB interrupt source.

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Page 10 of 18

The AUXFAULTB pins of the two LTC2974s are connected in a wire-and fashion to the cathode of a Shottky diode

via the AUXFAULT net, as shown in Fig. 10. The anode of the Shottky diode is connected to pin M41 on the FPGA

via the PCON_AUXFAULT_B net and protects the FPGA pin from high voltages. The LTC2974s are configured to

drive the AUXFAULTB pin low when any of the follow conditions occur:

Output overvoltage fault on any channel

Output over current or under current fault on any channel

When any of the above conditions occur, the AUXFAULT net will be driven low, which causes the

PCON_AUXFAULT_B net to be pulled low through the diode. The AUXFAULT net will remain driven low until

LTC2974 experiencing the fault condition is commanded to re-enter the ON state. Enabling the internal pull-up on

pin M41 will allow the FPGA application to detect when one of the faults described above has occurred.

Figure. 10. AUXFUALTB interrupt source.

The FAULTB1 pin of the LTC2974 is bi-directional open-drain input/output that can be configured to drive low in

response to any channel entering a "faulted off state". The LTC2974 can also be configured to disable any given

channel in response to a logic low being detected on the FAULTB1 pin. However, it has been pre-configured by

Digilent during manufacturing to serve strictly as an output that indicates when any channel has faulted off.

The FAULTB1 pin of the two LTC2974s are connected in a wire-and fashion to the gate of a transistor (N-FET). This

transistor connects to the PCON_FAULT1 net, which is in turn connected to pin N40 of the FPGA, as shown in Fig.

11. When neither of the FAULTB1 pins is asserted low, the gate of the transistor is pulled high and the

PCON_FAULT1 net is connected to ground. When any channel enters the "faulted off state," the gate of the

transistor is driven low and the transistor turns off. Enabling an internal pull-up on pin N40 will allow the FPGA

application to detect logic '1' when any channel has faulted off and logic '0' when no channels have faulted off.

Figure 11. FAULTB1 interrupt source.

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