Cypress FR Series Manual de usuario

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www.cypress.com Document No. 002-05317 Rev. *C 1 
AN205317 
FR, MB91460, FR Clocks 
 
The FR Family MCUs feature a sophisticated clock distribution scheme with the different clock sources such as RC 
Clock, Main Clock, PLL Clock, Modulated PLL Clock, and Sub Clock. The core and the peripherals are connected to 
different clock trees that can be connected to different clock sources and clock frequencies to allow for a fine-grained 
control over the required operation speed and power consumption. 
Contents 
1Introduction...............................................................1 
2Clock Tree................................................................1 
2.1 Overview ......................................................1 
2.2 RC Clock ......................................................2 
2.3 Main Clock ......................................................2 
2.4 PLL Clock ......................................................2 
2.5 Sub Clock ......................................................3 
2.6 Clock Modulator ...............................................3 
3Registers ..................................................................5 
3.1 Clock Source Control Register (CLKR)...............5 
3.2 Clock Division Setting Register 0 (DIVR0)..........5 
3.3 Clock Division Setting Register 0 (DIVR1)..........5 
3.4 Clock Source Configuration Register (CSCFG)..6 
3.5 Oscillation Control Register (OSCCR) ................7 
3.6 PLL Control Registers (PLLDIVM)......................7 
3.7 PLL Control Registers (PLLDIVN).......................7 
3.8 PLL Control Registers (PLLDIVG)......................8 
3.9 PLL Control Registers (PLLMULG).....................8 
3.10 PLL Control Registers (PLLCTRL)......................8 
3.11 Clock Supervisor Control Register (CSVCR)......9 
3.12 Clock Modulator Control Register (CMCR).......10 
3.13 Clock Modulation Parameter Register (CMPR) 10 
4Using the start.asm ................................................11 
5Clock setup sequence............................................13 
5.1 Clock Setup Sequence (Example)....................14 
6Clock Modulator Configuration...............................17 
7Clocks Example......................................................18 
7.1 Starting Clock Modulator ..................................18 
7.2 Stopping Clock Modulator.................................18 
8Additional Information.............................................19 
Document History............................................................20 
 
 
1 Introduction 
The FR Family MCUs feature a sophisticated clock distribution scheme with the different clock sources such as RC 
Clock, Main Clock, PLL Clock, Modulated PLL Clock, and Sub Clock. The core and the peripherals are connected to 
different clock trees that can be connected to different clock sources and clock frequencies to allow for a fine-grained 
control over the required operation speed and power consumption. 
2 Clock Tree 
The FR Family MCUs feature a sophisticated clock distribution that allows for fine-grained control over the used 
clocks and frequencies. The details are given below. 
2.1 Overview 
The FR Family can be used with 2 different external clocks: the Main Clock and the Sub Clock and 1 internal (on-
chip) clock: the RC Clock. The external clocks may be connected to an oscillator, an oscillation circuit of a crystal and 
capacitors, or an external clock supply. The internal RC Clock can be configured at 2 MHz or 100 kHz. 
Internally, 4 different clocks are used: the core clock CLKB, the peripheral clock CLKP, External bus clock CLKT and 
CAN clock CLKCAN. The CLKB provides the clock to the CPU. The CLKCAN provides the clock to the CAN 
controllers. The CLKP provides the clock for all other peripherals. 
Each of these four clocks features a separate prescaler. The following block diagram shows the clock distribution. 
 

FR, MB91460, FR Clocks

www.cypress.com Document No. 002-05317 Rev. *C 2

Figure 1. Block Diagram of Clock Circuitry

2.2 RC Clock

The RC clock is available on all FR devices. The RC clock CLKRC is the output clock of the internal RC oscillator.

The RC-oscillator is enabled at power on.

The timeout counter is clocked with CLKRC.

The typical value of these clocks is 2 MHz and 100 kHz, respectively.

2.3 Main Clock

The Main Clock is available on all FX devices. Main clock / 2 is the default clock selected after power on.

The allowed input frequency is limited to the range 3.5 MHz to 16 MHz when an oscillation circuit is used. The range

is from 3.5 MHz to 4 MHz when an external clock signal is supplied. With respect to EMI considerations, a frequency

of 4 MHz is recommended.

2.4 PLL Clock

The PLL Clock is available on all FR devices and is based on the Main Clock. By default, it is disabled. Before

enabling it, it must be configured.

The PLL Clock also feeds the Clock Modulator. The Clock Modulator is discussed in subsequent sections.

FR, MB91460, FR Clocks

www.cypress.com Document No. 002-05317 Rev. *C 3

2.5 Sub Clock

The Sub Clock is available on all FR dual-clock devices. It can be used as a supplemental clock for low-power

applications. By default, it is enabled, but needs to be selected before use.

The allowed input frequency is limited to the range 32 kHz to 100 kHz when an oscillation circuit is used, while the

range is extended from 0 Hz to 100 kHz when an external clock signal is supplied. Most time-dependent peripherals

offer clock prescalers to allow for full-second intervals when a frequency of 32.768 kHz is provided.

2.6 Clock Modulator

The clock modulator is primarily used to minimize the electromagnetic interference (EMI). It scatters the spectrum of

the clock signal over a wide range of frequencies in order to do so.

The source of the clock for the modulator is the PLL Clock (CLKPLL). The minimum and maximum frequency for a

given reference frequency of CLKPLL and the degree of modulation is dependent on the parameters like resolution of

modulation range and modulation degrees. The average frequency of the resultant Modulated PLL Clock - CLKMOD

is equal to the reference frequency CLKPLL.

As a result of the modulation, there results in skew in the phase of CLKMOD with reference to CLKPLL. This ‘Phase

Skew’ is the maximal phase shift of the CLKMOD relative to the CLKPLL in terms of clock periods of the CLKPLL.

The phase skew is dependent on configuration such resolution and modulation degrees at a given PLL frequency

(CLKPLL).

The following figure explains the phase skew:

Figure 2. Phase Skew

Example:

For CLKPLL of 16 MHz (at a given CMPR configuration), if 100 periods of CLKMOD takes 6.5 microseconds then

phase skew is calculated as follows:

One period of CLKPLL = (1/16 MHz) = 62.5 ns, hence the Phase Skew = (62.5 ns * 100 –6.5 µs)/ 62.5 ns = -4

periods.

The recommended setting of the modulation parameters (for a given CLKPLL) with the resultant min/max frequency

and phase skew is discussed in greater detail in the hardware manual.

If the USART is used in the asynchronous mode with the clock modulator is switched on, then it would affect the baud

rate of the USART and introduce deviation in the baud rate. In some cases, there may be deviation in the baud rate

which may not be acceptable.

Example:

Let’s consider the case where the required Modulated PLL Clock - CLKMOD is 16 MHz with the desired baud rate for

the USART in asynchronous mode is 2 MBPS.

FR, MB91460, FR Clocks

www.cypress.com Document No. 002-05317 Rev. *C 4

Here the BGRn register needs to be configured with the value of 0x0007. So the deviation in the baud rate as per

USART chapter in the hardware manual is 0. But the CLKMOD would also have an impact on this deviation of baud

rate.

Lets also consider that the character format is 8E1 that means one USART character contains 11 bits (1 Start bit + 8

Data bits + 1 Even Parity bit + 1 Stop bit).

If the data that needs to be transmitted is 0x00, the parity bit would also be zero and the USART output should

remain at low level for period of 10 bits. These 10 bits corresponds to the 80 clock periods (cycles) of CLKMOD.

Let’s also consider that the clock modulator is configured for the resolution of 11 and modulation degree of 1 then the

“± phase skew min/max” would be 7.875. This means that the 80 clock periods would be either shortened to 72.125

clock periods or may get lengthened to 87.875 clock period that is the error of up to 1 bit. This may cause parity error

or framing error respectively at the receiver.

FR, MB91460, FR Clocks

www.cypress.com Document No. 002-05317 Rev. *C 5

3 Registers

The configuration of the Clock Tree is controlled by the following Registers:

3.1 Clock Source Control Register (CLKR)

Selects the clock source for the base clock used to run the MCU and controls the PLL.

Bit No.

Name

Explanation

Initial

Value

Operation

Undefined

Always write 0

SCKEN

Sub clock select enable

Stop Sub clock oscillator

Enable Sub clock selection

PLL1EN

Enable Main PLL operation

Halt Main PLL

Enable Main PLL operation

CLKS1,

CLKS0

Clock source selection

Main clock input from X0/X1 divided by

Main PLL

Sub clock

3.2 Clock Division Setting Register 0 (DIVR0)

Sets the division ratio for the clocks used for internal device operation.

Bit No.

Name

Explanation

Initial

Value

Operation

7-4

B3,B2,

B1,B0

Sets the clock division ratio

for the clock used by the

CPU, internal memory, and

internal buses (CLKB).

0000

Base clock / 1

0001

Base clock / 2

…

1111

Base clock / 16

3-0

P3,P2,

P1,P0

Sets the clock division ratio

for the clock used by the

peripheral circuits and

peripheral bus (CLKP).

0011

0000

Base clock / 1

0001

Base clock / 2

…

1111

Base clock / 16

3.3 Clock Division Setting Register 0 (DIVR1)

Sets the division ratio for the clocks used for internal device operation.

Bit No.

Name

Explanation

Initial

Value

Operation

7,6,5,4

T3,T2,

T1,T0

Sets the clock division ratio

(relative to the base clock)

for the clock used by the

external bus interface

(CLKT).

0000

Base clock / 1

0001

Base clock / 2

…

1111

Base clock / 16

3,2,1,0

Undefined

Always write 0

FR, MB91460, FR Clocks

www.cypress.com Document No. 002-05317 Rev. *C 6

3.4 Clock Source Configuration Register (CSCFG)

Bit No.

Name

Explanation

Initial

Value

Operation

EDSUEN

EDSU/MPU Enable

EDSU/MPU is (clock) disabled

EDSU/MPU is (clock) enabled

PLLLOCK

PLL Lock

PLL is in the un-locked state

PLL is in the locked state

RCSEL

CLKRC Selector

CLKRC is set to 100kHz

CLKRC is set to 2MHz

MONCKI

Clock Monitor MONCLK

inverter

MONCLK mark level is low

MONCLK mark level is high

CSC3

Clock Source Selection for

LCD Controller

LCD Controller is sourced by Sub

Oscillator

LCD Controller is sourced by RC

Oscillator (100kHz)

CSC2

Clock Source Selection for

Sub clock calibration

Sub clock Calibration is sourced by Sub

Oscillator

Sub clock Calibration is sourced by RC

Oscillator(100kHz)

1,0

CSC1,

CSC0

Clock Source Selection for

RTC

Real Time Clock is sourced by Main

Oscillator

Real Time Clock is sourced by Sub

Oscillator

Real Time Clock is sourced by RC

Oscillator(100kHz)

Setting prohibited

FR, MB91460, FR Clocks

www.cypress.com Document No. 002-05317 Rev. *C 7

3.5 Oscillation Control Register (OSCCR)

Bit No.

Name

Explanation

Initial

Value

Operation

7-2

Undefined

Always write 0

OSCDS2

Stop Sub clock oscillation in

Sub-RUN on CLKRC

X+

Write: Does not halt Sub clock

oscillation during Sub-

RUN on CLKRC

Read: Sub clock mode can be selected

after the

oscillation stabilization time elapses

Write: Halt Sub clock oscillation during

Sub-RUN on

CLKRC

Read: Selecting Sub clock mode is

prohibited

OSCDS1

Stop Sub clock oscillation in

Sub-RUN on CLKRC

X+

Write: Does not halt Main clock

oscillation during Sub clock mode

Read: Main clock mode can be selected

after the

oscillation stabilization time elapses

Write: Halt Main clock oscillation during

Sub clock mode

Read: Selecting Main clock mode is

prohibited

3.6 PLL Control Registers (PLLDIVM)

Bit No.

Name

Explanation

Initial Value

Value

Operation

7,6,5,4

Undefined

Always write 0

3,2,1,0

DVM3-0

PLL divide-by-M selection

0000*

XXXX+

0000

CLKVCO / 1

0001

CLKVCO / 2

…

1111

CLKVCO / 16

3.7 PLL Control Registers (PLLDIVN)

Bit No.

Name

Explanation

Initial Value

Value

Operation

7,6

Undefined

Always write 0

5-0

DVN5-0

PLL divide-by-N selection

0000*

XXXX+

0000

CLKPLL/ 1

0001

CLKPLL/ 2

…

1111

CLKPLL/ 16

* INITX pin input, watchdog reset

+ Software reset

FR, MB91460, FR Clocks

www.cypress.com Document No. 002-05317 Rev. *C 8

3.8 PLL Control Registers (PLLDIVG)

Bit No.

Name

Explanation

Initial Value

Value

Operation

7-4

Undefined

Always write 0

3-0

DVNG-0

PLL auto gear start/end

divide-by-G selection

0000*

XXXX+

0000

Auto gear disabled

0001

CLKVCO / 2

…

1111

CLKVCO / 16

3.9 PLL Control Registers (PLLMULG)

Bit No.

Name

Explanation

Initial Value

Value

Operation

7-0

MLG7-0

PLL auto gear divide-by-G

step multiplier selection

0000*

XXXX+

00000000

Divide-by-G step x 1 (multiply by 1)

00000001

Divide-by-G step x 2 (multiply by 2)

…

11111111

Divide-by-G step x 256 (multiply by

256)

3.10 PLL Control Registers (PLLCTRL)

Bit No.

Name

Explanation

Initial

Value

Operation

7,6,5,4

Undefined

Always write 0

IEDN

Interrupt Request Enable

Gear DOWN

X+

Gear DOWN interrupt request disabled

Gear DOWN interrupt request enabled

GRDN

Interrupt Flag Gear DOWN.

X+

Gear DOWN interrupt not active

Gear DOWN interrupt active

IEUP

Interrupt Request Enable

Gear UP

X+

Gear UP interrupt request disabled

Gear UP interrupt request enabled

GRUP

Interrupt Flag Gear UP

X+

Gear UP interrupt not active

Gear UP interrupt active

* INITX pin input, watchdog reset

+ Software reset

FR, MB91460, FR Clocks

www.cypress.com Document No. 002-05317 Rev. *C 9

3.11 Clock Supervisor Control Register (CSVCR)

The Clock Supervisor Control Register (CSVCR) sets the operation mode of the Clock Supervisor.

Bit No.

Name

Explanation

Initial

Value

Operation

SCKS

Sub clock select

Do not enable ports for MCLK_MISSING

and

SCLK_MISSING output pins

Enable ports for MCLK_MISSING and

SCLK_MISSING output pins

Main clock missing

Do not perform reset upon transition

from Main clock to

Sub clock modes if Sub clock is already

missing

Perform reset upon transition from Main

clock to Sub

clock modes if Sub clock is already

missing

Sub clock missing

Disable Sub clock supervisor

Enable Sub clock supervisor

RCE

RC oscillator enable

Disable Main clock supervisor

Enable Main clock supervisor

MSVE

Main clock supervisor

enable

Disable RC-oscillator

Enable RC-oscillator

SSVE

Sub clock supervisor enable

Missing Sub clock has not been

detected

Missing Sub clock has been detected

SRST

Sub clock mode reset

Missing Main clock has not been

detected

Missing Main clock has been detected

OUTE

Output enable

32k oscillation used as Sub clock

RC oscillation used as Sub clock

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