Cypress Semiconductor CY7C1381D Manual de usuario

18-Mbit (512K x 36/1M x 18) Flow-Through SRAM

CY7C1381D, CY7C1381F

CY7C1383D, CY7C1383F

Cypress Semiconductor Corporation • 198 Champion Court • San Jose,CA 95134-1709 • 408-943-2600

Document #: 38-05544 Rev. *F Revised Feburary 07, 2007

Features

• Supports 133 MHz bus operations

• 512K × 36 and 1M × 18 common IO

• 3.3V core power supply (VDD)

• 2.5V or 3.3V IO supply (VDDQ)

• Fast clock-to-output time

— 6.5 ns (133 MHz version)

• Provides high performance 2-1-1-1 access rate

• User selectable burst counter supporting Intel®Pentium®

interleaved or linear burst sequences

• Separate processor and controller address strobes

• Synchronous self-timed write

• Asynchronous output enable

• CY7C1381D/CY7C1383D available in JEDEC-standard

Pb-free 100-pin TQFP, Pb-free and non Pb-free 165-ball

FBGA package. CY7C1381F/CY7C1383F available in

Pb-free and non Pb-free 119-ball BGA package

• IEEE 1149.1 JTAG-Compatible Boundary Scan

• ZZ sleep mode option

Functional Description [1]

The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F is a

3.3V, 512K x 36 and 1M x 18 synchronous flow through

SRAMs, designed to interface with high-speed

microprocessors with minimum glue logic. Maximum access

delay from clock rise is 6.5 ns (133 MHz version). A 2-bit

on-chip counter captures the first address in a burst and

increments the address automatically for the rest of the burst

access. All synchronous inputs are gated by registers

controlled by a positive edge triggered clock input (CLK). The

synchronous inputs include all addresses, all data inputs,

address pipelining chip enable (CE1), depth-expansion chip

enables (CE2and CE3 [2]), burst control inputs (ADSC, ADSP,

and ADV), write enables (BWx, and BWE), and global write

(GW). Asynchronous inputs include the output enable (OE)

and the ZZ pin.

The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F

allows interleaved or linear burst sequences, selected by the

MODE input pin. A HIGH selects an interleaved burst

sequence, while a LOW selects a linear burst sequence. Burst

accesses can be initiated with the processor address strobe

(ADSP) or the cache controller address strobe (ADSC) inputs.

Address advancement is controlled by the address

advancement (ADV) input.

Addresses and chip enables are registered at rising edge of

clock when address strobe processor (ADSP) or address

strobe controller (ADSC) are active. Subsequent burst

addresses can be internally generated as controlled by the

advance pin (ADV).

The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F

operates from a +3.3V core power supply while all outputs

operate with a +2.5V or +3.3V supply. All inputs and outputs

are JEDEC-standard and JESD8-5-compatible.

Selection Guide

133 MHz 100 MHz Unit

Maximum Access Time 6.5 8.5 ns

Maximum Operating Current 210 175 mA

Maximum CMOS Standby Current 70 70 mA

Notes:

1. For best practices or recommendations, please refer to the Cypress application note AN1064, SRAM System Design Guidelines on www.cypress.com.

2. CE3, CE2are for TQFP and 165 FBGA packages only. 119 BGA is offered only in 1 chip enable.

[+] Feedback

CY7C1381D, CY7C1381F

CY7C1383D, CY7C1383F

Document #: 38-05544 Rev. *F Page 2 of 29

Logic Block Diagram – CY7C1381D/CY7C1381F [3] (512K x 36)

Logic Block Diagram – CY7C1383D/CY7C1383F[3] (1M x 18)

ADDRESS

BURST

COUNTER

AND LOGIC

CLR

ENABLE

SENSE

AMPS

OUTPUT

BUFFERS

INPUT

REGISTERS

MEMORY

ARRAY

MODE

[1:0]

DQs

DQP A

DQP B

DQP C

DQP D

A0, A1, A

ADV

CLK

ADSP

ADSC

BW D

BW C

BW B

BW A

BWE

CE1

CE2

CE3

SLEEP

DQ A

DQP

BYTE

WRITE REGISTER

DQ B

DQP

WRITE REGISTER

DQ C

DQP

WRITE REGISTER

BYTE

WRITE REGISTER

DQP

BYTE

WRITE REGISTER

DQP

BYTE

WRITE REGISTER

DQ C

DQP

WRITE REGISTER

DQ B

DQP

WRITE REGISTER

DQ A

DQP

BYTE

WRITE REGISTER

ADDRESS

ADV BURST

COUNTER AND

SENSE

AMPS

MEMORY

ARRAY

OUTPUT

BUFFERS

INPUT

REGISTERS

MODE

BWE

A0,A1,A

,DQP

ENABLE

A[1:0]

DQs

DQP A

DQP B

,DQP

WRITE DRIVER

,DQP

WRITE DRIVER

SLEEP

CONTROL

Note:

3. CY7C1381F and CY7C1383F have only 1 chip enable (CE1).

[+] Feedback

CY7C1381D, CY7C1381F

CY7C1383D, CY7C1383F

Document #: 38-05544 Rev. *F Page 3 of 29

Pin Configurations

VSS

VDD

DQPB

DQB

VDDQ

VSSQ

DQB

VSSQ

VDDQ

DQB

VSS

VDD

DQA

VDDQ

VSSQ

DQA

VSSQ

VDDQ

DQA

DQPA

DQPC

DQC

VDDQ

VSSQ

DQC

VSSQ

VDDQ

DQC

VDD

VSS

DQD

VDDQ

VSSQ

DQD

VSSQ

VDDQ

DQD

DQPD

CE1

CE2

BWD

BWC

BWB

BWA

CE3

VDD

VSS

CLK

BWE

ADSC

ADSP

ADV

100

MODE

CY7C1381D

(512K x 36)

VSS/DNU

VSS

VDD

VDDQ

VSSQ

DQPA

DQA

VSSQ

VDDQ

DQA

VSS

VDD

DQA

VDDQ

VSSQ

DQA

VSSQ

VDDQ

VSSQ

DQB

VSSQ

VDDQ

DQB

VDD

VSS

DQB

VDDQ

VSSQ

DQB

DQPB

VSSQ

VDDQ

CE1

CE2

BWB

BWA

CE3

VDD

VSS

CLK

BWE

ADSC

ADSP

ADV

100

MODE

CY7C1383D

(1M x 18)

VSS/DNU

100-pin TQFP Pinout (3 Chip Enable)

[+] Feedback

CY7C1381D, CY7C1381F

CY7C1383D, CY7C1383F

Document #: 38-05544 Rev. *F Page 4 of 29

Pin Configurations (continued)

2345671

VDDQ

NC/288M

NC/144M

DQPC

DQC

DQD

DQC

DQD

AA AA

ADSP VDDQ

DQC

VDDQ

DQC

VDDQ

DQD

VDDQ

VDD

CLK

VDD

VSS

NC/576M

NC/1G

TDOTCKTDITMS

NC/36MNC/72M

VDDQ

AAA

DQA

DQC

DQA

DQB

DQA

DQB

VDD

DQC

VDD

DQD

ADSC

CE1

ADV

VSS

VSS DQPA

MODE

DQPD

DQPB

BWB

BWC

NC VDD NC

BWA

BWE

BWD

2345671

VDDQ

NC/288M

NC/144M

NCDQB

DQB

AA AA

ADSP VDDQ

VDDQ

NC/72M

VDDQ

VDD

CLK

VDD

VSS

NC/576M

NC/1G

TDOTCKTDITMS

VDDQ

ANC/36MA

DQA

DQB

DQA

VDD

DQB

VDD

DQB

ADSC

CE1

ADV

VSS

VSS NC

MODE

DQPB

DQPA

BWB

NC VDD NC

BWA

BWE

CY7C1383F (1M x 18)

CY7C1381F (512K x 36)

119-Ball BGA Pinout

[+] Feedback

CY7C1381D, CY7C1381F

CY7C1383D, CY7C1383F

Document #: 38-05544 Rev. *F Page 5 of 29

Pin Configurations (continued)

165-Ball FBGA Pinout(3 Chip Enable)

CY7C1381D (512K x 36)

234 5671

TDO

NC/288M

NC/144M

DQPC

DQC

DQPD

DQD

CE1BWB CE3

BWCBWE

ACE2

DQC

DQD

MODE

DQC

DQD

NC/36M

NC/72M

VDDQ

BWDBWACLK GW

VSS VSS VSS VSS

VDDQ VSS

VDD VSS

VSS

VDDQ

VDD VSS

VDD VSS VSS

VDDQ VDD

VSS

VDD

VSS

VDD VSS VSS

VSS

VDD

VDD VSS

VDD VSS VSS

TCK

VSS

TDI

DQCVSS

DQC

VSS

DQD

VDDQ

VSS

TMS

891011

ADV AADSC NC

OE ADSP ANC/576M

VSS VDDQ NC/1G DQPB

VDDQ

VDD DQB

DQB

DQA

VDD VDDQ

VDD VDDQ DQB

VDD

DQA

VDD VDDQ DQA

VDDQ

VDD

VDD VDDQ

VDD VDDQ DQA

VDDQ

VSS

DQB

DQA

DQPA

DQA

VDDQ

CY7C1383D (1M x 18)

VSS

234 5671

TDO

NC/288M

NC/144M

DQPB

VSS

DQB

ACE

1NC CE3

BWBBWE

ACE2

DQB

MODE

DQB

NC/36M

NC/72M

VDDQ

NC BWACLK GW

VSS VSS VSS VSS

VDDQ VSS

VDD VSS

VSS

VDDQ

VDD VSS

VDD VSS VSS

VDDQ VDD

VSS

VDD

VSS

VDD VSS VSS

VSS

VDD

VDD VSS

VDD VSS VSS

TCKA0

VSS

TDI

DQBVSS

NC VSS

DQB

VSS

DQB

VDDQ

VSS

TMS

891011

ADV AADSC A

OE ADSP ANC/576M

VSS VDDQ NC/1G DQPA

VDDQ

VDD NC

DQA

VDD VDDQ

VDD VDDQ DQA

VDD

NCVDD VDDQ DQA

VDDQ

VDD

VDD VDDQ

VDD VDDQ NC

VDDQ

VSS

DQA

VDDQ

[+] Feedback

CY7C1381D, CY7C1381F

CY7C1383D, CY7C1383F

Document #: 38-05544 Rev. *F Page 6 of 29

Pin Definitions

Name IO Description

A0,A1, AInput-

Synchronous

Address inputs used to select one of the address locations. Sampled at the rising edge

of the CLK if ADSP or ADSC is active LOW, and CE1,CE2, and CE3 [2] are sampled active.

A[1:0] feed the 2-bit counter.

BWA, BWB

BWC, BWD

Input-

Synchronous

Byte write select inputs, active LOW. Qualified with BWE to conduct byte writes to the

SRAM. Sampled on the rising edge of CLK.

GW Input-

Synchronous

Global write enable input, active LOW. When asserted LOW on the rising edge of CLK, a

global write is conducted (all bytes are written, regardless of the values on BW[A:D] and BWE).

CLK Input-

Clock

Clock input. Used to capture all synchronous inputs to the device. Also used to increment

the burst counter when ADV is asserted LOW, during a burst operation.

CE1Input-

Synchronous

Chip enable 1 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction

with CE2and CE3 [2] to select or deselect the device. ADSP is ignored if CE1is HIGH. CE1

is sampled only when a new external address is loaded.

CE2Input-

Synchronous

Chip enable 2 input, active HIGH. Sampled on the rising edge of CLK. Used in conjunction

with CE1and CE3 [2] to select or deselect the device. CE2 is sampled only when a new

external address is loaded.

CE3 [2] Input-

Synchronous

Chip enable 3 input, active LOW. Sampled on the rising edge of CLK. Used in conjunction

with CE1and CE2to select or deselect the device. CE3is sampled only when a new external

address is loaded.

OE Input-

Asynchronous

Output enable, asynchronous input, active LOW. Controls the direction of the IO pins.

When LOW, the IO pins behave as outputs. When deasserted HIGH, IO pins are tri-stated,

and act as input data pins. OE is masked during the first clock of a read cycle when emerging

from a deselected state.

ADV Input-

Synchronous

Advance input signal. Sampled on the rising edge of CLK. When asserted, it automatically

increments the address in a burst cycle.

ADSP Input-

Synchronous

Address strobe from processor, sampled on the rising edge of CLK, active LOW.

When asserted LOW, addresses presented to the device are captured in the address

registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both

asserted, only ADSP is recognized. ASDP is ignored when CE1is deasserted HIGH.

ADSC Input-

Synchronous

Address strobe from controller, sampled on the rising edge of CLK, active LOW.

When asserted LOW, addresses presented to the device are captured in the address

registers. A[1:0] are also loaded into the burst counter. When ADSP and ADSC are both

asserted, only ADSP is recognized.

BWE Input-

Synchronous

Byte write enable input, active LOW. Sampled on the rising edge of CLK. This signal

must be asserted LOW to conduct a byte write.

ZZ Input-

Asynchronous

ZZ sleep input. This active HIGH input places the device in a non-time critical sleep

condition with data integrity preserved. For normal operation, this pin has to be LOW or left

floating. ZZ pin has an internal pull down.

DQsIO-

Synchronous

Bidirectional data IO lines. As inputs, they feed into an on-chip data register that is

triggered by the rising edge of CLK. As outputs, they deliver the data contained in the

memory location specified by the addresses presented during the previous clock rise of the

read cycle. The direction of the pins is controlled by OE. When OE is asserted LOW, the

pins behave as outputs. When HIGH, DQsand DQPXare placed in a tri-state condition.The

outputs are automatically tri-stated during the data portion of a write sequence, during the

first clock when emerging from a deselected state, and when the device is deselected,

regardless of the state of OE.

DQPXIO-

Synchronous

Bidirectional data parity IO lines. Functionally, these signals are identical to DQs.During

write sequences, DQPXis controlled by BWX correspondingly.

[+] Feedback

CY7C1381D, CY7C1381F

CY7C1383D, CY7C1383F

Document #: 38-05544 Rev. *F Page 7 of 29

Functional Overview

All synchronous inputs pass through input registers controlled

by the rising edge of the clock. Maximum access delay from

the clock rise (tCDV) is 6.5 ns (133 MHz device).

The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F

supports secondary cache in systems utilizing a linear or

interleaved burst sequence. The interleaved burst order

supports Pentium®and i486™ processors. The linear burst

sequence is suited for processors that utilize a linear burst

sequence. The burst order is user selectable, and is

determined by sampling the MODE input. Accesses can be

initiated with the processor address strobe (ADSP) or the

controller address strobe (ADSC). Address advancement

through the burst sequence is controlled by the ADV input. A

two-bit on-chip wraparound burst counter captures the first

address in a burst sequence and automatically increments the

address for the rest of the burst access.

Byte write operations are qualified with the byte write enable

(BWE) and byte write select (BWX) inputs. A global write

enable (GW) overrides all byte write inputs and writes data to

all four bytes. All writes are simplified with on-chip

synchronous self-timed write circuitry.

Three synchronous chip selects (CE1, CE2, CE3 [2]) and an

asynchronous output enable (OE) provide for easy bank

selection and output tri-state control. ADSP is ignored if CE1

is HIGH.

Single Read Accesses

A single read access is initiated when the following conditions

are satisfied at clock rise: (1) CE1, CE2, and CE3 [2] are all

asserted active, and (2) ADSP or ADSC is asserted LOW (if

the access is initiated by ADSC, the write inputs must be

deasserted during this first cycle). The address presented to

the address inputs is latched into the address register and the

burst counter and/or control logic, and later presented to the

memory core. If the OE input is asserted LOW, the requested

data will be available at the data outputs with a maximum to

tCDV after clock rise. ADSP is ignored if CE1is HIGH.

Single Write Accesses Initiated by ADSP

This access is initiated when the following conditions are

satisfied at clock rise: (1) CE1, CE2, CE3 [2] are all asserted

active, and (2) ADSP is asserted LOW. The addresses

presented are loaded into the address register and the burst

inputs (GW, BWE, and BWX) are ignored during this first clock

cycle. If the write inputs are asserted active (see Truth Table

for Read/Write [4, 9] on page 10 for appropriate states that

indicate a write) on the next clock rise, the appropriate data will

be latched and written into the device. Byte writes are allowed.

All IOs are tri-stated during a byte write. As this is a common

IO device, the asynchronous OE input signal must be

MODE Input-Static Selects burst order. When tied to GND selects linear burst sequence. When tied to VDD

or left floating selects interleaved burst sequence. This is a strap pin and must remain static

during device operation. Mode pin has an internal pull up.

VDD Power Supply Power supply inputs to the core of the device.

VDDQ IO Power Supply Power supply for the IO circuitry.

VSS Ground Ground for the core of the device.

VSSQ IO Ground Ground for the IO circuitry.

TDO JTAG serial output

Synchronous

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. If the

JTAG feature is not being utilized, this pin can be left unconnected. This pin is not available

on TQFP packages.

TDI JTAG serial input

Synchronous

Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature

is not being utilized, this pin can be left floating or connected to VDD through a pull up

resistor. This pin is not available on TQFP packages.

TMS JTAG serial input

Synchronous

Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG feature

is not being utilized, this pin can be disconnected or connected to VDD. This pin is not

available on TQFP packages.

TCK JTAG-

Clock

Clock input to the JTAG circuitry. If the JTAG feature is not being utilized, this pin must

be connected to VSS. This pin is not available on TQFP packages.

NC – No connects. Not internally connected to the die. 36M, 72M, 144M, 288M, 576M, and 1G

are address expansion pins and are not internally connected to the die.

VSS/DNU Ground/DNU This pin can be connected to ground or can be left floating.

Pin Definitions (continued)

Name IO Description

[+] Feedback

CY7C1381D, CY7C1381F

CY7C1383D, CY7C1383F

Document #: 38-05544 Rev. *F Page 8 of 29

deasserted and the IOs must be tri-stated prior to the presen-

tation of data to DQs. As a safety precaution, the data lines are

tri-stated once a write cycle is detected, regardless of the state

of OE.

Single Write Accesses Initiated by ADSC

This write access is initiated when the following conditions are

satisfied at clock rise: (1) CE1, CE2, and CE3 [2] are all

asserted active, (2) ADSC is asserted LOW, (3) ADSP is

deasserted HIGH, and (4) the write input signals (GW, BWE,

and BWX) indicate a write access. ADSC is ignored if ADSP is

active LOW.

The addresses presented are loaded into the address register

and the burst counter, the control logic, or both, and delivered

to the memory core The information presented to DQ[A:D] will

be written into the specified address location. Byte writes are

allowed. All IOs are tri-stated when a write is detected, even a

byte write. Since this is a common IO device, the

asynchronous OE input signal must be deasserted and the IOs

must be tri-stated prior to the presentation of data to DQs. As

a safety precaution, the data lines are tri-stated once a write

cycle is detected, regardless of the state of OE.

Burst Sequences

The CY7C1381D/CY7C1383D/CY7C1381F/CY7C1383F

provides an on-chip two-bit wraparound burst counter inside

the SRAM. The burst counter is fed by A[1:0], and can follow

either a linear or interleaved burst order. The burst order is

determined by the state of the MODE input. A LOW on MODE

will select a linear burst sequence. A HIGH on MODE will

select an interleaved burst order. Leaving MODE unconnected

will cause the device to default to a interleaved burst

sequence.

Sleep Mode

The ZZ input pin is an asynchronous input. Asserting ZZ

places the SRAM in a power conservation sleep mode. Two

clock cycles are required to enter into or exit from this sleep

mode. While in this mode, data integrity is guaranteed.

Accesses pending when entering the sleep mode are not

considered valid nor is the completion of the operation

guaranteed. The device must be deselected prior to entering

the sleep mode. CE1, CE2, CE3 [2], ADSP, and ADSC must

remain inactive for the duration of tZZREC after the ZZ input

returns LOW.

Interleaved Burst Address Table

(MODE = Floating or VDD)

First

Address

A1: A0

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

00 01 10 11

01 00 11 10

10 11 00 01

11 10 01 00

Linear Burst Address Table (MODE = GND)

First

Address

A1: A0

Second

Address

A1: A0

Third

Address

A1: A0

Fourth

Address

A1: A0

00 01 10 11

01 10 11 00

10 11 00 01

11 00 01 10

ZZ Mode Electrical Characteristics

Parameter Description Test Conditions Min Max Unit

IDDZZ Sleep mode standby current ZZ > VDD – 0.2V 80 mA

tZZS Device operation to ZZ ZZ > VDD – 0.2V 2tCYC ns

tZZREC ZZ recovery time ZZ < 0.2V 2tCYC ns

tZZI ZZ active to sleep current This parameter is sampled 2tCYC ns

tRZZI ZZ inactive to exit sleep current This parameter is sampled 0 ns

[+] Feedback

CY7C1381D, CY7C1381F

CY7C1383D, CY7C1383F

Document #: 38-05544 Rev. *F Page 9 of 29

Truth Table [4, 5, 6, 7, 8]

Cycle Description

ADDRESS

Used CE1CE2CE3ZZ ADSP ADSC ADV WRITE OE CLK DQ

Deselected Cycle, Power

Down

None H X X L X L X X X L-H Tri-State

Deselected Cycle, Power

Down

None L L X L L X X X X L-H Tri-State

Deselected Cycle, Power

Down

None L X H L L X X X X L-H Tri-State

Deselected Cycle, Power

Down

None L L X L H L X X X L-H Tri-State

Deselected Cycle, Power

Down

None X X X L H L X X X L-H Tri-State

Sleep Mode, Power Down None X X X H X X X X X X Tri-State

Read Cycle, Begin Burst External L H L L L X X X L L-H Q

Read Cycle, Begin Burst External L H L L L X X X H L-H Tri-State

Write Cycle, Begin Burst External L H L L H L X L X L-H D

Read Cycle, Begin Burst External L H L L H L X H L L-H Q

Read Cycle, Begin Burst External L H L L H L X H H L-H Tri-State

Read Cycle, Continue Burst Next X X X L H H L H L L-H Q

Read Cycle, Continue Burst Next X X X L H H L H H L-H Tri-State

Read Cycle, Continue Burst Next H X X L X H L H L L-H Q

Read Cycle, Continue Burst Next H X X L X H L H H L-H Tri-State

Write Cycle, Continue Burst Next X X X L H H L L X L-H D

Write Cycle, Continue Burst Next H X X L X H L L X L-H D

Read Cycle, Suspend Burst Current X X X L H H H H L L-H Q

Read Cycle, Suspend Burst Current X X X L H H H H H L-H Tri-State

Read Cycle, Suspend Burst Current H X X L X H H H L L-H Q

Read Cycle, Suspend Burst Current H X X L X H H H H L-H Tri-State

Write Cycle, Suspend Burst Current X X X L H H H L X L-H D

Write Cycle, Suspend Burst Current H X X L X H H L X L-H D

Notes:

4. X=Don't Care, H = Logic HIGH, L = Logic LOW.

5. WRITE = L when any one or more byte write enable signals, and BWE = L or GW = L. WRITE = H when all byte write enable signals, BWE, GW = H.

6. The DQ pins are controlled by the current cycle and the OE signal. OE is asynchronous and is not sampled with the clock.

7. The SRAM always initiates a read cycle when ADSP is asserted, regardless of the state of GW, BWE, or BWX. Writes may occur only on subsequent clocks after

the ADSP or with the assertion of ADSC. As a result, OE must be driven HIGH prior to the start of the write cycle to allow the outputs to tri-state. OE is a don't

care for the remainder of the write cycle.

8. OE is asynchronous and is not sampled with the clock rise. It is masked internally during write cycles. During a read cycle all data bits are tri-state when OE is

inactive or when the device is deselected, and all data bits behave as output when OE is active (LOW).

[+] Feedback

CY7C1381D, CY7C1381F

CY7C1383D, CY7C1383F

Document #: 38-05544 Rev. *F Page 10 of 29

Truth Table for Read/Write [4, 9]

Function (CY7C1381D/CY7C1381F) GW BWE BWDBWCBWBBWA

Read HHXXXX

Read HLHHHH

Write Byte A (DQA, DQPA) HLHHHL

Write Byte B(DQB, DQPB)HLHHLH

Write Bytes A, B (DQA, DQB, DQPA, DQPB)H L H H L L

Write Byte C (DQC, DQPC) HLHLHH

Write Bytes C, A (DQC, DQA, DQPC, DQPA)HLHLHL

Write Bytes C, B (DQC, DQB, DQPC, DQPB)H L H L L H

Write Bytes C, B, A (DQC, DQB, DQA, DQPC,

DQPB, DQPA)

HLHLLL

Write Byte D (DQD, DQPD)HLLHHH

Write Bytes D, A (DQD, DQA, DQPD, DQPA)H L L H H L

Write Bytes D, B (DQD, DQA, DQPD, DQPA)H L L H L H

Write Bytes D, B, A (DQD, DQB, DQA, DQPD,

DQPB, DQPA)

HLLHLL

Write Bytes D, B (DQD, DQB, DQPD, DQPB)HLLLHH

Write Bytes D, B, A (DQD, DQC, DQA, DQPD,

DQPC, DQPA)

HLLLHL

Truth Table for Read/Write [4, 9]

Function (CY7C1383D/CY7C1383F) GW BWE BWBBWA

Write Bytes D, C, A (DQD, DQB, DQA, DQPD,

DQPB, DQPA)

HLLL

Write All Bytes H L L L

Write All Bytes L X X X

Read H H X X

Read H L H H

Write Byte A – (DQAand DQPA)HLHL

Write Byte B – (DQBand DQPB)HLLH

Write All Bytes H L L L

Write All Bytes L X X X

Note:

9. Table only lists a partial listing of the byte write combinations. Any combination of BWX is valid. Appropriate write will be done based on which byte write is active.

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Este manual sirve para los siguientes modelos

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