CMOSTEK NextGenRF CMT2189B Manual de usuario

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Overview

The CMT2189B is a low power, high performance, Flash-based, OOK RF transmitter chip embedded with the RISK MCU , which

covers a wireless communication band of 240 - 960 MHz. The product is a part of the CMOSTEK NextGenRFTM product family

which covers a complete product line consisting of transmitters, receivers, transceiver, etc.

The product models covered in this document are shown in the table below.

Table 1. Product Models Covered in This Document

Product

Model

Frequency

Range

Modulation

Method

Tx Power

Tx Current

Configuration

Package

CMT2189B

240 - 960MHz

OOK

+13 dBm

17.5 mA

Embedded

MCU

SOP14

Notes:

The test condition for the Tx power and Tx current is: 433.92 MHz, CW mode (always in the Tx carrier mode), Tx mode of Duty 50%

and Tx current of 8.5 mA.

AN201

CMT2189B User Guide

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Table of Contents

1Chip Architecture.............................................................................................................................. 5

1.1 Overall Operating Principle ................................................................................................................................ 5

1.2 IO Pin Description ..............................................................................................................................................5

2RF Part Configuration and Control Mechanism............................................................................ 8

2.1 Operating Mode..................................................................................................................................................8

2.2 Simple Operating Mode...................................................................................................................................... 8

2.3 Advanced Configuration Mode...........................................................................................................................9

2.4 SPI Interface Timing......................................................................................................................................... 10

2.5 RF Configuration Parameter ............................................................................................................................ 11

2.6 Configuration Register...................................................................................................................................... 14

2.7 Packet Related Register................................................................................................................................... 15

2.7.1 Tx Rate ....................................................................................................................................................16

2.7.2 Hardware Packet Format.........................................................................................................................17

2.7.3 Preamble .................................................................................................................................................18

2.7.4 Head/Sync...............................................................................................................................................18

2.7.5 Addr/ID.....................................................................................................................................................19

2.7.6 Key Value.................................................................................................................................................21

2.7.7 LBD Status Configuration ........................................................................................................................22

2.7.8 Stop Bit Configuration..............................................................................................................................24

2.7.9 Pause/Interval Configuration....................................................................................................................25

2.7.10 Tcycle Configuration.................................................................................................................................25

2.8 State and Function Register............................................................................................................................. 27

2.8.1 Soft Reset................................................................................................................................................27

2.8.2 Operating State and State Switching.......................................................................................................27

2.8.3 Operating State Query.............................................................................................................................28

2.9 Hardware Packet Tx Mode............................................................................................................................... 29

2.9.1 Power-up Initialization..............................................................................................................................29

2.9.2 Tx Process...............................................................................................................................................29

2.10 Pass-through Tx Mode (Advanced Configuration Mode).................................................................................. 31

2.10.1 Power-up initialization..............................................................................................................................31

2.10.2 Tx Process...............................................................................................................................................31

2.10.3 Related Register......................................................................................................................................31

3Program Memory ............................................................................................................................ 33

4Special Function Register(SFR).................................................................................................... 34

4.1 Address Mapping ............................................................................................................................................. 34

4.1.1 Bank0 SFR ..............................................................................................................................................34

4.1.2 BANK1 SFR.............................................................................................................................................35

4.1.3 TMR0 (Addr:0x01) ...................................................................................................................................36

4.1.4 STATUS (Addr:0x03)................................................................................................................................36

4.1.5 PORTA (Addr:0x05) .................................................................................................................................38

4.1.6 PORTC（Addr:0x07）.............................................................................................................................38

4.1.7 INTCON (Addr:0x0B)...............................................................................................................................39

4.1.8 PIR1 (Addr:0x0C).....................................................................................................................................40

4.1.9 TMR2 (Addr:0x11)....................................................................................................................................41

4.1.10 T2CON (Addr:0x12).................................................................................................................................41

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4.1.11 WDTCON (Addr:0x18).............................................................................................................................42

4.1.12 CMCON0 (Addr:0x19)..............................................................................................................................42

4.1.13 PR0 (Addr:0x1A)......................................................................................................................................43

4.1.14 MSCKCON (Addr:0x1B) ..........................................................................................................................44

4.1.15 SOSCPR (Addr:0x1C/0x1D)....................................................................................................................44

4.1.16 OPTION (Addr:0x81) ...............................................................................................................................45

4.1.17 TRISA (Addr:0x85)...................................................................................................................................46

Table 4-32. TRISA Bit Function Description ...................................................................................... 46

4.1.18 TRISC (Addr:0x87) ..................................................................................................................................46

4.1.19 PIE1（Addr:0x8C）.................................................................................................................................47

4.1.20 PCON（Addr:0x8E）...............................................................................................................................48

4.1.21 OSCCON (Addr:0x8F).............................................................................................................................48

4.1.22 PR2 (Addr:0x92)......................................................................................................................................49

4.1.23 WPUA (Addr:0x95)...................................................................................................................................50

4.1.24 IOCA (Addr:0x96).....................................................................................................................................50

4.1.25 VRCON (Addr:0x99)................................................................................................................................50

4.1.26 EEDAT（Addr:0x9A）.............................................................................................................................51

4.1.27 EEADR（Addr:0x9B）.............................................................................................................................51

4.1.28 EECON1（Addr:0x9C）..........................................................................................................................51

4.1.29 EECON2 (Addr:0x9D)..............................................................................................................................52

4.1.30 Configuration Register UCFGx ................................................................................................................52

4.1.31 PCL and PCLATH....................................................................................................................................54

4.1.32 INDF and FSR Register...........................................................................................................................55

5System Clock Source..................................................................................................................... 56

5.1 Clock Source Mode.......................................................................................................................................... 56

5.2 External Clock Mode........................................................................................................................................ 57

5.2.1 EC Mode..................................................................................................................................................57

5.2.2 LP and XT Modes ....................................................................................................................................57

5.3 Internal Clock Mode ......................................................................................................................................... 57

5.3.1 Frequency Selection Bit (IRCF) ...............................................................................................................57

5.3.2 Clock Switching Timing of HFINTOSC and LFINTOSC ...........................................................................58

5.4 Clock Switching................................................................................................................................................ 58

5.4.1 System Clock Selection bit (SCS)............................................................................................................59

5.4.2 Oscillator Start-up Timeout State (OSTS) Bit...........................................................................................59

5.5 Two-Speed Clock Start-up Mode ..................................................................................................................... 59

5.5.1 Two-Speed Start-up Mode Configuration.................................................................................................59

5.5.2 Two-Speed Start-up Sequence................................................................................................................60

5.6 Fail-Safe Clock Monitor.................................................................................................................................... 60

5.6.1 Fail-Safe Detection ..................................................................................................................................60

5.6.2 Fail-Safe Operation..................................................................................................................................61

5.6.3 Fail-Safe Condition Clearing....................................................................................................................61

5.6.4 Reset or Wake-up from Sleep..................................................................................................................61

6Reset Timing.................................................................................................................................... 62

6.1 Power-on Reset (POR) .................................................................................................................................... 63

6.2 MCLR External Reset (MCLR)......................................................................................................................... 63

6.3 Power-up Timer (PWRT).................................................................................................................................. 63

6.4 Brown-out Reset / Low Voltage Reset.............................................................................................................. 63

6.5 Error Instruction Reset ..................................................................................................................................... 64

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6.6 Timeout Action ................................................................................................................................................. 64

7BOOT................................................................................................................................................ 67

8Watchdog Timer.............................................................................................................................. 68

9Timer 0.............................................................................................................................................. 69

9.1 Timer0 Introduction .......................................................................................................................................... 69

9.2 Timer Mode of Timer 0..................................................................................................................................... 69

9.3 Counter Mode of Timer 0 ................................................................................................................................. 70

9.3.1 Prescaler Circuit Configurable by Software .............................................................................................70

9.3.2 Timer 0 Interrupt ......................................................................................................................................71

9.3.3 Timer 0 Driven by External Clock.............................................................................................................71

10 Timer 2.............................................................................................................................................. 72

11 Comparator...................................................................................................................................... 74

12 Data EEPROM.................................................................................................................................. 75

13 Clock Measurement........................................................................................................................ 76

14 Interrupt Mode................................................................................................................................. 78

14.1 INT Interrupt..................................................................................................................................................... 78

14.2 PORTA Level Change Interrupt........................................................................................................................ 79

14.3 Interrupt Response........................................................................................................................................... 79

14.4 Context Saving During Interrupts ..................................................................................................................... 81

15 MCU Sleep Mode for Energy Saving............................................................................................. 81

15.1 Wakeup Mode.................................................................................................................................................. 81

15.2 Watchdog Wake-up.......................................................................................................................................... 81

16 I/O Port ............................................................................................................................................. 82

16.1 PORTA Port and TRISA Register..................................................................................................................... 82

16.2 Other Functions of the Port.............................................................................................................................. 82

16.2.1 Weak Pull-Up...........................................................................................................................................82

16.2.2 Sate Change Interrupt..............................................................................................................................82

16.3 Port Description................................................................................................................................................ 83

16.3.1 PORTA<2:0>............................................................................................................................................83

16.3.2 PORTA3/PA3 ...........................................................................................................................................84

16.3.3 PORTA4/PA4 ...........................................................................................................................................85

16.3.4 PORTA5/PA5 ...........................................................................................................................................86

16.3.5 PORTA7/PA7 ...........................................................................................................................................86

16.3.6 PORTC<7:0>...........................................................................................................................................87

17 Instruction Set................................................................................................................................. 88

18 Revise History................................................................................................................................. 90

19 Contacts........................................................................................................................................... 91

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1 Chip Architecture

1.1 Overall Operating Principle

The CMT2189B is a RF transmitting chip integrated with digital and analog parts altogether, which applies a crystal oscillator to

provide the reference frequency and digital clock for PLL, supporting OOK modulation with a data rate range of 1 ~ 40 kbps. It

supports status control through the MCU programming to fulfill various low power transmission applications.

LDOs

PFD/CP

N-DIV

Interface and Digital Logic

Loop Filter

Modulator Ramp

Control

VCO

XOSC

AVDD

GND

XTAL

RFCTRL

RFO

POR LFOSC

EEPROM

Bandgap VTR

CPU

Program ROM

2K * 14Bit

Data EEPROM

256 * 8Bit

TMR/WDT

CMP

RSTC/OST/

PWRT/BOOT CLKC

SFR

EXTCK

IRCCK

SRAM

128 * 8Bit

CFG

DVDD

PA0 PA1 PA2 PA3 PA4 PC4 PC6PA7

DIN

3-SPI

PC0

PC[3:1]

Figure 1. CMT2189B System Architecture

The chip adopts the PLL+PA architecture to achieve the Sub-GHz wireless transmission function with supports of FIFO packet

mode and pass-through mode (in the FIFO packet mode, the embedded encoder allows users to select appropriate encoding

formats). After the processed data is sent to the modulator (for the pass-through mode, data is not processed by the encoder but

sent to the modulator directly after deburring), the modulator controls PLL and PA to have OOK modulation on the data and

transmit the data after then.

By controlling the RF part through the 3-wire SPI interface, the MCU can control various status switching, mode selection and low

power control.

1.2 IO Pin Description

DVDD

PC6

PC4/C2OUT

XTAL

RFCTRL

AVDD

GND

PA2/T0CKI/INT/C1OUT

RFO

PA3

PA7/OSC1/CLKI

PA1/C1IN-/ICSPDAT

PA0/C1IN+/ICSPCLK

PA4

Figure 2. CMT2189B Pin Top View

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Table 2. CMT2189B Pin Description - SOP14 Package

Pin #

Pin Name

Type

I/O

Description

DVDD

Digital

Chip power supply +

PC6

Digital

General purpose IO

PC4/C2OUT

Digital

PC4

General purpose IO

C2OUT

Comparator 2 output

XTAL

Analog

Crystal oscillator input in RF part

RFCTRL

Digital

SPI interface enabling control in RF part, low active, internal pull up.

AVDD

Analog

RF part power supply +

GND

Digital

Chip power supply ground

RF0

Analog

RF part PA output

PA4

Digital

General purpose IO with support of IOC and configurable pull-up

PA3

Digital

General purpose IO with support of IOC and configurable pull-up

PA2/T0CKI/INT/C1OUT

Digital

PA2

General purpose IO with support of IOC and

configurable pull-up

T0CKI

Timer 0 clock source input (Max=4MHz)

INT

External interrupt input

C1OUT

Comparator 1 output

PA0/C1IN+/ICSPCLK

Digital

PA0

General purpose IO with support of IOC and

configurable pull-up

C1IN+

Comparator 1 input +

ICSPCLK

Serial port clock signal for debug/programming

mode

PA1/C1IN-/ICSPDAT

Digital

PA1

General purpose IO with support of IOC and

configurable pull-up

C1IN-

Comparator 1 input -

ICSPDAT

Serial port data signal for debug/programming

mode

PA7/OSC1/CLKI

Digital

PA7

General purpose IO with support of IOC and

configurable pull-up

OSC1

MCU crystal pin

CLKI

External clock input pin

Internal

PC0/C2IN+/RFDIN

Digital

PC0

General purpose IO

C2IN+

Comparator 2 input +

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Pin #

Pin Name

Type

I/O

Description

RFDIN

RF data input pin for pass-through mode

Internal

PC1/C2IN-/SDIO

Digital

PC1

General purpose IO, connecting RF part and chip

internally

C2IN-

Comparator 1 output -

SDIO

3-wire SPI serial bus data SDIO in RF part, which

is a bidirectional port without pull-up or pull-down

resistors.

Internal

PC2/SCLK

Digital

PC2

General purpose IO, connecting RF part and chip

internally

SCLK

3-wire SPI serial bus clock SCLK in RF part

Internal

PC3/CSB

Digital

PC3

General purpose IO, connecting RF part and chip

internally

CSB

3-wire SPI serial bus chip selection CSB in RF

part with internal pull-up resistor

Notes:

1. The MCU has 2 built-in comparators, but the 2 internal comparators cannot be used due to the pin packaging limitation and

the multiplexing of RF part for some pins. However the MCU still needs to have necessary comparator settings after

initialization to avoid impact on other functions.

2. The clock source system of the MCU supports both internal oscillations and external oscillations. The external oscillation

supports dual-end crystal and single-end clock source input. However, due to the package pin limitation, the PA6 has no

package pin, therefore it does not support the external oscillation mode per dual-end crystal, namely only the external

oscillation mode per single-end clock source is supported.

3. PC<3:0> is the internal control pin of the chip, which has no package pin, but it is used as a bus controlling RF part

internally.

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2 RF Part Configuration and Control

Mechanism

2.1 Operating Mode

The built-in OOK Tx function of the CMT2189B supports 2 operating modes.

Simple operating mode: the default entry mode upon power-up, namely, the non-configuration mode, which supports the

pass-through Tx mode only.

Advanced configuration mode: it supports register configuration and operating state control through the SPI bus, which

supports both the FIFO and pass-through Tx mode.

Notes:

1. The pass-through Tx input sources in the 2 operating modes are different. Please see more details in below Sections.

2.2 Simple Operating Mode

In the simple operating mode, the only peripheral required is a crystal oscillator. Upon power-up, the chip controls data

transmission through the internal PC1 (SDIO) to fulfill data transmission at the corresponding frequency. In this mode, the

frequency multiplier factor is fixed to 16.5, calculated based on the following formula.

314 MHz ≤ FRF ≤ 480 MHz,

where FXTAL is the crystal frequency and FRF is the target frequency, and the frequency range is 314 MHz ~ 480MHz.

TOFF

PC1/SDIO

STATE

PA _ OUT

SLEEP

CALS

PLL

SLEEP

PA _ OUT

Figure 3. Tx Timing Diagram in the Simple operating Mode

Notes:

1. This mode supports a rate range of 1 ~ 20 kbps.

2. The maximum power output is fixed to +13 dBm. Users can reduce the Tx power by connecting a resistor to limit current

before the chock inductor if it is needed.

3. The internal SPI bus does not need to send any control commands and only needs to hold PC<3:0> in a high resistance

input status (except PC1).

4. The RFCTRL pin can be suspended in this mode.

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5. In this mode, the data transmitting pin is PC1 (SDIO), which is set to 0 in the low power state (the normal state). When data

transmitting is needed, it triggers on the rising edge to enter data transmitting state. After transmitting, PC1 is set to 0 and

lasts for more than 20 ms (TOFF time), and RF exits from the Tx mode automatically to enter the low power state.

6. For this mode, in low power state, PC1/SDIO is set 0 to output and PC2/SCLK, PC3/CSB, and PC0/RFDIN are set to high

resistance input.

2.3 Advanced Configuration Mode

To achieve higher performance and more functions such as the target operating frequency of 868MHz and chip automatic packet

transmitting in transmission process, users need to use the advanced configuration mode with supports of the following features.

Support more frequency multiplication factors to cover a frequency range of 240 ~ 960 MHz.

By filling the FIFO and transmitting the message automatically (repeatedly, multiple times and periodically), it can

release the MCU to do more work (In the pass-through mode, this process will take up MCU resource).

Support more accurate Tx rates with the accuracy determined by crystal, which is excellent in accuracy (in the

pass-through mode, the speed is controlled by the MCU software, and the accuracy depends on the software and the

internal RC).

Support voltage detection function inside RF, which offers simple power supply voltage detection and analysis

judgment processing.

Dynamical Tx power adjustment according to the power supply voltage to save power and prolong battery life.

In this mode, the chip internal MCU can have the RF mode control by operating registers through the 3-wire SPI (PC3/CSB,

PC2/SCLK, PC1/SDIO) to fulfill the 2 Tx modes.

1. Hardware packet Tx mode, which fills FIFO through SPI (see Section 2.9 for details)

The contents that need to be transmitted are filled into specified registers, which are automatically transmitted according to the

speed, coding mode, number of packets and packet interval, etc.(the data package format and other relevant information are

detailed in Section 2.7).

2. Pass-through Tx mode using PC0/RFDIN as data pin (see Section 2.10 for details)

That is, the 1-Pin Tx mode, the data stream is generated by the MCU and output through the specified pin to fulfill the most

elementary operating mode, namely data pin in, antenna out.

Notes:

1. The 2 Tx modes mentioned above are all in the advanced configuration mode, namely configuring and operating the chip

through SPI.

2. In the advanced configuration mode, it is required to control RFCTRL through other pins, therefore the RFCTRL pin cannot

be suspended.

3. The pass-through mode in the advanced configuration mode is similar to the pass-through mode in simple operating mode,

namely they both control data transmitting through a data pin, however the data input sources are different. In simple

operating mode, the Tx input pin is PC1/SDIO, while in the advanced configuration mode, it is changed to PC0/RFDIN

because PC1/SDIO is used as the serial data line of SPI. With both using the register configuring method, the pass-through

mode in advanced configuration mode can support more frequency selection and power selection than that in the simple

operating mode.

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2.4 SPI Interface Timing

The RF function inside the chip is controlled by a 3-wire SPI, and the corresponding relationship between SPI interface and the

IO of the MCU is as follows.

Table 3. Relationship between SPI Bus and Control Port

3-wire SPI

MCU Control Port

Function

CSB

PC3

Bus chip selection enabling, low active, built-in pull-up.

SCLK

PC2

Bus clock line, triggering on the rising edge

SDIO

PC1

Bi-directional bus data

Notes

1. SDIO, a bi-directional port, is used for data input and output. Both the address and data part are transmitted starting from

MSB.

2. When the RF part is accessed, RFCTRLis pulled down[*] to enable SPI serial port function, then the chip selection enabling

(PC3/CSB) is pulled down and a R/W bit is sent followed by a 7-bit register address. After the chip selection enabling

(PC3/CSB) is pulled down, it is necessary to wait for at least half a PC2 (SCLK) cycle to start sending R/W bit. After sending

the falling edge of the last PC2 (SCLK), the chip must wait for at least half a SCLK cycle, and then pull the PC3 (CSB) high.

3. In the SPI read operation as shown in the below figure, please pay special consideration on PC1/SDIO, since SDIO is a

bi-directional port, which will switch from the input state to the output state on the falling edge of the 8th clock (the dotted line

in the middle of the figure below), and SDIO needs to switch from the output state to the input state before the falling edge

of the 8th clock.

X 01234567 X

01234567

r/w =1

>0.5 SCLK cycle >0.5 SCLK cycle

PC3/CSB

PC2/SCLK

1PC /SDIO

RFCTRL

Figure 4. SPI Read Register Timing

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