Caen V793 Documento técnico
Technical
Information
Manual
MOD. V 793
16 January 2001
Revision n. 0
ICARUS
SLOW CONTROL
MODULE
NPO:
00100/98:V793x.MUTx/00
Document type: Title: Revision date: Revision:
User's Manual (MUT) Mod. V793, ICARUS Slow Control Module 16/01/01 0
NPO: Filename: Number of
pages: Page:
00100/98:V793x.MUTx/00 V793_REV0.DOC 19 2
TABLE OF CONTENTS
1. GENERAL DESCRIPTION............................................................................................................................................4
1.1. OVERVIEW.................................................................................................................................................................4
1.2. BLOCK DIAGRAM.....................................................................................................................................................5
1.3. FUNCTIONAL DESCRIPTION...................................................................................................................................6
1.3.1. Baseline generation.......................................................................................................................................6
1.3.2. EN_BRD signals generation........................................................................................................................6
1.3.3. Clock signal generation...............................................................................................................................6
1.3.4. Detector and crate power supply voltages measurement.......................................................................6
1.3.5. Test pulses distribution.................................................................................................................................7
2. TECHNICAL SPECIFICATIONS .................................................................................................................................8
2.1. PACKAGING...............................................................................................................................................................8
2.2. POWER REQUIREMENTS.........................................................................................................................................8
2.3. FRONT PANEL..........................................................................................................................................................9
2.4. EXTERNAL CONNECTIONS...................................................................................................................................10
2.4.1. Backplane connectors................................................................................................................................10
2.4.2. Front panel connectors..............................................................................................................................12
2.5. DISPLAYS AND SWITCHES....................................................................................................................................12
2.6. JUMPERS..................................................................................................................................................................13
3. RS232 INTERFACE.....................................................................................................................................................15
4. CAENET INTERFACE..................................................................................................................................................17
4.1. THE V793 CAENET CONTROLLER......................................................................................................................17
Document type: Title: Revision date: Revision:
User's Manual (MUT) Mod. V793, ICARUS Slow Control Module 16/01/01 0
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LIST OF FIGURES
FIG. 1.1 - BLOCK DIAGRAM OF THE MODEL V793...............................................................................................................5
FIG. 2.1 - MODEL V793 FRONT PANEL..................................................................................................................................9
FIG. 2.2 - PIN CONFIGURATION OF MODEL V793 BACKPLANE CONNECTORS..............................................................11
FIG. 2.3 - JUMPERS LOCATION...............................................................................................................................................13
FIG. 2.4 – RS232 PORT CONFIGURATION.............................................................................................................................14
FIG. 3.1 – DACS VALUES AND LINES STATUS WITH RS232..............................................................................................15
FIG. 3.2 – V793 SETTING MENU WITH RS232....................................................................................................................16
FIG. 4.1 – V793 CAENET CONTROLLER USER INTERFACE ..............................................................................................18
LIST OF TABLES
TABLE 2.1 - POWER REQUIREMENTS.....................................................................................................................................8
TABLE 3.1 – RS232 PORT SETTINGS....................................................................................................................................15
Document type: Title: Revision date: Revision:
User's Manual (MUT) Mod. V793, ICARUS Slow Control Module 16/01/01 0
NPO: Filename: Number of
pages: Page:
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1. General description
1.1. Overview
The CAEN Model V793 board has been designed for the slow control, via either RS232 or
CAENET communication path, of the analog crates into the ICARUS experiment
acquisition chain. Each ICARUS analog crate can be equipped with a Mod. V793 and up to
19 Mod. V791 boards. The Mod. V793 main functions are:
•Generate the EN_BRD logic signals to enable/disable the Mod. V791 boards
•Set the acquisition baseline for the V791 boards
•Generate a clock signal to synchronise all the Mod. V791 boards in a crate
•Measure detector and crate power supply voltages
•Forward test pulses to the V791 boards, to the decoupling boards (Mod. A764) or to the
detector during functional tests
Fig. 1.1shows a detailed block diagram of the V793 module.
The Mod. V793 is housed in a 1-unit wide, 6 unit high Eurocard mechanics; please note
that, although the module fits in a VME-like crate, the rear connectors are not VME
standard connectors.
Document type: Title: Revision date: Revision:
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1.2. Block diagram
to V791
to A764
ADC MUX
CON_HV[1..4]
4
GND
+5V D
+5V A
-5V A
DAC 1
DAC 2 DAC2
EN_BRD[1..19]
19
OUT
REG
TEST_PULSE-
TEST_PULSE+
T_PULSE-
T_PULSE+
CAENET
CONTROLLER
CAENET Line
DRV_1
CLOCK+
CLOCK-
RS232
DRV_2
DRV_3
DRV_4
CLOCK
LVDS
CLK
I/O
MICROPROCESSOR
to A764
to V791
PULSE IN
+
-
+
-
CALIB_ODD
CALIB_EVEN
ENABLE_ODD
ENABLE_EVEN
TEST_C
DAC1
Fig. 1.1- Block diagram of the Model V793
Document type: Title: Revision date: Revision:
User's Manual (MUT) Mod. V793, ICARUS Slow Control Module 16/01/01 0
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1.3. Functional description
1.3.1. Baseline generation
The Mod. V793 generates two DC voltage levels (DAC1 and DAC2) which allows to set the
baseline acquisition for the V791 boards; the DC levels can be remotely programmed with
12 bit resolution on the 0÷+2.5 V range either via RS232 or CAENET interface. For each
V791 board, it is possible to select the baseline (DAC1 or DAC2) according to the type of
signal to be converted by acting on a backplane jumper.
1.3.2. EN_BRD signals generation
The Mod. V793 is able to generate the EN_BOARD[1…19] TTL signals which allow to
enable/disable each of the V791 boards within an analog crate. If the EN_BOARD[n] signal
is active, the n-th V791 board is forced into reset state and signal digitisation is stopped.
The EN_BOARD signals can be remotely programmed either via RS232 or CAENET
interface.
1.3.3. Clock signal generation
The Mod. V793 houses a 40 MHz quartz oscillator producing an LVDS differential clock
signal CLOCK+/CLOCK-; this signal is employed to synchronise data acquisition on all the
V791 modules in a crate. The clock signal can be also externally supplied via the front
panel CLK I/O connector. The internal/external clock selection is performed through the
JP8 jumpers (see § 2.6 for further details)
1.3.4. Detector and crate power supply voltages measurement
The Mod. V793 houses eight 8-bit ADCs dedicated to detector and crate power supply
voltages measurement on the relevant backplane lines (see table below). The ADCs can be
read out either via RS232 or CAENET interface.
Line Range Line Range
CON_HV1 ±2.5 V GND ±0.5 V
CON_HV2 ±2.5 V +5 V 5±1 V
CON_HV3 ±2.5 V +5 V ANALOG 5±1 V
CON_HV4 ±2.5 V -5 V ANALOG -5±1 V
Document type: Title: Revision date: Revision:
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pages: Page:
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1.3.5. Test pulses distribution
During functional tests, a differential test pulse (±2.5 V range) can be injected into the V793
through the front panel PULSE IN connector (see block diagram at page 5); the pulse is
splitted and then forwarded to the V791 modules or to the decoupling boards depending on
the status of the CALIB_EVEN, CALIB_ODD, ENABLE_EVEN, ENABLE_ODD lines (TTL
levels) as explained in the table below. The lines status is remotely programmable by
RS232 or CAENET interface; four front panel LED (CE, CO, EE and EO) display the lines
status. At module power-on test pulsing is disabled on all channels.
SIGNAL ENABLE
CALIB_EVEN =1 Test-pulse through T_PULSE lines (to V791 even channels)
CALIB_ODD =1 Test-pulse through T_PULSE lines (to V791 odd channels)
ENABLE_EVEN =1 Test-pulse through TEST_PULSE lines (on A764 even
channels)
ENABLE_ODD =1 Test-pulse through TEST_PULSE lines (on A764 odd
channels)
Besides this, four remotely programmable lines (DRV_1…DRV_4]) are available to send
test pulses directly to the detector. The status of these lines is indicated by four front panel
LEDs (DRV1…4).
Document type: Title: Revision date: Revision:
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pages: Page:
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2. Technical Specifications
2.1. Packaging
The board is housed in a 1-unit wide, 6-unit high Eurocard standard mechanics.
The front panel of the Model V791 is shown in Fig. 2.1.
2.2. Power Requirements
The power requirements of the board are:
Table 2.1- Power requirements
Power Supply Absorption (max)
+5 V digital 300 mA
+5 V analog 150 mA
-5 V analog 150 mA
The crate must have a low-noise linear power supply with separate analog and digital
supply sections. It is suggested the use of a π-filter regulator for the analog section.
Document type: Title: Revision date: Revision:
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pages: Page:
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2.3. Front panel
SERIAL
IN/OUT
STATION
NUMBER
CLK I/0
RS 232
PULSE
IN
1
2
3
4
CE
CO
EE
EO
DRV
Mod. V793
ICARUS
SLOW
CONTROL
MODULE
0
0
Fig. 2.1- Model V793 front panel
Document type: Title: Revision date: Revision:
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2.4. External connections
2.4.1. Backplane connectors
The backplane connection pin configurations of the V793 module are shown in Fig. 2.2,
while their function and electro-mechanical specifications are listed in the following
sections.
BACKPLANE CONNECTOR P3
Mechanical specifications:
96-pin, C-type, A/B/C lines, DIN41612 standard connector;
Electrical specifications:
•EN_BRD1... EN_BRD19: enable signals for the V791 boards, TTL level;
•ENABLE_EVEN,
ENABLE_ODD test pulse enable signals for even (odd) A764
channels,
TTL level;
•CALIB_EVEN,
CALIB_ODD test pulse enable signals for even (odd) V791
channels, TTL level;
•CLOCK+, CLOCK-differential clock signal, LVDS level;
•TEST_PULSE+,
TEST_PULSE-differential test pulse to A764
•T_PULSE+,
T_PULSE-differential test pulse to V791
•AGND analog ground;
•DGND digital ground;
•+5V D +5V for the digital section;
•+5V A +5V for the analog section;
•-5V A -5V for the analog section;
•CON_HV1…CON_HV4 monitor lines for detector HV power supply,
±2.5 V range;
•TEST_C TEST_C signal, TTL level
•DAC1, DAC2 programmable baseline for the V791 boards
BACKPLANE CONNECTOR P1
Mechanical specifications:
32×2-pin, C-type, A/C lines, DIN41612 standard connector;
Electrical specifications:
•AGND: analog ground;;
•DRV_1…DRV_4: detector test pulses;
Tabla de contenidos
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