Atmel AT91 Series Manual de usuario

Features

•Incorporates the ARM7TDMI®ARM®Thumb®Processor

– High-performance 32-bit RISC Architecture

– High-density 16-bit Instruction Set

– Leader in MIPS/Watt

– Embedded ICE In-circuit Emulation, Debug Communication Channel Support

•Internal High-speed Flash

– 256 Kbytes (AT91SAM7XC256) Organized in 1024 Pages of 256 Bytes

– 128 Kbytes (AT91SAM7XC128) Organized in 512 Pages of 256 Bytes

– Single Cycle Access at Up to 30 MHz in Worst Case Conditions

– Prefetch Buffer Optimizing Thumb Instruction Execution at Maximum Speed

– Page Programming Time: 6 ms, Including Page Auto-erase,

Full Erase Time: 15 ms

– 10,000 Write Cycles, 10-year Data Retention Capability,

Sector Lock Capabilities, Flash Security Bit

– Fast Flash Programming Interface for High Volume Production

•Internal High-speed SRAM, Single-cycle Access at Maximum Speed

– 64 Kbytes (AT91SAM7XC256)

– 32 Kbytes (AT91SAM7XC128)

•Memory Controller (MC)

– Embedded Flash Controller, Abort Status and Misalignment Detection

•Reset Controller (RSTC)

– Based on Power-on Reset Cells and Low-power Factory-calibrated Brownout

Detector

– Provides External Reset Signal Shaping and Reset Source Status

•Clock Generator (CKGR)

– Low-power RC Oscillator, 3 to 20 MHz On-chip Oscillator and one PLL

•Power Management Controller (PMC)

– Power Optimization Capabilities, Including Slow Clock Mode (Down to 500 Hz) and

Idle Mode

– Four Programmable External Clock Signals

•Advanced Interrupt Controller (AIC)

– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources

– Two External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt

Protected

•Debug Unit (DBGU)

– 2-wire UART and Support for Debug Communication Channel interrupt,

Programmable ICE Access Prevention

•Periodic Interval Timer (PIT)

– 20-bit Programmable Counter plus 12-bit Interval Counter

•Windowed Watchdog (WDT)

– 12-bit key-protected Programmable Counter

– Provides Reset or Interrupt Signals to the System

– Counter May Be Stopped While the Processor is in Debug State or in Idle Mode

•Real-time Timer (RTT)

– 32-bit Free-running Counter with Alarm

– Runs Off the Internal RC Oscillator

•Two Parallel Input/Output Controllers (PIO)

– Sixty-two Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os

– Input Change Interrupt Capability on Each I/O Line

– Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output

AT91 ARM®

Thumb®-based

Microcontrollers

AT91SAM7XC256

AT91SAM7XC128

Summary

Preliminary

6209AS–ATARM–20-Oct-05

Note: This is a summary document. A complete document

is available on our Web site at www.atmel.com.

6209AS–ATARM–20-Oct-05

AT91SAM7XC256/128 Preliminary

•Seventeen Peripheral DMA Controller (PDC) Channels

•One Advanced Encryption System (AES)

– 128-bit Key Algorithm, Compliant with FIPS PUB 197 Specifications

– Buffer Encryption/Decryption Capabilities with PDC

•One Triple Data Encryption System (TDES)

– Two-key or Three-key Algorithms, Compliant with FIPS PUB 46-3 Specifications

– Optimized for Triple Data Encryption Capability

•One USB 2.0 Full Speed (12 Mbits per second) Device Port

– On-chip Transceiver, 1352-byte Configurable Integrated FIFOs

•One Ethernet MAC 10/100 base-T

– Media Independent Interface (MII) or Reduced Media Independent Interface (RMII)

– Integrated 28-byte FIFOs and Dedicated DMA Channels for Transmit and Receive

•One Part 2.0A and Part 2.0B Compliant CAN Controller

– Eight Fully-programmable Message Object Mailboxes, 16-bit Time Stamp Counter

•One Synchronous Serial Controller (SSC)

– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter

– I²S Analog Interface Support, Time Division Multiplex Support

– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer

•Two Universal Synchronous/Asynchronous Receiver Transmitters (USART)

– Individual Baud Rate Generator, IrDA Infrared Modulation/Demodulation

– Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support

– Full Modem Line Support on USART1

•Two Master/Slave Serial Peripheral Interfaces (SPI)

– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects

•One Three-channel 16-bit Timer/Counter (TC)

– Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel

– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability

•One Four-channel 16-bit Power Width Modulation Controller (PWMC)

•One Two-wire Interface (TWI)

– Master Mode Support Only, All Two-wire Atmel EEPROMs Supported

•One 8-channel 10-bit Analog-to-Digital Converter, Four Channels Multiplexed with Digital I/Os

•SAM-BA™Boot Assistance

– Default Boot program

– Interface with SAM-BA Graphic User Interface

•IEEE 1149.1 JTAG Boundary Scan on All Digital Pins

•5V-tolerant I/Os, Including Four High-current Drive I/O lines, Up to 16 mA Each

•Power Supplies

– Embedded 1.8V Regulator, Drawing up to 100 mA for the Core and External Components

– 3.3V VDDIO I/O Lines Power Supply, Independent 3.3V VDDFLASH Flash Power Supply

– 1.8V VDDCORE Core Power Supply with Brownout Detector

•Fully Static Operation: Up to 55 MHz at 1.65V and 85°C Worst Case Conditions

•Available in a 100-lead LQFP Green Package

6209AS–ATARM–20-Oct-05

AT91SAM7XC256/128 Preliminary

1. Description

Atmel's AT91SAM7XC256/128 is a member of a series of highly integrated Flash microcontrol-

lers based on the 32-bit ARM RISC processor. It features 256/128 Kbyte high-speed Flash and

64/32 Kbyte SRAM, a large set of peripherals, including an 802.3 Ethernet MAC, a CAN control-

ler, an AES 128 Encryption accelerator and a Triple Data Encryption System. A complete set of

system functions minimizes the number of external components.

The embedded Flash memory can be programmed in-system via the JTAG-ICE interface or via

a parallel interface on a production programmer prior to mounting. Built-in lock bits and a secu-

rity bit protect the firmware from accidental overwrite and preserve its confidentiality.

The AT91SAM7XC256/128 system controller includes a reset controller capable of managing

the power-on sequence of the microcontroller and the complete system. Correct device opera-

tion can be monitored by a built-in brownout detector and a watchdog running off an integrated

RC oscillator.

By combining the ARM7TDMI processor with on-chip Flash and SRAM, and a wide range of

peripheral functions, including USART, SPI, CAN Controller, Ethernet MAC, AES 128 accelera-

tor, TDES, Timer Counter, RTT and Analog-to-Digital Converters on a monolithic chip, the

AT91SAM7XC256/128 is a powerful device that provides a flexible, cost-effective solution to

many embedded control applications requiring secure communication over, for example, Ether-

net, CAN wired and Zigbee wireless networks.

2. Configuration Summary of the AT91SAM7XC256 and AT91SAM7XC128

The AT91SAM7XC256 and AT91SAM7XC128 differ only in memory sizes. Table 2-1 summa-

rizes the configurations of the two devices.

Table 2-1. Configuration Summary

Device Flash SRAM

AT91SAM7XC256 256K bytes 64K bytes

AT91SAM7XC128 128K bytes 32K bytes

6209AS–ATARM–20-Oct-05

AT91SAM7XC256/128 Preliminary

3. AT91SAM7XC256/128 Block Diagram

Figure 3-1. AT91SAM7XC256/128 Block Diagram

TDI

TDO

TMS

TCK

NRST

FIQ

IRQ0-IRQ1

PCK0-PCK3

PMC

Peripheral Bridge

Peripheral DMA

Controller

AIC

PLL

RCOSC

SRAM

64/32 Kbytes

ARM7TDMI

Processor

ICE

JTAG

SCAN

JTAGSEL

PIOA

USART0

SSC

Timer Counter

RXD0

TXD0

SCK0

RTS0

CTS0

SPI0_NPCS0

SPI0_NPCS1

SPI0_NPCS2

SPI0_NPCS3

SPI0_MISO

SPI0_MOSI

SPI0_SPCK

Flash

256/128 Kbytes

Reset

Controller

DRXD

DTXD

TCLK0

TCLK1

TCLK2

TIOA0

TIOB0

TIOA1

TIOB1

TIOA2

TIOB2

Memory Controller

Abort

Status

Address

Decoder

Misalignment

Detection

PIO

APB

POR

Embedded

Flash

Controller

AD0

AD1

AD2

AD3

ADTRG

PLLRC

17 Channels

PDC

USART1

RXD1

TXD1

SCK1

RTS1

CTS1

DCD1

DSR1

DTR1

RI1

PDC

SPI0

PDC

ADC

ADVREF

PDC

TC0

TC1

TC2

TWD

TWCK

TWI

OSC

XIN

XOUT

VDDIN

PWMC

PWM0

PWM1

PWM2

PWM3

1.8 V

Voltage

Regulator

USB Device

FIFO DDM

DDP

Transceiver

GND

VDDOUT

BOD

VDDCORE

VDDFLASH

AD4

AD5

AD6

AD7

VDDFLASH

Fast Flash

Programming

Interface

ERASE

PIO

PGMD0-PGMD15

PGMNCMD

PGMEN0-PGMEN1

PGMRDY

PGMNVALID

PGMNOE

PGMCK

PGMM0-PGMM3

VDDIO

TST

DBGU PDC

PDC

PIT

WDT

RTT

System Controller

VDDCORE

CAN CANRX

CANTX

PIO

Ethernet MAC 10/100

ETXCK-ERXCK-EREFCK

ETXEN-ETXER

ECRS-ECOL, ECRSDV

ERXER-ERXDV

ERX0-ERX3

ETX0-ETX3

EMDC

EMDIO

DMA

FIFO

PIOB

SPI1_NPCS0

SPI1_NPCS1

SPI1_NPCS2

SPI1_NPCS3

SPI1_MISO

SPI1_MOSI

SPI1_SPCK

PDC

SPI1

AES 128

PDC

EF100

SAM-BA

TDES

PDC

ROM

VDDFLASH

6209AS–ATARM–20-Oct-05

AT91SAM7XC256/128 Preliminary

4. Signal Description

Table 4-1. Signal Description List

Signal Name Function Type

Active

Level Comments

Power

VDDIN Voltage Regulator and ADC Power

Supply Input Power 3V to 3.6V

VDDOUT Voltage Regulator Output Power 1.85V

VDDFLASH Flash and USB Power Supply Power 3V to 3.6V

VDDIO I/O Lines Power Supply Power 3V to 3.6V

VDDCORE Core Power Supply Power 1.65V to 1.95V

VDDPLL PLL Power 1.65V to 1.95V

GND Ground Ground

Clocks, Oscillators and PLLs

XIN Main Oscillator Input Input

XOUT Main Oscillator Output Output

PLLRC PLL Filter Input

PCK0 - PCK3 Programmable Clock Output Output

ICE and JTAG

TCK Test Clock Input No pull-up resistor

TDI Test Data In Input No pull-up resistor.

TDO Test Data Out Output

TMS Test Mode Select Input No pull-up resistor.

JTAGSEL JTAG Selection Input Pull-down resistor.

Flash Memory

ERASE Flash and NVM Configuration Bits Erase

Command Input High Pull-down resistor

Reset/Test

NRST Microcontroller Reset I/O Low Pull-Up resistor, Open Drain

Output

TST Test Mode Select Input High Pull-down resistor

Debug Unit

DRXD Debug Receive Data Input

DTXD Debug Transmit Data Output

AIC

IRQ0 - IRQ1 External Interrupt Inputs Input

FIQ Fast Interrupt Input Input

PIO

PA0 - PA30 Parallel IO Controller A I/O Pulled-up input at reset

PB0 - PB30 Parallel IO Controller B I/O Pulled-up input at reset

6209AS–ATARM–20-Oct-05

AT91SAM7XC256/128 Preliminary

USB Device Port

DDM USB Device Port Data - Analog

DDP USB Device Port Data + Analog

USART

SCK0 - SCK1 Serial Clock I/O

TXD0 - TXD1 Transmit Data I/O

RXD0 - RXD1 Receive Data Input

RTS0 - RTS1 Request To Send Output

CTS0 - CTS1 Clear To Send Input

DCD1 Data Carrier Detect Input

DTR1 Data Terminal Ready Output

DSR1 Data Set Ready Input

RI1 Ring Indicator Input

Synchronous Serial Controller

TD Transmit Data Output

RD Receive Data Input

TK Transmit Clock I/O

RK Receive Clock I/O

TF Transmit Frame Sync I/O

RF Receive Frame Sync I/O

Timer/Counter

TCLK0 - TCLK2 External Clock Inputs Input

TIOA0 - TIOA2 I/O Line A I/O

TIOB0 - TIOB2 I/O Line B I/O

PWM Controller

PWM0 - PWM3 PWM Channels Output

Serial Peripheral Interface - SPIx

SPIx_MISO Master In Slave Out I/O

SPIx_MOSI Master Out Slave In I/O

SPIx_SPCK SPI Serial Clock I/O

SPIx_NPCS0 SPI Peripheral Chip Select 0 I/O Low

SPIx_NPCS1-NPCS3 SPI Peripheral Chip Select 1 to 3 Output Low

Two-wire Interface

TWD Two-wire Serial Data I/O

TWCK Two-wire Serial Clock I/O

Table 4-1. Signal Description List (Continued)

Signal Name Function Type

Active

Level Comments

6209AS–ATARM–20-Oct-05

AT91SAM7XC256/128 Preliminary

Analog-to-Digital Converter

AD0-AD3 Analog Inputs Analog Digital pulled-up inputs at reset

AD4-AD7 Analog Inputs Analog Analog Inputs

ADTRG ADC Trigger Input

ADVREF ADC Reference Analog

Fast Flash Programming Interface

PGMEN0-PGMEN1 Programming Enabling Input

PGMM0-PGMM3 Programming Mode Input

PGMD0-PGMD15 Programming Data I/O

PGMRDY Programming Ready Output High

PGMNVALID Data Direction Output Low

PGMNOE Programming Read Input Low

PGMCK Programming Clock Input

PGMNCMD Programming Command Input Low

CAN Controller

CANRX CAN Input Input

CANTX CAN Output Output

Ethernet MAC 10/100

EREFCK Reference Clock Input RMII only

ETXCK Transmit Clock Input MII only

ERXCK Receive Clock Input MII only

ETXEN Transmit Enable Output

ETX0 - ETX3 Transmit Data Output ETX0 - ETX1 only in RMII

ETXER Transmit Coding Error Output MII only

ERXDV Receive Data Valid Input MII only

ECRSDV Carrier Sense and Data Valid Input RMII only

ERX0 - ERX3 Receive Data Input ERX0 - ERX1 only in RMII

ERXER Receive Error Input

ECRS Carrier Sense Input MII only

ECOL Collision Detected Input MII only

EMDC Management Data Clock Output

EMDIO Management Data Input/Output I/O

EF100 Force 100 Mbits/sec. Output High RMII only

Table 4-1. Signal Description List (Continued)

Signal Name Function Type

Active

Level Comments

6209AS–ATARM–20-Oct-05

AT91SAM7XC256/128 Preliminary

5. Package

The AT91SAM7XC256/128 is available in 100-lead LQFP package.

5.1 100-lead LQFP Mechanical Overview

Figure 5-1 shows the orientation of the 100-lead LQFP package. A detailed mechanical descrip-

tion is given in the Mechanical Characteristics section of the full datasheet.

Figure 5-1. 100-lead LQFP Package Pinout (Top View)

5.2 AT91SAM7XC256/128 Pinout

100

Table 5-1. Pinout in 100-lead TQFP Package

1 ADVREF 26 PA18/PGMD6 51 TDI 76 TDO

2 GND 27 PB9 52 GND 77 JTAGSEL

3 AD4 28 PB8 53 PB16 78 TMS

4 AD5 29 PB14 54 PB4 79 TCK

5 AD6 30 PB13 55 PA23/PGMD11 80 PA30

6 AD7 31 PB6 56 PA24/PGMD12 81 PA0/PGMEN0

7 VDDOUT 32 GND 57 NRST 82 PA1/PGMEN1

8 VDDIN 33 VDDIO 58 TST 83 GND

9 PB27/AD0 34 PB5 59 PA25/PGMD13 84 VDDIO

10 PB28/AD1 35 PB15 60 PA26/PGMD14 85 PA3

11 PB29/AD2 36 PB17 61 VDDIO 86 PA2

12 PB30/AD3 37 VDDCORE 62 VDDCORE 87 VDDCORE

13 PA8/PGMM0 38 PB7 63 PB18 88 PA4/PGMNCMD

14 PA9/PGMM1 39 PB12 64 PB19 89 PA5/PGMRDY

15 VDDCORE 40 PB0 65 PB20 90 PA6/PGMNOE

16 GND 41 PB1 66 PB21 91 PA7/PGMNVALID

17 VDDIO 42 PB2 67 PB22 92 ERASE

18 PA10/PGMM2 43 PB3 68 GND 93 DDM

19 PA11/PGMM3 44 PB10 69 PB23 94 DDP

20 PA12/PGMD0 45 PB11 70 PB24 95 VDDFLASH

21 PA13/PGMD1 46 PA19/PGMD7 71 PB25 96 GND

22 PA14/PGMD2 47 PA20/PGMD8 72 PB26 97 XIN/PGMCK

23 PA15/PGMD3 48 VDDIO 73 PA27/PGMD15 98 XOUT

24 PA16/PGMD4 49 PA21/PGMD9 74 PA28 99 PLLRC

25 PA17/PGMD5 50 PA22/PGMD10 75 PA29 100 VDDPLL

6209AS–ATARM–20-Oct-05

AT91SAM7XC256/128 Preliminary

6. Power Considerations

6.1 Power Supplies

The AT91SAM7XC256/128 has six types of power supply pins and integrates a voltage regula-

tor, allowing the device to be supplied with only one voltage. The six power supply pin types are:

• VDDIN pin. It powers the voltage regulator and the ADC; voltage ranges from 3.0V to 3.6V,

3.3V nominal. In order to decrease current consumption, if the voltage regulator and the ADC

are not used, VDDIN, ADVREF, AD5, AD6 and AD7 should be connected to GND. In this

case, VDDOUT should be left unconnected.

• VDDOUT pin. It is the output of the 1.8V voltage regulator.

• VDDIO pin. It powers the I/O lines; voltage ranges from 3.0V to 3.6V, 3.3V nominal.

• VDDFLASH pin. It powers the USB transceivers and a part of the Flash and is required for

the Flash to operate correctly; voltage ranges from 3.0V to 3.6V, 3.3V nominal.

• VDDCORE pins. They power the logic of the device; voltage ranges from 1.65V to 1.95V,

1.8V typical. It can be connected to the VDDOUT pin with decoupling capacitor. VDDCORE

is required for the device, including its embedded Flash, to operate correctly.

• VDDPLL pin. It powers the oscillator and the PLL. It can be connected directly to the

VDDOUT pin.

No separate ground pins are provided for the different power supplies. Only GND pins are pro-

vided and should be connected as shortly as possible to the system ground plane.

6.2 Power Consumption

The AT91SAM7XC256/128 has a static current of less than 60 µA on VDDCORE at 25°C,

including the RC oscillator, the voltage regulator and the power-on reset when the brownout

detector is deactivated. Activating the brownout detector adds 28 µA static current.

The dynamic power consumption on VDDCORE is less than 90 mA at full speed when running

out of the Flash. Under the same conditions, the power consumption on VDDFLASH does not

exceed 10 mA.

6.3 Voltage Regulator

The AT91SAM7XC256/128 embeds a voltage regulator that is managed by the System

Controller.

In Normal Mode, the voltage regulator consumes less than 100 µA static current and draws 100

mA of output current.

The voltage regulator also has a Low-power Mode. In this mode, it consumes less than 25 µA

static current and draws 1 mA of output current.

Adequate output supply decoupling is mandatory for VDDOUT to reduce ripple and avoid oscil-

lations. The best way to achieve this is to use two capacitors in parallel: one external 470 pF (or

1 nF) NPO capacitor should be connected between VDDOUT and GND as close to the chip as

possible. One external 2.2 µF (or 3.3 µF) X7R capacitor should be connected between VDDOUT

and GND.

6209AS–ATARM–20-Oct-05

AT91SAM7XC256/128 Preliminary

Adequate input supply decoupling is mandatory for VDDIN in order to improve startup stability

and reduce source voltage drop. The input decoupling capacitor should be placed close to the

chip. For example, two capacitors can be used in parallel: 100 nF NPO and 4.7 µF X7R.

6.4 Typical Powering Schematics

The AT91SAM7XC256/128 supports a 3.3V single supply mode. The internal regulator input

connected to the 3.3V source and its output feeds VDDCORE and the VDDPLL. Figure 6-1

shows the power schematics to be used for USB bus-powered systems.

Figure 6-1. 3.3V System Single Power Supply Schematic

Power Source

ranges

from 4.5V (USB)

to 18V

3.3V

VDDIN

Voltage

Regulator

VDDOUT

VDDIO

DC/DC Converter

VDDCORE

VDDFLASH

VDDPLL

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