Atmel AT91SAM9 Instrucciones de instalación y funcionamiento

AT91SAM9 LCD Controller

1. Scope

This application note explains how to connect the Atmel®ARM®Thumb®-based

AT91SAM9 LCD Controller to an STN or TFT display. It includes display selection

guidelines, describes the hardware and software configurations and gives perfor-

mance results and software examples.

AT91 ARM

Thumb

Microcontrollers

Application Note

6300A–ATARM–09-Jul-07

Application Note

2. Display Overview

2.1 TFT and STN Technologies

The most commonly used display technologies are TFT (Thin Film Transistor) and STN (Super

Twisted Nematic).

STN displays use a passive matrix screen technology that has no active or controlling element

inside the display cell. Pixels are controlled by energizing the appropriate row and column drive

lines of the matrix from outside the display, resulting in a slow frame rate. STN screens have lim-

ited color range and viewing angle (~15 degrees max).

With TFT LCDs, each pixel is controlled by one to four transistors. Typically, one transistor is

used for each of the RGB color channels. Because of this direct control technique, TFT screens

are sometimes called Active-Matrix LCDs. TFT technology provides more accurate color control,

allowing it to display more colors. TFT screens also offer a wider viewing angle range (30 to 70

degrees) than the other popular types of LCDs.

2.2 Interface

The typical interface of a display is based on analog and digital inputs. The digital lines are a

data bus, a pixel clock, vertical and horizontal synchronization signals and a data enable line.

The voltage input is generally used for contrast control. The LCD Controller drives all these inter-

face lines. If more inputs are required by the display, it may be managed by PIOs (power control,

AC bias on some STN displays, backlight control, etc.)

2.3 Blanking

For the internal synchronization mechanism, the display may need some dummy data at the

beginning and/or end of a line, and at the beginning and/or end of a frame. This is called

blanking.

Display

Contrast Control

Horizontal Synchro

Vertical Synchro

Data bus

Data Enable

Pixel Clock

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Application Note

The dummy pixels/lines are not part of the frame buffer; they are managed by the LCD Control-

ler. Some delays must be introduced in vertical and horizontal timings to support it. These delays

are often described as vertical/horizontal front/back porch delays in the display datasheets.

2.4 Definitions

The following definitions and clarifications are necessary when using the LCD Controller.

• Bits per pixel (Bpp): Corresponds to the number of bits that describe the pixel color. (i.e., in

16 bits per pixel mode, each pixel can have 65536 different colors).

• Interface Width (IfWidth): Corresponds to the number of I/O data lines (data bus width) used

for the interface between the LCD controller and the display.

• Frame Rate: This parameter is given by the display datasheet (in Hz). This rate must be

respected to ensure the correct behavior of the display, thus avoiding bad image quality

(flickering).

Real image

Dummy pixel area

Horizontal Front Porch

Horizontal Back Porch

Vertical Front Porch

Vertical Back Porch

LCDVSYNC

LCDHSYNC

LCDDOTCK

Idle lines

Vertical Back Porch

Idle lines

Vertical Front Porch

Idle pixels

Horizontal Back Porch

Idle pixels

Horizontal Front Porch

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Application Note

3. Display Selection Guide

In order to verify the compatibility of a display with the AT91SAM9 LCD Controller, a list of items

to check is given below.

3.1 Technology Type

The LCD controller supports TFT RGB (up to 16M colors), color STN (up to 4096 colors) and

Monochrome STN (up to 16 gray shades) displays. Other technologies may also be used if their

interface is compatible.

3.2 Screen Size

The screen size is fully programmable. The maximum size supported is 2048 x 2048. Most of

standard display resolution levels are compatible: VGA (640x480), QVGA (320 x 240), etc.

In STN mode, single and double scan modes are supported. For a double scan mode, the maxi-

mum size for each panel is 1024 x 2048.

3.3 Hardware Interface

The interface must be 3.3V compliant.

All the display lines should be present in the lines description list. If the display features more

lines (i.e, gate command), the LCD Controller is not able to manage them. They could be man-

aged by the PIO Controller or other peripherals (PWM, TC, etc.).

The polarity is programmable on:

LCDDOTCK: dot clock signal

LCDDEN: data enable signal

LCDVSYNC: vertical synchro signal

LCDHSYNC: horizontal synchro signal

Refer to Section 6.1 for more details on data bus connection in TFT mode.

3.4 Timings

The display size (LxH) and the frame rate are given by the display specifications.

The LCD Controller clock (LCDDOTCK) verifies the following formula:

STN Mono:

STN Color:

TFT:

LCDDOTCKfreq FrameRate DisplaySize×

IfWidth

---------------------------------------------------------------------=

LCDDOTCKfreq FrameRate DisplaySize 3××

IfWidth

-------------------------------------------------------------------------------=

LCDDOTCKfreq FrameRate DisplaySize×=

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Application Note

According to the AT91SAM9 features, the maximum LCDDOTCK frequency is equal to the mas-

ter clock (in bypass mode).

The signal timings provided by the display specification must respect the timings supported by

the LCD Controller.

• Vertical pulse width from 1 to 64 lines.

• Horizontal pulse width from 1 to 64 dot clock cycles.

• Vertical Front Porch from 1 to 256 lines.

• Vertical Back Porch from 1 to 256 lines.

• Horizontal Front Porch from 1 to 2048 dot clock cycles.

• Horizontal Back Porch from 1 to 256 dot clock cycles.

Parameter Min Max Unit Symbol

Vertical Front Porch 1 256 Line T0

Vertical Back Porch 1 256 Line T1

Horizontal Front Porch 1 2048 LCDDOTCK cycle T2

Horizontal Back porch 1 256 LCDDOTCK cycle T3

Vertical Pulse Width 1 64 Line T4

Horizontal Pulse Width 1 64 LCDDOTCK cycles T5

LCDVSYNC

LCDHSYNC

LCDDOTCK

T5T2 T3T3

Horizontal BlankingActive Area

T4T0 T1T1

Vertical Blanking

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Application Note

4. TFT Display Selection Guide Example

4.1 Display Description

An example of a display specification (TX09D71VM1CCA on AT91SAM9261-EK):

• TFT QVGA

• RGB 262K colors

• VCC [3.0 to 3.6V]

• Frame rate: 60 Hz

• Vertical Pulse Width : typ = 1 (in lines)

• Vertical Back Porch (VBP) : typ = 4 (in lines)

• Vertical Front Porch (VFP) : typ = 2 (in lines)

• Horizontal Pulse Width : typ = 5 (in pixels)

• Horizontal Back Porch (HBP): typ = 17 (in pixels)

• Horizontal Front Porch (HFP): typ = 11 (in pixels)

Interface:

4.2 Compatibility

To determine whether the display in the example is compatible, the following points should be

evaluated:

4.2.1 Technology

It is a TFT display, thus the technology is supported.

4.2.2 Size

QVGA is 320 x 240, thus the size is acceptable.

4.2.3 Interface

VCC = 3.3V

Data bus 18 bits, 6 bits per color.

VSYNC corresponds to LCDVSYNC

HSYNC to LCDHSYNC

Display

Vctrl

HSYNC

VSYNC

R0 - R5

DTMG

DCLK

PCI

G0 - G5

B0 - B5

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Application Note

DCLK to LCDDOTCK

DTMG to LCDDEN

Add a passive filter between LCDCC and Vctrl.

Use a PIO for PCI control.

This interface is compatible.

4.2.4 Timings

Frame rate 60 Hz:

LCDDOTCKfreq = 60 x 320 x 240 = 4.608 MHz < LCDDOTCKfreq max.

The delays are all between 1 and 17. The LCD controller is able to manage delays between 1

and 256: all the blanking delays are in a compatible range.

The timings are compatible.

4.2.5 Conclusion

The display given in the example is compatible with the AT91SAM9261 LCD Controller.

5. STN Display Selection Guide Example

5.1 Display Description

An example of a display specification (SP06Q002):

• STN QVGA

• 16 gray shades

• VCC [3.0 to 3.6V]

• Frame rate: 75 Hz

• Horizontal Pulse Width : typ = 1 (in pixels)

• Horizontal Back Porch (HBP): typ = 1 (in pixels)

• Horizontal Front Porch (HFP): typ = 1 (in pixels)

Interface:

Display

Vled-/Vled+

CL1

FLM

CL2

DOFF

D0 - D3

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Application Note

5.2 Compatibility

To determine whether the display in the example is compatible, the following points should be

evaluated:

5.2.1 Technology

It is a STN display, thus the technology is supported.

5.2.2 Size

QVGA is 320 x 240, thus the size is acceptable.

5.2.3 Interface

VCC = 3.3V

Data bus 4 bits.

FLM corresponds to LCDVSYNC

CL1 to LCDHSYNC

CL2 to LCDDOTCK

Add a passive filter between LCDCC and Vled-/leld+

Use a PIO for DOFF control.

This interface is compatible.

5.2.4 Timings

Frame rate 75 Hz:

LCDDOTCKfreq = 75 x 320 x 240 / 4 = 1.44MHz < LCDDOTCKfreq max.

The delays are all equal to 1. The LCD controller is able to manage delays between 1 and 256:

all the blanking delays are in a compatible range. In STN mode, vertical timings should be set to

The timings are compatible.

5.2.5 Conclusion

The display given in the example is compatible with the AT91SAM9 LCD Controller.

6. Configuration

6.1 TFT Hardware Connection

The AT91SAM9 LCD Controller is based on Blue-Green-Red (BGR) standard while most graph-

ical layers use RGB color map.

As an example, the memory map of a pixel in 16-bit mode in the frame buffer is:

where:

I B4B3B2B1B0G4G3G2G1G0R4R3R2R1R0

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Application Note

– I is Intensity Bit

– R[4:0], G[4:0] and B[4:0] are respectively red, green and blue video components.

Most graphical layers use RGB 5-6-5:

This leads to a swap between blue and red components. There are two solutions to correct, via

software or via hardware.

6.1.1 Software Swap

The swap of blue and red components by software is CPU consuming.

This is done using a piece of code. An example of the code follows, in C for an inline function:

__inline unsigned int swap_it(swap){

unsigned int tmpR,tmpB;

tmpB = swap <<10;//extract Blue

tmpR = swap >>10;//extract Red

swap = swap & 0x83E0; //keep only Green and I Bit

return swap |= tmpB|tmpR;/returns the swapped color

}

In ASM, once compiled with armcc:

mov r0,r5

mov r3,r0,lsl #10

mov r2,r0,asr #10

ldr r1,0x000005fc ; = #0x000083e0

and r0,r0,r1

orr r1,r3,r2

orr r1,r1,r0

ARMulate gives 8 CPU cycles for this sequence.

It must be done for each pixel of the frame, i.e., 320*240 = 76,800 times for each frame. There-

fore, 76,800*8 = 614,400 CPU cycles per frame.

This means 614,400 * 25 = 15,360,000 CPU cycles per second for a 25 Hz refresh rate.

Compared to the 200,000,000 CPU cycles per second when running at 200 MHz, this gives

7.7% of the CPU time wasted to swap the LCD framebuffer.

For use the software solution, the LCD device is to be connected as follows to the PIOB lines.

6.1.1.1 18-bit TFT Display

In this mode, the LCD Controller can be programmed in 16-bit or 24-bit mode, as the LCD Con-

troller does not offer 18-bit mode.

In 16-bit mode, some framebuffer memory is saved. The number of colors available is 65,536.

R4 R3 R2 R1 R0 G5 G4 G3 G2 G1 G0 B4 B3 B2 B1 B0

6300A–ATARM–09-Jul-07

Application Note

In 24-bit mode, as only 18 bits are wired to the LCD device, the number of colors available is

262,144.

Figure 6-1. 18-bit TFT Display Hardware Connection (Software Swap) in 24-bit Mode

LCD Device

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