Atmel AVR ATmega324PA Manual de usuario

Features

•High-performance, Low-power AVR® 8-bit Microcontroller

•Advanced RISC Architecture

– 131 Powerful Instructions – Most Single-clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 20 MIPS Throughput at 20 MHz

– On-chip 2-cycle Multiplier

•High Endurance Non-volatile Memory segments

– 16/32/64/128K Bytes of In-System Self-programmable Flash program memory

(ATmega164PA/324PA/644PA/1284P)

– 512B/1K/2K/4K Bytes EEPROM (ATmega164PA/324PA/644PA/1284P)

– 1/2/4/16K Bytes Internal SRAM (ATmega164PA/324PA/644PA/1284P)

– Write/Erase Cycles: 10,000 Flash/ 100,000 EEPROM

– Data retention: 20 years at 85°C/ 100 years at 25°C(1)

– Optional Boot Code Section with Independent Lock Bits

In-System Programming by On-chip Boot Program

True Read-While-Write Operation

– Programming Lock for Software Security

•JTAG (IEEE std. 1149.1 Compliant) Interface

– Boundary-scan Capabilities According to the JTAG Standard

– Extensive On-chip Debug Support

– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface

•Peripheral Features

– Two 8-bit Timer/Counters with Separate Prescalers and Compare Modes

– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture Mode

– Real Time Counter with Separate Oscillator

– Six PWM Channels

– 8-channel, 10-bit ADC

Differential mode with selectable gain at 1x, 10x or 200x

– Byte-oriented Two-wire Serial Interface

– Two Programmable Serial USART

– Master/Slave SPI Serial Interface

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

– Interrupt and Wake-up on Pin Change

•Special Microcontroller Features

– Power-on Reset and Programmable Brown-out Detection

– Internal Calibrated RC Oscillator

– External and Internal Interrupt Sources

– Six Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, Standby and

Extended Standby

•I/O and Packages

– 32 Programmable I/O Lines

– 40-pin PDIP, 44-lead TQFP, 44-pad VQFN/QFN/MLF

– 44-pad DRQFN

– 49-ball VFBGA

•Operating Voltages

– 1.8 - 5.5V

•Speed Grades for ATmega164PA/324PA/644PA/1284P

– 0 - 20MHz @ 1.8 - 5.5V

•Power Consumption at 1 MHz, 1.8V, 25°C

– Active: 0.4 mA

– Power-down Mode: 0.1µA

– Power-save Mode: 0.6µA (Including 32 kHz RTC)

Note: 1. See ”Data Retention” on page 9 for details.

8-bit

Microcontroller

with

16/32/64/128K

Bytes In-System

Programmable

Flash

ATmega164PA

ATmega324PA

ATmega644PA

ATmega1284P

Summary

Rev. 8152GS–AVR–11/09

8152GS–AVR–11/09

ATmega164PA/324PA/644PA/1284P

1. Pin Configurations

1.1 Pinout - PDIP/TQFP/VQFN/QFN/MLF for ATmega164PA/324PA/644PA/1284P

Figure 1-1. Pinout

Note: The large center pad underneath the VQFN/QFN/MLF package should be soldered to ground on

the board to ensure good mechanical stability.

(PCINT8/XCK0/T0) PB0

(PCINT9/CLKO/T1) PB1

(PCINT10/INT2/AIN0) PB2

(PCINT11/OC0A/AIN1) PB3

(PCINT12/OC0B/SS) PB4

(PCINT13/MOSI) PB5

(PCINT14/MISO) PB6

(PCINT15/SCK) PB7

RESET

VCC

GND

XTAL2

XTAL1

(PCINT24/RXD0) PD0

(PCINT25/TXD0) PD1

(PCINT26/RXD1/INT0) PD2

(PCINT27/TXD1/INT1) PD3

(PCINT28/XCK1/OC1B) PD4

(PCINT29/OC1A) PD5

(PCINT30/OC2B/ICP) PD6

PA0 (ADC0/PCINT0)

PA1 (ADC1/PCINT1)

PA2 (ADC2/PCINT2)

PA3 (ADC3/PCINT3)

PA4 (ADC4/PCINT4)

PA5 (ADC5/PCINT5)

PA6 (ADC6/PCINT6)

PA7 (ADC7/PCINT7)

AREF

GND

AVCC

PC7 (TOSC2/PCINT23)

PC6 (TOSC1/PCINT22)

PC5 (TDI/PCINT21)

PC4 (TDO/PCINT20)

PC3 (TMS/PCINT19)

PC2 (TCK/PCINT18)

PC1 (SDA/PCINT17)

PC0 (SCL/PCINT16)

PD7 (OC2A/PCINT31)

PDIP

PA4 (ADC4/PCINT4)

PA5 (ADC5/PCINT5)

PA6 (ADC6/PCINT6)

PA7 (ADC7/PCINT7)

AREF

GND

AVCC

PC7 (TOSC2/PCINT23)

PC6 (TOSC1/PCINT22)

PC5 (TDI/PCINT21)

PC4 (TDO/PCINT20)

(PCINT13/MOSI) PB5

(PCINT14/MISO) PB6

(PCINT15/SCK) PB7

RESET

VCC

GND

XTAL2

XTAL1

(PCINT24/RXD0) PD0

(PCINT25/TXD0) PD1

(PCINT26/RXD1/INT0) PD2

(PCINT27/TXD1/INT1) PD3

(PCINT28/XCK1/OC1B) PD4

(PCINT29/OC1A) PD5

(PCINT30/OC2B/ICP) PD6

(PCINT31/OC2A) PD7

VCC

GND

(PCINT16/SCL) PC0

(PCINT17/SDA) PC1

(PCINT18/TCK) PC2

(PCINT19/TMS) PC3

PB4 (SS/OC0B/PCINT12)

PB3 (AIN1/OC0A/PCINT11)

PB2 (AIN0/INT2/PCINT10)

PB1 (T1/CLKO/PCINT9)

PB0 (XCK0/T0/PCINT8)

GND

VCC

PA0 (ADC0/PCINT0)

PA1 (ADC1/PCINT1)

PA2 (ADC2/PCINT2)

PA3 (ADC3/PCINT3)

TQFP/VQFN/QFN/MLF

8152GS–AVR–11/09

ATmega164PA/324PA/644PA/1284P

1.2 Pinout - DRQFN for ATmega164PA/324PA/644PA

Figure 1-2. DRQFN - Pinout

Table 1-1. DRQFN - Pinout

A1 PB5 A7 PD3 A13 PC4 A19 PA 3

B1 PB6 B6 PD4 B11 PC5 B16 PA 2

A2 PB7 A8 PD5 A14 PC6 A20 PA 1

B2 RESET B7 PD6 B12 PC7 B17 PA 0

A3 VCC A9 PD7 A15 AVCC A21 VCC

B3 GND B8 VCC B13 GND B18 GND

A4 XTAL2 A10 GND A16 AREF A22 PB0

B4 XTAL1 B9 PC0 B14 PA 7 B19 PB1

A5 PD0 A11 PC1 A17 PA 6 A23 PB2

B5 PD1 B10 PC2 B15 PA 5 B20 PB3

A6 PD2 A12 PC3 A18 PA 4 A24 PB4

Top view Bottom view

A18

B15

A17

B14

A16

B13

A15

B12

A14

B11

A13

A12

B10

A11

A10

A24

B20

A23

B19

A22

B18

A21

B17

A20

B16

A19

A18

B15

A17

B14

A16

B13

A15

B12

A14

B11

A13

A10

A11

B10

A12

A19

B16

A20

B17

A21

B18

A22

B19

A23

B20

A24

8152GS–AVR–11/09

ATmega164PA/324PA/644PA/1284P

1.3 Pinout - VFBGA for ATmega164PA/324PA/644PA

Figure 1-3. VFBGA - Pinout

Table 1-2. BGA - Pinout

1234567

AGND PB4 PB2 GND VCC PA2 GND

BPB6 PB5 PB3 PB0 PA0 PA3 PA5

CVCC RESET PB7 PB1 PA1 PA6 AREF

DGND XTAL2 PD0 GND PA4 PA7 GND

EXTAL1 PD1 PD5 PD7 PC5 PC7 AVCC

FPD2 PD3 PD6 PC0 PC2 PC4 PC6

GGND PD4 VCC GND PC1 PC3 GND

1234567

7654321

Top view Bottom view

8152GS–AVR–11/09

ATmega164PA/324PA/644PA/1284P

2. Overview

The ATmega164PA/324PA/644PA/1284P is a low-power CMOS 8-bit microcontroller based on

the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle,

the ATmega164PA/324PA/644PA/1284P achieves throughputs approaching 1 MIPS per MHz

allowing the system designer to optimize power consumption versus processing speed.

2.1 Block Diagram

Figure 2-1. Block Diagram

The AVR core combines a rich instruction set with 32 general purpose working registers. All the

32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

registers to be accessed in one single instruction executed in one clock cycle. The resulting

architecture is more code efficient while achieving throughputs up to ten times faster than con-

ventional CISC microcontrollers.

CPU

GND

VCC

RESET

Power

Supervision

POR / BOD &

RESET

Watchdog

Oscillator

Watchdog

Timer

Oscillator

Circuits /

Clock

Generation

XTAL1

XTAL2

PORT A (8)

PORT D (8)

PD7..0

PORT C (8)

PC5..0

TWI

SPI

EEPROM

JTAG/OCD 16bit T/C 1

8bit T/C 2

8bit T/C 0

SRAMFLASH

USART 0

Internal

Bandgap reference

Analog

Comparator

A/D

Converter

PA7..0

PORT B (8)

PB7..0

USART 1

TOSC1/PC6TOSC2/PC7

8152GS–AVR–11/09

ATmega164PA/324PA/644PA/1284P

The ATmega164PA/324PA/644PA/1284P provides the following features: 16/32/64/128K bytes

of In-System Programmable Flash with Read-While-Write capabilities, 512B/1K/2K/4K bytes

EEPROM, 1/2/4/16K bytes SRAM, 32 general purpose I/O lines, 32 general purpose working

registers, Real Time Counter (RTC), three flexible Timer/Counters with compare modes and

PWM, 2 USARTs, a byte oriented 2-wire Serial Interface, a 8-channel, 10-bit ADC with optional

differential input stage with programmable gain, programmable Watchdog Timer with Internal

Oscillator, an SPI serial port, IEEE std. 1149.1 compliant JTAG test interface, also used for

accessing the On-chip Debug system and programming and six software selectable power sav-

ing modes. The Idle mode stops the CPU while allowing the SRAM, Timer/Counters, SPI port,

and interrupt system to continue functioning. The Power-down mode saves the register contents

but freezes the Oscillator, disabling all other chip functions until the next interrupt or Hardware

Reset. In Power-save mode, the asynchronous timer continues to run, allowing the user to main-

tain a timer base while the rest of the device is sleeping. The ADC Noise Reduction mode stops

the CPU and all I/O modules except Asynchronous Timer and ADC, to minimize switching noise

during ADC conversions. In Standby mode, the Crystal/Resonator Oscillator is running while the

rest of the device is sleeping. This allows very fast start-up combined with low power consump-

tion. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue

to run.

The device is manufactured using Atmel’s high-density nonvolatile memory technology. The On-

chip ISP Flash allows the program memory to be reprogrammed in-system through an SPI serial

interface, by a conventional nonvolatile memory programmer, or by an On-chip Boot program

running on the AVR core. The boot program can use any interface to download the application

program in the application Flash memory. Software in the Boot Flash section will continue to run

while the Application Flash section is updated, providing true Read-While-Write operation. By

combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip,

the Atmel ATmega164PA/324PA/644PA/1284P is a powerful microcontroller that provides a

highly flexible and cost effective solution to many embedded control applications.

The ATmega164PA/324PA/644PA/1284P AVR is supported with a full suite of program and sys-

tem development tools including: C compilers, macro assemblers, program

debugger/simulators, in-circuit emulators, and evaluation kits.

2.2 Comparison Between ATmega164PA, ATmega324PA, ATmega644PA and ATmega1284P

Table 2-1. Differences between ATmega164PA, ATmega324PA and ATmega644PA and

ATmega1284P

Device Flash EEPROM RAM

ATmega164PA 16 Kbyte 512 Bytes 1 Kbyte

ATmega324PA 32 Kbyte 1 Kbyte 2 Kbyte

ATmega644PA 64 Kbyte 2 Kbyte 4 Kbyte

ATmega1284P 128 Kbyte 4 Kbyte 16 Kbyte

8152GS–AVR–11/09

ATmega164PA/324PA/644PA/1284P

2.3 Pin Descriptions

2.3.1 VCC

Digital supply voltage.

2.3.2 GND

Ground.

2.3.3 Port A (PA7:PA0)

Port A serves as analog inputs to the Analog-to-digital Converter.

Port A also serves as an 8-bit bi-directional I/O port with internal pull-up resistors (selected for

each bit). The Port A output buffers have symmetrical drive characteristics with both high sink

and source capability. As inputs, Port A pins that are externally pulled low will source current if

the pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes

active, even if the clock is not running.

Port A also serves the functions of various special features of the

ATmega164PA/324PA/644PA/1284P as listed on page 81.

2.3.4 Port B (PB7:PB0)

Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port B also serves the functions of various special features of the

ATmega164PA/324PA/644PA/1284P as listed on page 83.

2.3.5 Port C (PC7:PC0)

Port C is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port C output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port C pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port C pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port C also serves the functions of the JTAG interface, along with special features of the

ATmega164PA/324PA/644PA/1284P as listed on page 86.

2.3.6 Port D (PD7:PD0)

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port D output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port D pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port D pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port D also serves the functions of various special features of the

ATmega164PA/324PA/644PA/1284P as listed on page 88.

8152GS–AVR–11/09

ATmega164PA/324PA/644PA/1284P

2.3.7 RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a

reset, even if the clock is not running. The minimum pulse length is given in ”System and Reset

Characteristics” on page 330. Shorter pulses are not guaranteed to generate a reset.

2.3.8 XTAL1

Input to the inverting Oscillator amplifier and input to the internal clock operating circuit.

2.3.9 XTAL2

Output from the inverting Oscillator amplifier.

2.3.10 AVCC

AVCC is the supply voltage pin for Port A and the Analog-to-digital Converter. It should be exter-

nally connected to VCC, even if the ADC is not used. If the ADC is used, it should be connected

to VCC through a low-pass filter.

2.3.11 AREF

This is the analog reference pin for the Analog-to-digital Converter.

8152GS–AVR–11/09

ATmega164PA/324PA/644PA/1284P

3. Resources

A comprehensive set of development tools, application notes and datasheetsare available for

download on http://www.atmel.com/avr.

4. About Code Examples

This documentation contains simple code examples that briefly show how to use various parts of

the device. Be aware that not all C compiler vendors include bit definitions in the header files

and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-

tation for more details.

The code examples assume that the part specific header file is included before compilation. For

I/O registers located in extended I/O map, "IN", "OUT", "SBIS", "SBIC", "CBI", and "SBI" instruc-

tions must be replaced with instructions that allow access to extended I/O. Typically "LDS" and

"STS" combined with "SBRS", "SBRC", "SBR", and "CBR".

Note: 1.

5. Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less

than 1 PPM over 20 years at 85°C or 100 years at 25°C.

8152GS–AVR–11/09

ATmega164PA/324PA/644PA/1284P

6. Register Summary

Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page

(0xFF) Reserved - - - - - - -

(0xFE) Reserved - - - - - - - -

(0xFD) Reserved - - - - - - - -

(0xFC) Reserved - - - - - - - -

(0xFB) Reserved - - - - - - -

(0xFA) Reserved - - - - - - - -

(0xF9) Reserved - - - - - - -

(0xF8) Reserved - - - - - - - -

(0xF7) Reserved - - - - - - - -

(0xF6) Reserved - - - - - - - -

(0xF5) Reserved - - - - - - -

(0xF4) Reserved - - - - - - - -

(0xF3) Reserved - - - - - - - -

(0xF2) Reserved - - - - - - - -

(0xF1) Reserved - - - - - - -

(0xF0) Reserved - - - - - - - -

(0xEF) Reserved - - - - - - -

(0xEE) Reserved - - - - - - - -

(0xED) Reserved - - - - - - - -

(0xEC) Reserved - - - - - - - -

(0xEB) Reserved - - - - - - -

(0xEA) Reserved - - - - - - - -

(0xE9) Reserved - - - - - - - -

(0xE8) Reserved - - - - - - - -

(0xE7) Reserved - - - - - - -

(0xE6) Reserved - - - - - - - -

(0xE5) Reserved - - - - - - - -

(0xE4) Reserved - - - - - - - -

(0xE3) Reserved - - - - - - -

(0xE2) Reserved - - - - - - - -

(0xE1) Reserved - - - - - - -

(0xE0) Reserved - - - - - - -

(0xDF) Reserved - - - - - - - -

(0xDE) Reserved - - - - - - - -

(0xDD) Reserved - - - - - - - -

(0xDC) Reserved - - - - - - -

(0xDB) Reserved - - - - - - - -

(0xDA) Reserved - - - - - - - -

(0xD9) Reserved - - - - - - - -

(0xD8) Reserved - - - - - - - -

(0xD7) Reserved - - - - - - - -

(0xD6) Reserved - - - - - - - -

(0xD5) Reserved - - - - - - - -

(0xD4) Reserved - - - - - - - -

(0xD3) Reserved - - - - - - - -

(0xD2) Reserved - - - - - - - -

(0xD1) Reserved - - - - - - - -

(0xD0) Reserved - - - - - - - -

(0xCF) Reserved - - - - - - - -

(0xCE) UDR1 USART1 I/O Data Register 190

(0xCD) UBRR1H - - - - USART1 Baud Rate Register High Byte 194/207

(0xCC) UBRR1L USART1 Baud Rate Register Low Byte 194/207

(0xCB) Reserved - - - - - - - -

(0xCA) UCSR1C UMSEL11 UMSEL10 - - - UDORD1 UCPHA1 UCPOL1 192/206

(0xC9) UCSR1B RXCIE1 TXCIE1 UDRIE1 RXEN1 TXEN1 UCSZ12 RXB81 TXB81 191/205

(0xC8) UCSR1A RXC1 TXC1 UDRE1 FE1 DOR1 UPE1 U2X1 MPCM1 190/205

(0xC7) Reserved - - - - - - - -

(0xC6) UDR0 USART0 I/O Data Register 190

(0xC5) UBRR0H - - - - USART0 Baud Rate Register High Byte 194/207

(0xC4) UBRR0L USART0 Baud Rate Register Low Byte 194/207

(0xC3) Reserved - - - - - - - -

(0xC2) UCSR0C UMSEL01 UMSEL00 - - - UDORD0 UCPHA0 UCPOL0 192/206

(0xC1) UCSR0B RXCIE0 TXCIE0 UDRIE0 RXEN0 TXEN0 UCSZ02 RXB80 TXB80 191/205

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