Analog Devices ADuC7026 Suplemento

AN-744

APPLICATION NOTE

One Technology Way • P.O. Box 9106 • Norwood, MA 02062-9106, U.S.A. • Tel: 781.329.4700 • Fax: 781.461.3113 • www.analog.com

ADuC7026 Evaluation Board Reference Guide

MicroConverter® ADuC7026 Development System

by Aude Richard

Rev. A | Page 1 of 16

AN-744

Rev. A | Page 2 of 16

TABLE OF CONTENTS

Evaluation Board Overview ............................................................ 3

Considerations.............................................................................. 3

Evaluation Board Features............................................................... 4

Power Supply................................................................................. 4

RS-232 Interface ........................................................................... 4

Emulation Interface...................................................................... 4

Crystal Circuit............................................................................... 4

External Reference (ADR291) .................................................... 4

Reset/Download/IRQ0 Push Buttons........................................ 4

Power Indicator/General-Purpose LEDs .................................. 5

Analog I/O Connections ............................................................. 5

General-Purpose Prototype Area............................................... 5

External Memories and Latch Footprint................................... 5

DIP Switch Link Options................................................................. 6

S1-1 VREF ........................................................................................ 6

S1-2 VOCM....................................................................................... 6

S1-3 POT ....................................................................................... 6T

S1-4 ADC3 .....................................................................................6

S1-5 VIN− ......................................................................................6

S1-6 VIN+ ......................................................................................6

S1-7 ADC4 .....................................................................................6

S1-8 LED.........................................................................................6

External Connectors .........................................................................7

Analog I/O Connector J3.............................................................7

Power Supply Connector J5 .........................................................7

Emulation Connector J4...............................................................7

Serial Interface Connector J1.......................................................7

Digital I/O Connector J2..............................................................7

External Memory Interface ..............................................................9

Connections ...................................................................................9

Potentiometer Demonstration Circuit ........................................ 10

Schematic......................................................................................... 11

ADuC7026 Evaluation Board Parts List...................................... 13

AN-744

Rev. A | Page 3 of 16

EVALUATION BOARD OVERVIEW

The ADuC7026 evaluation board has the following features:

•2-layer PCB (4” × 5” form factor).

•9 V power supply regulated to 3.3 V on board.

•4-pin UART header to connect to RS-232 interface cable.

•20-pin standard JTAG connector.

•Demonstration circuit.

•32.768 kHz watch crystal to drive the PLL clock.

•ADR291 2.5 V external reference chip.

•Reset/download/IRQ0 push buttons.

•Power indicator/general-purpose LEDs.

•Access to all ADC inputs and DAC output from external

header. All device ports are brought out to external

header pins.

•Surface-mount and through-hole general-purpose

prototype area.

•External memories and latch footprint.

CONSIDERATIONS

•This document refers to the MicroConverter ADuC7026

evaluation board Revision B1.

•All references in this document to the physical orientation

of components on the board are made with respect to a

component-side view of the board with the prototype area

appearing in the bottom of the board.

•The board is laid out to minimize coupling between the

analog and digital sections of the board. To this end, the

ground plane is split with the analog section on the left

side and a digital plane on the right side of the board. The

regulated 3.3 V power supply is routed directly to the

digital section and is filtered before being routed into the

analog section of the board.

AN-744

Rev. A | Page 4 of 16

EVALUATION BOARD FEATURES

POWER SUPPLY

The user should connect the 9 V power supply via the 2.1 mm

input power socket (J5). The input connector is configured as a

center negative, that is, as GND on the center pin and +9 V on

the outer shield.

The 9 V supply is regulated via the Linear Voltage Regulator U5.

The 3.3 V regulator output is used to drive the digital side of the

board directly. The 3.3 V supply is also filtered and then used to

supply the analog side of the board.

When on, the LED (D3) indicates that a valid 3.3 V supply is

being driven from the regulator circuit. All active components

are decoupled with 0.1 μF at device supply pins to ground.

RS-232 INTERFACE

The ADuC7026 (U1) P1.1 and P1.0 lines are connected to the

RS-232 interface cable via Connector J1. The interface cable

generates the required level shifting to allow direct connection

to a PC serial port. Ensure that the cable supplied is connected

to the board correctly, that is, DVDD is connected to DVDD

and DGND is connected to DGND.

EMULATION INTERFACE

Nonintrusive emulation and download are possible on the

ADuC7026, via JTAG, by connecting a JTAG emulator to the

J4 connector.

CRYSTAL CIRCUIT

The board is fitted with a 32.768 kHz crystal, from which the

on-chip PLL circuit can generate a 41.78 MHz clock.

EXTERNAL REFERENCE (ADR291)

The external 2.5 V Reference Chip U2 has two functions. It is

provided on the evaluation board to demonstrate the external

reference option of the ADuC7026 but its main purpose is to

generate the VOCM voltage of the differential amplifier if

required.

RESET/DOWNLOAD/IRQ0 PUSH BUTTONS

A reset push button is provided to allow the user to reset the

part manually. When the button is pushed, the reset pin of the

ADuC7026 is pulled to DGND. Because the reset pin on the

ADuC7026 is Schmidt triggered internally, there is no need to

use an external Schmidt trigger on this pin.

When pushed, the IRQ0 push button switch drives P0.4/IRQ0

high. This can be used to initiate an external interrupt 0.

To enter serial download mode, the user must pull the P0.0/BM

pin low while reset is toggled. On the evaluation board, serial

download mode can easily be initiated by holding down the

serial download push button (S2) while inserting and releasing

the reset button (S3) as shown in Figure 1.

(RESET = 1)

(BM = 1)

(A) S3 AND S2 RELEASED

(BM = 0)

(RESET = 1)

(B) PUSH S2

(RESET = 1) S2

(BM = 0)

(D) RELEASE S3

(BM = 0)

(RESET = 0)

(BM = 1)

(RESET = 1)

(E) RELEASE S2

05032-001

Figure 1. Entering Serial Download Mode on the Evaluation Board

AN-744

Rev. A | Page 5 of 16

POWER INDICATOR/GENERAL-PURPOSE LEDS

A power LED (D3) is used to indicate that a sufficient supply is

available on the board. A general-purpose LED (D2) is directly

connected to P4.2 of the ADuC7026. When P4.2 is cleared, the

LED is turned on, and when P4.2 is set, the LED is turned off.

ANALOG I/O CONNECTIONS

All analog I/O connections are brought out on Header J3.

ADC0 and ADC1 are buffered using an AD8606 to evaluate

single-ended and pseudo differential mode. A potentiometer

can be connected to ADC0 (buffered).

ADC3 and ADC4 can be buffered with a single-ended to

differential op amp on-board, with the AD8132 used to evaluate

the ADC in fully differential mode.

ADC2 and ADC5 to ADC11 are not buffered. Be sure to follow

the data sheet recommendations when connecting signals to

these inputs.

DAC1 can be used to control the brightness of the LED D1,

when connected via the S1 switch.

GENERAL-PURPOSE PROTOTYPE AREA

General-purpose prototype areas are provided at the bottom of

the evaluation board for adding external components as

required in the user’s application. AVDD, AGND, VDDIO, and

DGND tracks are provided in the prototype area.

EXTERNAL MEMORIES AND LATCH FOOTPRINT

Footprints for a 32 k × 16 static RAM (CY7C1020CV33), a

64 k × 16 flash (AT29LV1024), and a16-bit latch are also

on-board. See the External Memory Interface section.

AN-744

Rev. A | Page 6 of 16

DIP SWITCH LINK OPTIONS

S1-1 VREF

Function

Connects the output of the 2.5 V external reference (ADR291)

to the VREF pin (Pin 68) of the ADuC7026.

Use

Slide S1-1 to the on position to connect the external reference

to the ADuC7026.

Slide S1-1 to the off position to use the internal 2.5 V reference

or a different external reference on the VREF pin of Header J3.

S1-2 VOCM

Function

Connects 1.67 V to the VOCM pin of the AD8132. No extra

dc voltage is required on the board to use the ADC in

differential mode.

Use

Slide S1-2 to the on position to connect VOCM of the differential

amplifier to the 1.67 V divided output of the ADR291 reference.

Slide S1-2 to the off position to use a different voltage for VOCM

by connecting a dc voltage to the VOCM pin of Header J3. Note

that the VOCM value is dependent on the reference value, as

shown in Table 1.

Table 1. VOCM Range

VREF VOCM minimum VOCM maximum

2.5 V 1.25 V 2.05 V

2.048 V 1.024 V 2.276 V

1.25 V 0.75 V 2.55 V

S1-3 POT

Function

Connects the potentiometer output to ADC0. This input is

buffered by an AD8606. This is for demonstration purposes.

Use

Slide S1-3 to the on position to connect the potentiometer to

the op amp of the ADC0 input channel.

Slide S1-3 to the off position to use the ADC0 input on Header J3.

S1-4 ADC3

Function

Brings out ADC3 (Pin 80) on Header J3.

Use

Slide S1-4 to the on position to connect ADC3 of Header J3

directly to the ADC3 pin (Pin 80) of the ADuC7026.

Slide S1-4 to the off position to disconnect ADC3 of Header J3

from the ADC3 pin (Pin 80) of the ADuC7026.

S1-5 VIN−

Function

Connects the −OUT pin of the single-ended to differential op

amp (AD8132) to ADC3. S1-5 and S1-6 must be used together.

When VIN− is in the on position, VIN+ must also be in the on

position to use the differential op amp on Channel ADC3 and

Channel ADC4.

Use

Slide S1-5 to the on position to connect −OUT of the AD8132

to ADC3.

Slide S1-5 to the off position to use ADC3 without the AD8132.

S1-6 VIN+

Function

Connects the +OUT pin of the single-ended to differential op

amp (AD8132) to ADC4. When VIN+ is in the on position,

VIN− must also be in the on position to use the differential op

amp on Channel ADC3 and Channel ADC4.

Use

Slide S1-6 to the on position to connect +OUT of the AD8132

to ADC4.

Slide S1-6 to the off position to use ADC4 without the AD8132.

S1-7 ADC4

Use

Slide S1-7 to the on position to connect ADC4 of Header J3

directly to the ADC4 pin (Pin 1) of the ADuC7026.

Slide S1-7 to the off position to disconnect ADC4 of Header J3

from the ADC4 pin (Pin 1) of the ADuC7026.

S1-8 LED

Function

Connects the DAC1 output to the green LED of the

demonstration circuit, D1.

Use

Slide S1-8 to the on position to connect the DAC1 output to D1.

Slide S1-8 to the off position to use the DAC1 output on

Header J3.

AN-744

Rev. A | Page 7 of 16

EXTERNAL CONNECTORS

ANALOG I/O CONNECTOR J3

Connector J3 provides external connections for all ADC inputs,

reference inputs and DAC outputs. The pinout of the connector

is shown in Tabl e 2.

POWER SUPPLY CONNECTOR J5

Connector J5 allows for the connection between the evaluation

board and the 9 V power supply provided in the ADuC7026

development system.

EMULATION CONNECTOR J4

Connector J4 provides a connection of the evaluation board to

the PC via a USB cable and mIDAS link provided in the

ADuC7026 QuickStart™ Plus development system only.

SERIAL INTERFACE CONNECTOR J1

Connector J1 provides a simple connection of the evaluation

board to the PC via a PC serial port cable provided with the

ADuC7026 development system.

DIGITAL I/O CONNECTOR J2

Connector J2 provides external connections for all GPIOs. The

pinout of the connector is shown in Table 3, with details of the

pin functions.

Table 2. Pin Functions for Analog I/O Connector J3

Pin No. Pin Description

J3-1 AVDD

J3-2 AGND

J3-3 VREF

J3-4 DACREF

J3-5 ADC0

J3-6 ADC1

J3-7 ADC2

J3-8 ADC3

J3-9 ADC4

J3-10 ADC5

J3-11 ADC6

J3-12 ADC7

J3-13 ADC8

J3-14 ADC9

J3-15 ADC10

J3-16 ADC11

J3-17 VDIFF

J3-18 VOCM

J3-19 DAC0

J3-20 DAC1

J3-21 DAC2

J3-22 DAC3

J3-23 ADCNEG

J3-24 AGND

AN-744

Rev. A | Page 8 of 16

Table 3. Pin Functions for Digital I/O Connector J2

Pin No. Pin Description

J2-1 DGND

J2-2 P4.5

AD13/PLAO[13]

J2-3 P4.4

AD12/PLAO[12]

J2-4 P4.3

AD/11PLAO[11]

J2-5 P4.2

AD10/PLAO[10]

J2-6 P1.0

T1/SIN/SCL0/PLAI[0]

J2-7 P1.1

SOUT/SDA0/PLAI[1]

J2-8 P1.2

RTS/SCL1/PLAI[2]

J2-9 P1.3

CTS/SDA1/PLAI[3]

J2-10 P1.4

IRQ2/RI/CLK/PLAI[4]

J2-11 P1.5

IRQ3/DCD/MISO/PLAI[5]

J2-12 P4.1

AD9/PLAO[9]

J2-13 P4.0

AD8/PLAO[8]

J2-14 P1.6

DSR/MOSI/PLAI[6]

J2-15 P1.7

DTR/CSL/PLAO[0]

J2-16 P2.2

PWM0L/RS/PLAO[7]

J2-17 P2.1

PWM0H/WS/PLAO[6]

J2-18 P2.7

PWM1L/MS3

J2-19 P3.7

PWMSYNC/AD7/PLAI[15]

J2-20 P3.6

PWMTRIP/AD6/PLAI[14]

J2-21 P0.7

ECLK/XCLK/SIN/PLAO[4]

Pin No. Pin Description

J2-22 P2.0

CONVSTART/SOUT/PLAO[5]

J2-23 P0.5

IRQ1/ADCBUSY/MS0/PLAO[2]

J2-24 P0.4

IRQ0/PWMTRIP/MS1/PLAO[1]

J2-25 P3.5

PWM2L/AD5/PLAI[13]

J2-26 P3.4

PWM2H/AD4/PLAI[12]

J2-27 P2.6

PWM1H/MS2

J2-28 P2.5

PWM0L/MS1

J2-29 P0.3

TRST/A16/ADCBUSY

J2-30 P2.4

PWM0H/MS0

J2-31 P3.3

PWM1L/AD3/PLAI[11]

J2-32 P3.2

PWM1H/AD2/PLAI[10]

J2-33 P3.1

PWM0L/AD1/PLAI[9]

J2-34 P3.0

PWM0H/AD0/PLAI[8]

J2-35 P0.2

PWM2L/BHE

J2-36 P0.6

T1/MRST/AE/PLAO[3]

J2-37 P0.0

CMP/MS2/PLAI[7]

J2-38 P4.7

AD15/PLAO[15]

J2-39 P4.6

AD14/PLAO[14]

J2-40 P2.3

J2-41 P0.1

PWM2H/BLE

J2-42 DGND

AN-744

Rev. A | Page 9 of 16

EXTERNAL MEMORY INTERFACE

A footprint for a 32 k × 16 SRAM, a 64 k × 16 Flash, and a

16-bit D-latch are provided on board because address and data

are multiplexed on the external bus.

The memory footprints are for a CY7C1020CV33 and

AT29LV1024. The latch footprint is for a 74LVT16373AGG.

Note that you can use different versions of the CY7C1020CV33

memory, with different access times. Wait states can be added in

the XMxPAR register to allow for interfacing to a slower

memory, if required.

CONNECTIONS

Table 4.

Connection Description

Controls RS, WS, and AE are the minimum control signals of any memory interface.

MS0 and MS1, memory select signals, are connected to the CE of the SRAM and the flash, respectively, to enable the

memory when necessary.

BHE and BLE allows the high or low byte of the 16-bit SRAM to be selected.

Data 16 bits of data AD[15-0] are directly connected from the ADuC7026 to the memory circuitry.

Addresses 16 bits of address AD[16-1] are connected from the ADuC702x to A[15-0] of the memory devices. AD[0] addresses a byte.

To address the 32 k of the SRAM only, 14-bit addresses are required.

15-bit addresses are required for the 64 k flash.

ADR [0:15] VDDIO

VCC VSS

VSS

ADR0

ADR1

ADR2

ADR15

ADR14

ADR13

ADR12

ADR11

ADR10

ADR9

ADR8

ADR7

ADR5

ADR6

ADR4

ADR3

ADR0

ADR1

ADR2

ADR14

ADR13

ADR12

ADR11

ADR10

ADR9

ADR8

ADR7

ADR5

ADR6

ADR4

ADR3

AD0

AD1

AD2

AD14

AD13

AD15

AD12

AD11

AD10

AD9

AD8

AD7

AD5

AD6

AD4

AD3

ADR0

ADR1

ADR2

ADR14

ADR13

ADR15

ADR12

ADR11

ADR10

ADR9

ADR8

ADR7

ADR5

ADR6

ADR4

ADR3

AD0

AD1

AD2

AD15

AD14

AD13

AD12

AD11

AD10

AD9

AD8

AD7

AD5

AD6

AD4

AD3

015

014

013

012

011

010

A15

A14

A13

A12

A11

A10

I01

I02

I015

I014

I016

I013

I012

I011

I010

I09

I08

I07

I05

I06

I04

I03

A14

A13

A12

A11

A10

AD0

AD1

AD2

AD15

AD14

AD13

AD12

AD11

AD10

AD9

AD8

AD7

AD5

AD6

AD4

AD3

RSMS1 OE

AT29LV1024

CY7C1020CV33-12

BHE VSS

VCC

VSS

BLE

MS0 VDDIO

BHE

BLE

1D0

1D1

1D2

2D6

2D5

2D7

2D4

2D3

2D2

2D1

2D0

1D7

VCC

1LE

2LE

2OE

1OE

1D5

1D6

1D4

1D3

1Q0

1Q1

1Q2

2Q6

2Q5

2Q7

2Q4

2Q3

2Q2

2Q1

2Q0

1Q7

GND

1Q5

1Q6

1Q4

1Q3

74LVT16373ADGG

R23

0Ω

VDDIO

5032-002

NOTES

1. THE FOOTPRINT FOR THE FLASH IS ON THE BOTTOM SIDE OF THE BOARD.

Figure 2. External Memory Connections

AN-744

Rev. A | Page 10 of 16

POTENTIOMETER DEMONSTRATION CIRCUIT

By using the sample code in pot.c located in the code example

folder on the accompanying CD, the variation in the

potentiometer resistance can be seen on the output LED.

Note that the internal and external reference are 2.5 V,

which gives an ADC input range of 0 V to 2.5 V in single-ended

mode. The potentiometer can give a voltage between 0 V and

AVDD = 3.3 V.

VDD

APPLICATION

CODE

DACADC

05032-003

Figure 3. Circuit Diagram of the RTD Circuit

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