Analog Devices SHARC ADSP-21368 Guía de aplicación

ADSP-21368 SHARC®Processor

Hardware Reference

Includes ADSP-21367, ADSP-21369,

ADSP-21371, ADSP-21375

Revision 1.0, September 2006

Part Number

82-000100-01

Analog Devices, Inc.

One Technology Way

Norwood, Mass. 02062-9106

document may not be reproduced in any form without prior,

express written consent from Analog Devices, Inc.

Printed in the USA.

Disclaimer

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use. No license is granted by implication or otherwise under the

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Trademark and Service Mark Notice

The Analog Devices logo and icon bar, Blackfin, EZ-KIT Lite,

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All other brand and product names are trademarks or service marks

of their respective owners.

ADSP-21368 SHARC Processor Hardware Reference iii

CONTENTS

PREFACE

Purpose of This Manual ............................................................... xxxi

Intended Audience ....................................................................... xxxi

Manual Contents ........................................................................ xxxii

What’s New in This Manual ....................................................... xxxiv

Technical or Customer Support ................................................... xxxv

Supported Processors .................................................................. xxxvi

Product Information .................................................................. xxxvi

MyAnalog.com .................................................................... xxxvii

Processor Product Information ............................................. xxxvii

Related Documents ............................................................ xxxviii

Online Technical Documentation ......................................... xxxix

Printed Manuals ....................................................................... xli

Conventions ................................................................................ xliii

INTRODUCTION

Design Advantages ........................................................................ 1-1

Architectural Overview ................................................................. 1-6

Processor Core ......................................................................... 1-7

Contents

iv ADSP-21368 SHARC Processor Hardware Reference

Processor Peripherals ............................................................... 1-7

I/O Processor ..................................................................... 1-7

Digital Audio Interface (DAI) ............................................. 1-9

Digital Peripheral Interface (DPI) ..................................... 1-10

Development Tools ..................................................................... 1-10

Differences From Previous Processors .......................................... 1-11

I/O Architecture Enhancements ............................................ 1-11

Instruction Set Enhancements ............................................... 1-12

I/O PROCESSOR

General Procedure for Configuring DMA ...................................... 2-2

Core Access to IOP Registers ........................................................ 2-3

Configuring IOP/Core Interaction ................................................ 2-6

Interrupt-Driven I/O .............................................................. 2-6

Interrupt Latency in Interrupt-Driven Transfers ................ 2-11

Polling/Status-Driven I/O ..................................................... 2-12

DMA Controller Operation .................................................. 2-13

Chaining DMA Processes .................................................. 2-14

Transfer Control Block Chain Loading (TCB) ................... 2-16

Setting Up DMA Channel Allocation and Priorities ............... 2-18

Managing DMA Channel Priority ..................................... 2-19

DMA Bus Arbitration ....................................................... 2-20

Setting Up DMA Parameter Registers .......................................... 2-24

DMA Transfer Direction ....................................................... 2-24

Data Buffer Registers ............................................................ 2-25

ADSP-21368 SHARC Processor Hardware Reference v

Contents

Port, Buffer, and DMA Control Registers ............................... 2-26

Addressing ............................................................................ 2-29

External Port DMA ..................................................................... 2-35

Setting Up and Starting Chained DMA .................................. 2-36

Delay Line DMA ................................................................... 2-38

Serial Port DMA ......................................................................... 2-40

Setting Up and Starting Chained DMA .................................. 2-40

Inserting a TCB in an Active Chain ....................................... 2-41

Serial Peripheral Interface DMA .................................................. 2-42

Setting Up and Starting Chained DMA over the SPI .............. 2-42

UART DMA ............................................................................... 2-44

Notes On Using DMA With the UART ................................. 2-47

Memory-to-Memory DMA ......................................................... 2-48

Summary .................................................................................... 2-48

Programming Example ................................................................ 2-49

EXTERNAL PORT

External Memory Interface ............................................................ 3-2

External Memory Interface on the ADSP-2137x Processors ...... 3-3

Direct Execution of Instructions From External Memory ..... 3-3

Throughput and Instruction Execution Rate ........................ 3-3

Location of Interrupt Vector Table (IVT) ............................ 3-4

Instruction Cache ............................................................... 3-5

Instruction Storage and Packing .......................................... 3-9

Contents

vi ADSP-21368 SHARC Processor Hardware Reference

EMI Registers and Signals ..................................................... 3-16

External Port Arbitration Logic ......................................... 3-18

Channel Freezing .............................................................. 3-18

Managing Data Paths ........................................................ 3-18

External Memory Interface Pins ............................................ 3-19

Asynchronous Memory Interface ................................................. 3-20

AMI Timing Control .................................................................. 3-21

Wait States ............................................................................ 3-21

Bus Idle Cycles ...................................................................... 3-22

Bus Hold Cycles .................................................................... 3-23

Setting AMI Modes .................................................................... 3-24

External Memory Reads ........................................................ 3-25

Data Packing .................................................................... 3-25

External Memory Writes ....................................................... 3-26

Data Packing .................................................................... 3-27

Read/Write Throughput ........................................................ 3-28

External Access Addressing .................................................... 3-28

External Port DMA ............................................................... 3-30

Booting Through the AMI .................................................... 3-30

SDRAM Controller .................................................................... 3-30

Definition of Terms .............................................................. 3-31

Timing External Memory Accesses ......................................... 3-36

Parallel Connection of SDRAMs ........................................... 3-39

SDRAM Control Register (SDCTL) ...................................... 3-39

ADSP-21368 SHARC Processor Hardware Reference vii

Contents

SDRAM Control Status Register (SDSTAT) ........................... 3-49

SDRAM Refresh Rate Control Register (SDRRC) .................. 3-49

SDRAM Initialization ........................................................... 3-51

SDRAM Address Mapping .................................................... 3-51

SDRAM Controller Address Mapping ............................... 3-58

SDC Operation ..................................................................... 3-58

Single Bank Operation ...................................................... 3-60

Multibank Operation (ADSP-2137x Processors) ................ 3-60

Data Mask (DQM) ........................................................... 3-61

SDC Configuration ............................................................... 3-61

SDC Commands ................................................................... 3-63

Load Mode Register .......................................................... 3-64

Single Bank Activation ...................................................... 3-65

Multibank Activation (ADSP-2137x Processors) ................ 3-66

Single Precharge (ADSP-2137x Processors) ........................ 3-66

Precharge All ..................................................................... 3-66

Read/Write ....................................................................... 3-67

Read/Write (ADSP-2137x Processors) ............................... 3-69

Burst Stop (ADSP-2137x Processors) ................................. 3-69

Auto-Refresh ..................................................................... 3-70

Self-Refresh Mode ............................................................. 3-70

No Operation/Command Inhibit ...................................... 3-71

Changing System Clock During Runtime .......................... 3-73

Contents

viii ADSP-21368 SHARC Processor Hardware Reference

SDRAM Timing ................................................................... 3-74

SDRAM Read Optimization ............................................. 3-75

External Memory Access Restrictions ................................ 3-78

Shared Memory Interface ............................................................ 3-79

Shared Memory Bus Arbitration ............................................ 3-79

Bus Arbitration Protocol ................................................... 3-82

Bus Arbitration Priority (RPBA) ....................................... 3-86

Bus Mastership Time-out .................................................. 3-87

Bus Synchronization After Reset ............................................ 3-88

Bus Synchronization Notes ............................................... 3-91

Bus Lock and Semaphores ..................................................... 3-92

Shared Memory Interface Status ........................................ 3-93

Shared Memory and the SDRAM Controller ......................... 3-94

Shared Memory Booting ....................................................... 3-94

DIGITAL AUDIO/DIGITAL PERIPHERAL INTERFACES

Structure of the Interfaces ............................................................. 4-2

DAI/DPI System Design ............................................................... 4-3

Signal Routing Units .................................................................... 4-8

Connecting Peripherals ........................................................... 4-8

Pin Interface ......................................................................... 4-10

Pin Buffers as Signal Output Pins .......................................... 4-11

Pin Buffers as Signal Input Pins ............................................. 4-12

Bidirectional Pin Buffers ....................................................... 4-13

ADSP-21368 SHARC Processor Hardware Reference ix

Contents

Making Connections in the SRUs ................................................ 4-15

DAI/SRU1 Connection Groups ............................................. 4-18

Group A Connections—Clock Signals ............................... 4-19

Group B Connections—Data Signals ................................. 4-25

Group C Connections—Frame Sync Signals ...................... 4-31

Group D Connections—Pin Signal Assignments ................ 4-36

Group E Connections—Interrupts and Miscellaneous

Signals ........................................................................... 4-43

Group F—Pin Enable Signals ............................................ 4-47

DPI/SRU2 Connection Groups ............................................. 4-51

Group A Connections—Input Routing Signals .................. 4-52

Group B Connections—Pin Assignment Signals ............... 4-56

Group C Connections—Pin Enable Signals ...................... 4-60

General-Purpose I/O (GPIO) and Flags ....................................... 4-64

DAI GPIO and Flags ............................................................. 4-64

DPI GPIO and Flags ............................................................. 4-65

Miscellaneous Signals .................................................................. 4-65

DAI/DPI Interrupt Controller ..................................................... 4-65

Relationship to the Core ........................................................ 4-65

DAI Interrupts ...................................................................... 4-66

DPI Interrupts ...................................................................... 4-67

High and Low Priority Latches .............................................. 4-69

Rising and Falling Edge Masks ............................................... 4-70

Contents

x ADSP-21368 SHARC Processor Hardware Reference

Configuring Peripherals Using SRU1 .......................................... 4-71

Configuring the SPORTs ...................................................... 4-71

Configuring the PCGs .......................................................... 4-72

Configuring Peripherals Using SRU2 .......................................... 4-72

Configuring the SPI .............................................................. 4-72

Choosing the Pin Enable for the SPI Clock ....................... 4-72

Configuring the Two Wire Interface ...................................... 4-73

Using the SRU() Macro to Configure

the DAI ................................................................................... 4-76

SERIAL PORTS

Features ........................................................................................ 5-2

Operation Modes ......................................................................... 5-3

Serial Port Signals ......................................................................... 5-5

Serial Port Signal Sensitivity .................................................... 5-9

SPORT Operation Modes ........................................................... 5-10

Standard DSP Serial Mode .................................................... 5-12

Standard DSP Serial Mode Control Bits ............................ 5-13

Clocking Options ............................................................. 5-13

Frame Sync Options ......................................................... 5-13

Data Formatting ............................................................... 5-14

Data Transfers .................................................................. 5-15

Status Information ............................................................ 5-15

Left-Justified Sample Pair Mode ............................................ 5-16

Setting the Internal Serial Clock and Frame Sync Rates ..... 5-17

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