Analog Devices ADSP-BF535 Blackfin Guía de aplicación

ADSP-BF535 Blackfin®Processor

Hardware Reference

Revision 3.3, February 2013

Part Number

82-000410-13

Analog Devices, Inc.

One Technology Way

Norwood, Mass. 02062-9106

ment may not be reproduced in any form without prior, express written

consent from Analog Devices, Inc.

Printed in the USA.

Disclaimer

Analog Devices, Inc. reserves the right to change this product without

prior notice. Information furnished by Analog Devices is believed to be

accurate and reliable. However, no responsibility is assumed by Analog

Devices for its use; nor for any infringement of patents or other rights of

third parties which may result from its use. No license is granted by impli-

cation or otherwise under the patent rights of Analog Devices, Inc.

Trademark and Service Mark Notice

The Analog Devices logo, Blackfin, CrossCore, VisualDSP++, and

EZ-KIT Lite are registered trademarks of Analog Devices, Inc.

All other brand and product names are trademarks or service marks of

their respective owners.

ADSP-BF535 Blackfin Processor Hardware Reference iii

CONTENTS

PREFACE

Purpose of This Manual ............................................................. xliii

Intended Audience ...................................................................... xliii

Manual Contents ......................................................................... xliv

What’s New in This Manual ..................................................... xlviii

Technical Support ..................................................................... xlviii

Supported Processors .................................................................... xlix

Product Information ........................................................................ l

Analog Devices Web Site ............................................................ l

EngineerZone ............................................................................ li

Notation Conventions .................................................................... lii

INTRODUCTION

ADSP-BF535 Peripherals .............................................................. 1-1

ADSP-BF535 Core Architecture .................................................... 1-2

Memory Architecture .................................................................... 1-5

Internal (On-Chip) Memory .................................................... 1-7

External (Off-Chip) Memory ................................................... 1-8

Contents

iv ADSP-BF535 Blackfin Processor Hardware Reference

PCI ........................................................................................ 1-8

I/O Memory Space ................................................................ 1-10

Event Handling .......................................................................... 1-10

DMA Support ........................................................................... 1-11

External Bus Interface Unit ......................................................... 1-12

PC133 SDRAM Controller ................................................... 1-12

Asynchronous Controller ...................................................... 1-13

PCI Interface .............................................................................. 1-13

PCI Host Function ............................................................... 1-14

PCI Target Function ............................................................. 1-15

USB Port .................................................................................... 1-15

Real-Time Clock ........................................................................ 1-15

Watchdog Timer ......................................................................... 1-16

Timers ....................................................................................... 1-17

Serial Ports (SPORTs) ................................................................. 1-17

Serial Peripheral Interface (SPI) Ports .......................................... 1-19

UART Ports ............................................................................... 1-20

Programmable Flags .................................................................... 1-21

Low Power Operation ................................................................. 1-22

Full On Operating Mode (Maximum Performance) ............... 1-22

Active Operating Mode (Low Power Savings) ......................... 1-22

Sleep Operating Mode (High Power Savings) ......................... 1-23

Deep Sleep Operating Mode (Maximum Power Savings) ........ 1-23

Clock Signals .............................................................................. 1-23

ADSP-BF535 Blackfin Processor Hardware Reference v

Contents

Boot Modes ................................................................................ 1-24

Instruction Set Description ......................................................... 1-24

Development Tools ..................................................................... 1-24

COMPUTATIONAL UNITS

Using Data Formats ...................................................................... 2-3

Binary String ........................................................................... 2-3

Unsigned ................................................................................. 2-4

Signed Numbers: Two’s-Complement ....................................... 2-4

Fractional Representation: 1.15 ................................................ 2-4

Data Register File .................................................................... 2-6

Accumulator Registers ............................................................ 2-6

Pointer Register File ................................................................ 2-6

DAG Register Set ................................................................... 2-7

Data Types .................................................................................. 2-10

Data Formats ........................................................................ 2-11

Endianess .............................................................................. 2-12

ALU Data Types .................................................................... 2-12

Multiplier Data Types ............................................................ 2-13

Shifter Data Types ................................................................. 2-14

Arithmetic Formats Summary ................................................ 2-15

Using Multiplier Integer and Fractional Formats .................... 2-16

Contents

vi ADSP-BF535 Blackfin Processor Hardware Reference

Rounding Multiplier Results ................................................. 2-18

Unbiased Rounding .......................................................... 2-18

Biased Rounding .............................................................. 2-20

Truncation ....................................................................... 2-21

Special Rounding Instructions ............................................... 2-21

Using Computational Status ....................................................... 2-22

Arithmetic Status Register (ASTAT) ............................................ 2-23

Arithmetic Logic Unit (ALU) ...................................................... 2-24

ALU Operations ................................................................... 2-24

Single 16-Bit Operations .................................................. 2-25

Dual 16-Bit Operations .................................................... 2-25

Quad 16-Bit Operations ................................................... 2-25

Single 32-Bit Operations .................................................. 2-27

Dual 32-Bit Operations .................................................... 2-27

ALU Instruction Summary .................................................... 2-28

ALU Data Flow Details ......................................................... 2-28

Dual 16-Bit Cross Options .............................................. 2-30

ALU Status Signals ........................................................... 2-31

ALU Division Support Features ............................................. 2-31

Special SIMD Video ALU Operations .................................. 2-32

Multiply Accumulators (Multipliers) ........................................... 2-32

Multiplier Operation ............................................................. 2-33

Placing Multiplier Results in Multiplier Accumulator

Registers ........................................................................ 2-34

Rounding or Saturating Multiplier Results ........................ 2-34

ADSP-BF535 Blackfin Processor Hardware Reference vii

Contents

Saturating Multiplier Results on Overflow ............................ 2-35

Multiplier Instruction Summary ............................................ 2-35

Multiplier Instruction Options .......................................... 2-35

Multiplier Data Flow Details ................................................. 2-38

Multiply Without Accumulate ............................................... 2-40

Special 32-Bit Integer MAC Instruction ................................. 2-42

Dual MAC Operations .......................................................... 2-43

Barrel Shifter (Shifter) ................................................................. 2-44

Shifter Operations ................................................................. 2-44

Two Operand Shifts .......................................................... 2-45

Immediate Shifts ........................................................... 2-45

Three Operand Shifts ........................................................ 2-46

Immediate Shifts ........................................................... 2-46

Bit Test, Set, Clear, Toggle ................................................ 2-48

Field Extract and Field Deposit ......................................... 2-48

Shifter Instruction Summary .................................................. 2-48

OPERATING MODES AND STATES

User Mode .................................................................................... 3-3

Protected Resources and Instructions ....................................... 3-4

Protected Memory ................................................................... 3-5

Contents

viii ADSP-BF535 Blackfin Processor Hardware Reference

Entering User Mode ................................................................ 3-5

Example Code to Enter User Mode Upon Reset ................... 3-5

Return Instructions That Invoke User Mode ....................... 3-5

Supervisor Mode .......................................................................... 3-6

Non-OS Environments ........................................................... 3-7

Example Code to Stay in Supervisor Mode Coming Out of

Reset ............................................................................... 3-8

Emulation Mode .......................................................................... 3-9

Idle State ...................................................................................... 3-9

Example Code for Transition to Idle State .............................. 3-10

Reset State .................................................................................. 3-10

System Reset and Power-up Configuration .................................. 3-12

Hardware Reset ..................................................................... 3-13

System Reset Configuration Register (SYSCR) ....................... 3-14

Software Resets and Watchdog Timer .................................... 3-14

Software Reset Register (SWRST) ......................................... 3-16

Core Only Software Reset ..................................................... 3-17

Booting Methods ........................................................................ 3-17

PROGRAM SEQUENCER

Sequencer Related Registers ......................................................... 4-3

Sequencer Status Register (SEQSTAT) ..................................... 4-4

Zero-Overhead Loop Registers (LC, LT, LB) ............................ 4-5

System Configuration Register (SYSCFG) ............................... 4-6

Instruction Pipeline ...................................................................... 4-7

ADSP-BF535 Blackfin Processor Hardware Reference ix

Contents

Branches and Sequencing .............................................................. 4-9

Direct Short and Long Jumps ................................................ 4-11

Direct Call ........................................................................... 4-11

Indirect Branch and Call ........................................................ 4-11

PC-Relative Indirect Branch and Call ..................................... 4-12

Condition Code Flag ............................................................. 4-12

Conditional Branches ........................................................ 4-13

Conditional Register Move ................................................ 4-13

Branch Prediction .................................................................. 4-14

Loops and Sequencing ................................................................. 4-15

Events and Sequencing ................................................................ 4-17

System Interrupt Processing ................................................... 4-20

System Peripheral Interrupts .................................................. 4-22

System Interrupt Wakeup-Enable Register (SIC_IWR) ........... 4-24

System Interrupt Status Register (SIC_ISR) ........................... 4-25

System Interrupt Mask Register (SIC_IMASK) ...................... 4-27

System Interrupt Assignment Registers (SIC_IARx) ................ 4-29

Event Controller Registers ........................................................... 4-31

Core Interrupt Mask Register (IMASK) ................................. 4-32

Core Interrupt Latch Register (ILAT) ..................................... 4-32

Core Interrupts Pending Register (IPEND) ............................ 4-33

Global Enabling/Disabling of Interrupts ...................................... 4-34

Contents

x ADSP-BF535 Blackfin Processor Hardware Reference

Event Vector Table ...................................................................... 4-35

Emulation ............................................................................. 4-36

Reset .................................................................................... 4-36

NMI (Non-Maskable Interrupt) ............................................ 4-38

Exceptions ............................................................................ 4-38

Exceptions While Executing an Exception Handler ................ 4-43

Hardware Error Interrupt ........................................................... 4-44

Core Timer ........................................................................... 4-46

General-Purpose Interrupts (IVG7-IVG15) ............................ 4-46

Servicing Interrupts .................................................................... 4-46

Interrupts With and Without Nesting ......................................... 4-48

Example Prolog Code for Nested Interrupt Service Routine .... 4-51

Example Epilog Code for Nested Interrupt Service Routine .... 4-51

Logging of Nested Interrupt Requests .................................... 4-52

Self-Nesting Mode ................................................................ 4-53

Exception Handling .............................................................. 4-54

Deferring Exception Processing ......................................... 4-55

Example Code for an Exception Handler ........................... 4-55

Example Code for an Exception Routine ........................... 4-57

Executing RTX, RTN, or RTE in a Lower Priority Event ... 4-57

Recommendation for Allocating the System Stack ............. 4-58

Latency in Servicing Events ................................................... 4-58

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