Altera MAX 10 series Manual de usuario
MAX 10 High-Speed LVDS I/O User Guide
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2016.10.31
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San Jose, CA 95134
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Contents
MAX 10 High-Speed LVDS I/O Overview..........................................................1-1
Altera So LVDS Implementation Overview...........................................................................................1-2
MAX 10 High-Speed LVDS Architecture and Features......................................2-1
MAX 10 LVDS Channels Support ............................................................................................................ 2-1
MAX 10 LVDS SERDES I/O Standards Support..................................................................................... 2-7
MAX 10 High-Speed LVDS Circuitry.....................................................................................................2-10
MAX 10 High-Speed LVDS I/O Location.............................................................................................. 2-11
Dierential I/O Pins in Low Speed Region............................................................................................ 2-14
MAX 10 LVDS Transmitter Design.....................................................................3-1
High-Speed I/O Transmitter Circuitry..................................................................................................... 3-1
LVDS Transmitter Programmable I/O Features...................................................................................... 3-1
Programmable Pre-Emphasis.........................................................................................................3-1
Programmable Dierential Output Voltage................................................................................. 3-2
LVDS Transmitter I/O Termination Schemes..........................................................................................3-3
Emulated LVDS External Termination......................................................................................... 3-3
Sub-LVDS Transmitter External Termination............................................................................. 3-3
SLVS Transmitter External Termination.......................................................................................3-4
Emulated RSDS, Emulated Mini-LVDS, and Emulated PPDS Transmitter External
Termination.................................................................................................................................3-4
LVDS Transmitter FPGA Design Implementation..................................................................................3-5
Altera So LVDS IP Core in Transmitter Mode.......................................................................... 3-6
High-Speed I/O Timing Budget.....................................................................................................3-8
Guidelines: LVDS Transmitter Channels Placement...................................................................3-9
Guidelines: LVDS Channels PLL Placement................................................................................ 3-9
Guidelines: LVDS Transmitter Logic Placement......................................................................... 3-9
Guidelines: Enable LVDS Pre-Emphasis for E144 Package......................................................3-10
LVDS Transmitter Debug and Troubleshooting....................................................................................3-10
Perform RTL Simulation Before Hardware Debug................................................................... 3-10
Geometry-Based and Physics-Based I/O Rules......................................................................... 3-10
MAX 10 LVDS Receiver Design.......................................................................... 4-1
High-Speed I/O Receiver Circuitry........................................................................................................... 4-1
So Deserializer................................................................................................................................4-1
Data Realignment Block (Bit Slip).................................................................................................4-2
LVDS Receiver I/O Termination Schemes................................................................................................4-2
LVDS, Mini-LVDS, and RSDS Receiver External Termination.................................................4-3
SLVS Receiver External Termination.............................................................................................4-3
Sub-LVDS Receiver External Termination...................................................................................4-3
TOC-2
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TMDS Receiver External Termination..........................................................................................4-4
HiSpi Receiver External Termination............................................................................................4-4
LVPECL External Termination...................................................................................................... 4-5
LVDS Receiver FPGA Design Implementation....................................................................................... 4-6
Altera So LVDS IP Core in Receiver Mode................................................................................4-6
High-Speed I/O Timing Budget.....................................................................................................4-9
Guidelines: Floating LVDS Input Pins........................................................................................ 4-13
Guidelines: LVDS Receiver Channels Placement...................................................................... 4-13
Guidelines: LVDS Channels PLL Placement.............................................................................. 4-13
Guidelines: LVDS Receiver Logic Placement.............................................................................4-14
Guidelines: LVDS Receiver Timing Constraints........................................................................4-14
LVDS Receiver Debug and Troubleshooting..........................................................................................4-14
Perform RTL Simulation Before Hardware Debug................................................................... 4-14
Geometry-Based and Physics-Based I/O Rules......................................................................... 4-14
MAX 10 LVDS Transmitter and Receiver Design...............................................5-1
Transmitter–Receiver Interfacing.............................................................................................................. 5-1
LVDS Transmitter and Receiver FPGA Design Implementation.......................................................... 5-2
LVDS Transmitter and Receiver PLL Sharing Implementation.................................................5-2
Initializing the Altera So LVDS IP Core.....................................................................................5-3
LVDS Transmitter and Receiver Debug and Troubleshooting...............................................................5-3
Perform RTL Simulation Before Hardware Debug......................................................................5-3
Geometry-Based and Physics-Based I/O Rules........................................................................... 5-3
MAX 10 High-Speed LVDS Board Design Considerations................................6-1
Guidelines: Improve Signal Quality...........................................................................................................6-1
Guidelines: Control Channel-to-Channel Skew...................................................................................... 6-1
Guidelines: Determine Board Design Constraints..................................................................................6-2
Guidelines: Perform Board Level Simulations......................................................................................... 6-2
Altera So LVDS IP Core References................................................................. 7-1
Altera So LVDS Parameter Settings ....................................................................................................... 7-1
Altera So LVDS Interface Signals............................................................................................................ 7-7
MAX 10 High-Speed LVDS I/O User Guide Archives....................................... A-1
Document Revision History for MAX 10 High-Speed LVDS I/O User Guide..
B-1
TOC-3
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MAX 10 High-Speed LVDS I/O Overview 1
2016.10.31
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e MAX®10 device family supports high-speed LVDS protocols through the LVDS I/O banks and the
Altera So LVDS IP core.
Table 1-1: Summary of LVDS I/O Buers Support in MAX 10 I/O Banks
I/O Buer Type I/O Bank Support
True LVDS input buer All I/O banks
True LVDS output buer Only bottom I/O banks
Emulated LVDS output buer All I/O banks
e LVDS I/O standards support diers between MAX 10 D and S variants. Refer to related information
for more details.
Related Information
•MAX 10 High-Speed LVDS Architecture and Features on page 2-1
Provides information about the high-speed LVDS architecture and the features supported by the
device.
•MAX 10 LVDS Transmitter Design on page 3-1
Provides information and guidelines for implementing LVDS transmitter in MAX 10 devices using the
Altera So LVDS IP core.
•MAX 10 LVDS Receiver Design on page 4-1
Provides information and guidelines for implementing LVDS receiver in MAX 10 devices using the
Altera So LVDS IP core.
•MAX 10 LVDS Transmitter and Receiver Design on page 5-1
Provides design guidelines for implementing both LVDS transmitters and receivers in the same MAX
10 device.
•Altera So LVDS IP Core References on page 7-1
Lists the parameters and signals of Altera So LVDS IP core for MAX 10 devices.
•MAX 10 LVDS SERDES I/O Standards Support on page 2-7
Lists the supported LVDS I/O standards and the support in dierent MAX 10 device variants.
•MAX 10 High-Speed LVDS I/O User Guide Archives on page 8-1
Provides a list of user guides for previous versions of the Altera So LVDS IP core.
©2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos
are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants
performance of its FPGA and semiconductor products to current specications in accordance with Intel's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of
device specications before relying on any published information and before placing orders for products or services.
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Altera Soft LVDS Implementation Overview
You can implement LVDS applications in MAX 10 devices as transmitter-only, receiver-only, or a
combination of transmitters and receivers.
Figure 1-1: MAX 10 LVDS Implementation Overview
Altera Soft LVDS
LVDS Transmitter
Implementation
LVDS Transmitter
and Receiver
Implementation
LVDS Receiver
Implementation
1-2 Altera Soft LVDS Implementation Overview UG-M10LVDS
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MAX 10 High-Speed LVDS Architecture and
Features 2
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e MAX 10 devices use registers and logic in the core fabric to implement LVDS input and output
interfaces.
• For LVDS transmitters and receivers, MAX 10 devices use the the double data rate I/O (DDIO)
registers that reside in the I/O elements (IOE). is architecture improves performance with regards to
the receiver input skew margin (RSKM) or transmitter channel-to-channel skew (TCCS).
• For the LVDS serializer/deserializer (SERDES), MAX 10 devices use logic elements (LE) registers.
Related Information
•MAX 10 High-Speed LVDS I/O Overview on page 1-1
•MAX 10 LVDS SERDES I/O Standards Support on page 2-7
Lists the supported LVDS I/O standards and the support in dierent MAX 10 device variants.
MAX 10 LVDS Channels Support
e LVDS channels available vary among MAX 10 devices. All I/O banks in MAX 10 devices support true
LVDS input buers and emulated LVDS output buers. However, only the bottom I/O banks support true
LVDS output buers.
Table 2-1: LVDS Buers in MAX 10 Devices
is table lists the LVDS buer support for I/O banks on each side of the devices.
©2016 Intel Corporation. All rights reserved. Intel, the Intel logo, Altera, Arria, Cyclone, Enpirion, MAX, Megacore, NIOS, Quartus and Stratix words and logos
are trademarks of Intel Corporation in the US and/or other countries. Other marks and brands may be claimed as the property of others. Intel warrants
performance of its FPGA and semiconductor products to current specications in accordance with Intel's standard warranty, but reserves the right to make
changes to any products and services at any time without notice. Intel assumes no responsibility or liability arising out of the application or use of any
information, product, or service described herein except as expressly agreed to in writing by Intel. Intel customers are advised to obtain the latest version of
device specications before relying on any published information and before placing orders for products or services.
ISO
9001:2008
Registered
www.altera.com
101 Innovation Drive, San Jose, CA 95134
Product Line Package Side
True LVDS Pairs Emulated LVDS Pairs
TX RX
10M02
V36
Top 0 1 1
Right 0 3 3
Le 0 3 3
Bottom 3 3 3
M153
Top 0 12 12
Right 0 12 12
Le 0 12 12
Bottom 9 13 13
U169
Top 0 12 12
Right 0 17 17
Le 0 15 15
Bottom 9 14 14
U324
Top 0 13 13
Right 0 24 24
Le 0 20 20
Bottom 9 16 16
E144
Top 0 10 10
Right 0 12 12
Le 0 11 11
Bottom 7 12 12
2-2 MAX 10 LVDS Channels Support UG-M10LVDS
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Product Line Package Side
True LVDS Pairs Emulated LVDS Pairs
TX RX
10M04
M153
Top 0 12 12
Right 0 12 12
Le 0 12 12
Bottom 9 13 13
U169
Top 0 12 12
Right 0 17 17
Le 0 15 15
Bottom 9 14 14
U324
Top 0 27 27
Right 0 31 31
Le 0 28 28
Bottom 15 28 28
F256
Top 0 19 19
Right 0 22 22
Le 0 19 19
Bottom 13 20 20
E144
Top 0 8 8
Right 0 12 12
Le 0 11 11
Bottom 10 10 10
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Product Line Package Side
True LVDS Pairs Emulated LVDS Pairs
TX RX
10M08
V81
Top 0 5 5
Right 0 7 7
Le 0 6 6
Bottom 7 7 7
M153
Top 0 12 12
Right 0 12 12
Le 0 12 12
Bottom 9 13 13
U169
Top 0 12 12
Right 0 17 17
Le 0 15 15
Bottom 9 14 14
U324
Top 0 27 27
Right 0 31 31
Le 0 28 28
Bottom 15 28 28
F256
Top 0 19 19
Right 0 22 22
Le 0 19 19
Bottom 13 20 20
E144
Top 0 8 8
Right 0 12 12
Le 0 11 11
Bottom 10 10 10
F484
Top 0 27 27
Right 0 33 33
Le 0 28 28
Bottom 15 28 28
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Product Line Package Side
True LVDS Pairs Emulated LVDS Pairs
TX RX
10M16
U169
Top 0 12 12
Right 0 17 17
Le 0 15 15
Bottom 9 14 14
U324
Top 0 27 27
Right 0 31 31
Le 0 28 28
Bottom 15 28 28
F256
Top 0 19 19
Right 0 22 22
Le 0 19 19
Bottom 13 20 20
E144
Top 0 8 8
Right 0 12 12
Le 0 11 11
Bottom 10 10 10
F484
Top 0 39 39
Right 0 38 38
Le 0 32 32
Bottom 22 42 42
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