ADMtek ADM5120 Manual de usuario

ADM5120

HOME GATEWAY CONTROLLER

Datasheet

Version 1.13

ADMtek.com.tw

Information in this document is provided in connection with ADMtek products. ADMtek may make

changes to specifications and product descriptions at any time, without notice. Designers must not rely on

the absence or characteristics of any features or instructions marked “reserved” or “undefined”. ADMtek

reserves these for future definition and shall have no responsibility whatsoever for conflicts or

incompatibilities arising from future changes to them

The products may contain design defects or errors known as errata, which may cause the product to deviate

from published specifications. Current characterized errata are available on request. To obtain the latest

documentation please contact you local ADMtek sales office or visit ADMtek’s website at

http://www.admtek.com.tw

*Third-party brands and names are the property of their respective owners.

ADMtek Inc. V1.13

About this Manual

Structure

This Data sheet contains 6 chapters

Chapter 1 Product Overview

Chapter 2 Interface Description

Chapter 3 Function Description

Chapter 4. Register Description

Chapter 5 Electrical Packaging

Chapter 6. Packaging

Customer Support

ADMtek Incorporated,

2F, No.2, Li-Hsin Rd.,

Science-based Industrial Park,

Hsinchu, 300, Taiwan, R.O.C.

Sales Information

Tel + 886-3-5788879

Fax + 886-3-5788871

ADM5120

ADMtek Inc. V1.13

Revision History

ADM5120

Date Version Change

19 March 2003 1.0 First release of ADM5120

05 June 2003 1.1 3.4, 4.5, 4.6, 4.7, 4.8 and 5.3 sections added. Updated pin

numbers.

13 June 2003 1.11 Updated Table for Clock Speeds

08 October 2003 1.12 2.2.5 Memory Bus : A[2]

2.2.10 PCI added CLK I/P

2.2.11 USB added CLK I/P

2.2.14 Corrected pin name

2.2.15 Changed I to O

4.4.1 Switched bits

4.4.11 Removed bits 31 – 17

4.4.12 Bits 31 – 30 bit error

4.4.13 Added bit [6]

29 October 1.13 2.2.5 Added default value to A[0], A[1] & A[13]

2.2.9 Added note

ADMtek Inc. V1.13

Table of Contents

CHAPTER 1 PRODUCT OVERVIEW ......................................................................1-1

1.1 OVERVIEW ............................................................................................................ 1-1

1.1.1 Product Order Information......................................................................1-1

1.2 FEATURES ............................................................................................................. 1-2

1.3 BLOCK DIAGRAM.................................................................................................. 1-3

1.4 ABBREVIATIONS ................................................................................................... 1-3

1.5 CONVENTIONS ...................................................................................................... 1-5

1.5.1 Data Lengths............................................................................................1-5

1.5.2 Register Descriptions...............................................................................1-5

1.5.3 Pin Descriptions.......................................................................................1-5

CHAPTER 2 INTERFACE DESCRIPTION..............................................................2-1

2.1 PIN ASSIGNMENT .................................................................................................. 2-1

2.1.1 324BGA Ball assignment.........................................................................2-1

2.1.2 208PQFP pin assignment........................................................................2-3

2.2 PIN DESCRIPTION BY FUNCTION............................................................................ 2-4

2.2.1 Network Media Connection .....................................................................2-5

2.2.2 Clock for Network....................................................................................2-5

2.2.3 LED..........................................................................................................2-5

2.2.4 GMII/MII Management............................................................................2-6

2.2.5 Memory Bus.............................................................................................2-7

2.2.6 SDRAM Control Signals..........................................................................2-8

2.2.7 UART........................................................................................................2-8

2.2.8 JTAG........................................................................................................2-9

2.2.9 General Purpose I/O (GPIO)...................................................................2-9

2.2.10 PCI...........................................................................................................2-9

2.2.11 USB........................................................................................................2-10

2.2.12 NAND Flash...........................................................................................2-10

2.2.13 External CS/INT/wait.............................................................................2-10

2.2.14 Power and Ground.................................................................................2-12

2.2.15 Regulator Interface................................................................................2-12

2.2.16 Miscellaneous ........................................................................................2-12

CHAPTER 3 FUNCTION DESCRIPTION................................................................3-1

3.1 SYSTEM................................................................................................................. 3-1

3.1.1 Frequency ................................................................................................3-1

3.1.2 Boot code data-width...............................................................................3-1

3.1.3 GMII/MII port..........................................................................................3-1

3.2 PHY...................................................................................................................... 3-2

3.2.1 PHY Overview..........................................................................................3-2

3.2.2 Link Detect...............................................................................................3-2

3.2.3 Auto-Negotiation......................................................................................3-2

3.2.4 Digital Adaptive Equalizer ......................................................................3-2

ADM5120 i

3.2.5 Clock Recovery ........................................................................................3-3

ADMtek Inc. V1.13

3.2.6 Stream Cipher Scrambler/ De-scrambler................................................3-3

3.2.7 Encoder/Decoder.....................................................................................3-3

3.3 SWITCH ENGINE.................................................................................................... 3-4

3.3.1 Hashing Function.....................................................................................3-4

3.3.2 Learning Process.....................................................................................3-4

3.3.3 Routing.....................................................................................................3-4

3.3.4 Forwarding..............................................................................................3-4

3.3.5 Buffer Management..................................................................................3-5

3.3.6 Flow Control (Patent Pending) ...............................................................3-5

3.3.7 Full Duplex ..............................................................................................3-5

3.3.8 Half Duplex..............................................................................................3-5

3.3.9 Packet priority and Class of Service (CoS) .............................................3-5

3.3.10 VLAN........................................................................................................3-6

3.3.11 Address table access................................................................................3-6

3.3.12 Address security.......................................................................................3-6

3.3.13 Bandwidth control function......................................................................3-7

3.3.14 Send descriptors content..........................................................................3-7

3.3.15 Receive descriptors content .....................................................................3-8

3.4 USB 1.1 HOST CONTROLLER.............................................................................. 3-10

3.4.1 Block Diagram.......................................................................................3-10

3.4.2 System bus interface...............................................................................3-10

3.4.3 Operational Register..............................................................................3-10

3.4.4 SIE..........................................................................................................3-11

3.4.5 DPLL......................................................................................................3-11

3.4.6 Memory BIST.........................................................................................3-11

3.5 DMA OPERATION............................................................................................... 3-11

3.5.1 Endpoint Descriptor Format..................................................................3-11

3.5.2 Transfer Descriptor Format ..................................................................3-12

3.5.3 DMA operation ......................................................................................3-14

CHAPTER 4 REGISTER DESCRIPTION ................................................................4-1

4.1 SYSTEM MEMORY MAP ........................................................................................ 4-1

4.2 SYSTEM AND INTERRUPT REGISTERS .................................................................... 4-1

4.2.1 Interrupt Control Register Map...............................................................4-1

4.2.2. Interrupt Request Source Description .....................................................4-1

4.2.3 IRQ_status, offset: 0x00...........................................................................4-1

4.2.4 IRQ_raw_status, offset: 0x40...................................................................4-2

4.2.5 IRQ_enable, offset: 0x80 .........................................................................4-2

4.2.6 IRQ_enable_clear, offset: 0xc0 ...............................................................4-2

4.2.7 Reserved, offset: 0x10..............................................................................4-2

4.2.8 INT_Mode, offset: 0x14 ...........................................................................4-2

4.2.9 FIQ_status, offset: 0x18...........................................................................4-3

4.2.10 IRQ_test_source, offset: 0x1c..................................................................4-3

4.2.11 IRQ_source_sel, offset: 0x20...................................................................4-3

4.2.12 INT_level, offset: 0x24.............................................................................4-3

4.3 SWITCH CONTROL REGISTER MAP........................................................................ 4-4

ADM5120 ii

4.4 SWITCH CONTROL REGISTER DESCRIPTION .......................................................... 4-5

ADMtek Inc. V1.13

4.4.1 Code, offset: 0x00 ....................................................................................4-5

4.4.2 SftReset, offset: 0x04................................................................................4-6

Note: Whenever you write the register offset 0x04, the SftReset will be active.......4-6

4.4.3 Boot_done, offset: 0x08 ...........................................................................4-6

4.4.3 SWReset, offset: 0x0c...............................................................................4-6

4.4.5 Global_St, offset: 0x10.............................................................................4-6

4.4.6 PHY_St, offset: 0x14................................................................................4-7

4.4.7 Port_St, offset: 0x18.................................................................................4-7

4.4.8 Mem_control, offset: 0x1c .......................................................................4-8

4.4.9 SW_conf, offset: 0x20...............................................................................4-8

4.4.10 CPUp_conf, offset 0x24.........................................................................4-10

4.4.11 Port_conf0, offset 0x28..........................................................................4-10

4.4.12 Port_conf1, offset 0x2c ..........................................................................4-11

4.4.13 Port_conf2, offset 0x30..........................................................................4-11

4.4.14 Reserved, offset: 0x34............................................................................4-12

4.4.15 Reserved, offset: 0x38............................................................................4-12

4.4.16 Reserved, offset: 0x3c ............................................................................4-13

4.4.17 VLAN_GI, offset 0x40............................................................................4-13

4.4.18 VLAN_GII, offset 0x44...........................................................................4-13

4.4.19 Send_trig, offset 0x48.............................................................................4-13

4.4.20 Srch_cmd, offset 0x4c ............................................................................4-13

4.4.21 ADDR_st0, offset 0x50...........................................................................4-14

4.4.22 ADDR_st1, offset 0x54...........................................................................4-14

4.4.23 MAC_wt0, offset 0x58............................................................................4-14

4.4.24 MAC_wt1, offset 0x5c............................................................................4-14

4.4.25 BW_cntl0, offset 0x60 ............................................................................4-15

4.4.26 BW_cntl1, offset 0x64 ............................................................................4-15

4.4.27 PHY_cntl0, offset 0x68...........................................................................4-15

4.4.28 PHY_cntl1, offset 0x6c...........................................................................4-16

4.4.29 FC_th, offset 0x70..................................................................................4-16

4.4.30 adj_port_th, offset 0x74.........................................................................4-16

4.4.31 Port_th, offset 0x78................................................................................4-16

4.4.32 PHY_cntl2, offset 0x7c...........................................................................4-16

4.4.33 PHY_cntl3, offset 0x80...........................................................................4-17

4.4.34 Pri_cntl, offset 0x84...............................................................................4-17

4.4.35 VLAN_pri, offset 0x88............................................................................4-17

4.4.36 TOS_en, offset 0x8c ...............................................................................4-18

4.4.37 TOS_map0, offset 0x90..........................................................................4-18

4.4.38 TOS_map1, offset 0x94..........................................................................4-18

4.4.39 Custom_pri1, offset 0x98.......................................................................4-18

4.4.40 Custom_pri2, offset 0x9c .......................................................................4-18

4.4.41 PHY_cntl4, offset 0xA0..........................................................................4-19

4.4.42 Empty_cnt, offset 0xA4...........................................................................4-19

4.4.43 Port_cnt_sel, offset 0xA8.......................................................................4-19

4.4.44 Port_cnt, offset 0xAc..............................................................................4-19

ADM5120 iii

4.4.45 Int_st, offset 0xB0...................................................................................4-20

ADMtek Inc. V1.13

4.4.46 Int_mask, offset 0xB4.............................................................................4-21

4.4.47 GPIO_conf0, offset 0xB8.......................................................................4-22

4.4.48 GPIO_conf2, offset 0xBc .......................................................................4-22

4.4.49 Watchdog0, offset 0xC0.........................................................................4-22

4.4.50 Watchdog1, offset 0xC4.........................................................................4-22

4.4.51 Swap_in, offset 0xC8..............................................................................4-23

4.4.52 Swap_out, offset 0xCc............................................................................4-23

4.4.53 send_Hbaddr, offset 0xD0 .....................................................................4-23

4.4.54 send_Lbaddr, offset 0xD4......................................................................4-23

4.4.55 receive_Hbaddr, offset 0xD8.................................................................4-23

4.4.56 receive_Lbaddr, offset 0xDc..................................................................4-24

4.4.57 send_Hwaddr, offset 0xE0.....................................................................4-24

4.4.58 send_Lwaddr, offset 0xE4......................................................................4-24

4.4.59 receive_Hwaddr, offset 0xE8.................................................................4-24

4.4.60 receive_Lwaddr, offset 0xEc..................................................................4-24

4.4.61 Timer_int, offset 0xF0............................................................................4-24

4.4.62 Timer, offset 0xF4..................................................................................4-25

4.4.63 Reserved, offset 0xF8.............................................................................4-25

4.4.64 Reserved, offset 0xFc.............................................................................4-25

4.4.65 port0_LED, offset 0x100........................................................................4-25

4.4.66 port1_LED, offset 0x104........................................................................4-25

4.4.67 port2_LED, offset 0x108........................................................................4-25

4.4.68 port3_LED, offset 0x10c........................................................................4-26

4.4.69 port4_LED, offset 0x110........................................................................4-26

4.5 USB CONTROL STATUS REGISTER MAP ............................................................. 4-26

4.6 USB CONTROL STATUS REGISTERS DESCRIPTION.............................................. 4-27

4.6.1 General Control , offset 0x00.................................................................4-27

4.6.2 Interrupt Status, offset 0x04...................................................................4-27

4.6.3 Interrupt Enable, offset 0x08 .................................................................4-28

4.6.4 Reserved, offset 0x0C.............................................................................4-28

4.6.5 Host General Control, offset 0x10.........................................................4-29

4.6.6 Reserved, offset 0x14 .............................................................................4-29

4.6.7 SOF Frame interval, offset 0x18............................................................4-29

4.6.8 SOF Frame number, offset 0x1C...........................................................4-30

4.6.9 Reserved, offset 0x20 – 0x6C.................................................................4-30

4.6.10 Low speed threshold, offset 0x70...........................................................4-30

4.6.11 RH descriptor, offset 0x74 .....................................................................4-31

4.6.12 Port x status, offset 0x78........................................................................4-33

4.6.13 Host Descriptor Head Starting Address, offset 0x80.............................4-36

4.7 MPMC REGISTERS ............................................................................................. 4-36

4.7.1 MPMC Registers Summary....................................................................4-36

4.7.2 MPMC Control register, offset 000h.....................................................4-38

4.7.3 MPMC Status register, offset 004h........................................................4-38

4.7.4 MPMC Config register, offset 008h.......................................................4-39

4.7.5 MPMC Dynamic Control register, offset 020h......................................4-39

ADM5120 iv

4.7.6 MPMC Dynamic Refresh register, offset 024h......................................4-40

ADMtek Inc. V1.13

4.7.7 MPMC Dynamic RP register, offset 030h .............................................4-40

4.7.8 MPMC Dynamic RAS register, offset 034h ...........................................4-41

4.7.9 MPMC Dynamic SREX register, offset 038h.........................................4-41

4.7.10 MPMC Dynamic APR register, offset 03Ch..........................................4-41

4.7.11 MPMC Dynamic DAL register, offset 040h...........................................4-41

4.7.12 MPMC Dynamic WR register, offset 044h ............................................4-41

4.7.13 MPMC Dynamic RC register, offset 048h.............................................4-42

4.7.14 MPMC Dynamic RFC register, offset 04Ch..........................................4-42

4.7.15 MPMC Dynamic XSR register, offset 050h ...........................................4-42

4.7.16 MPMC Dynamic RRD register, offset 054h ..........................................4-42

4.7.17 MPMC Dynamic MRD register, offset 058h..........................................4-42

4.7.18 MPMC Static Extended Wait register, offset 080h................................4-43

4.7.19 MPMC Dynamic Config [0,1,2,3] register............................................4-43

4.7.20 MPMC Dynamic Ras Cas[0,1,2,3] register...........................................4-46

4.7.21 MPMC Static Config[0,1,2,3] register..................................................4-46

4.7.22 MPMC Static Wait Wen [0,1,2,3] register ............................................4-47

4.7.23 MPMC Static Wait Oen[0,1,2,3] register..............................................4-47

4.7.24 MPMC Static Wait Rd [0,1,2,3] register...............................................4-48

4.7.25 MPMC Static Wait Page [0,1,2,3] register ...........................................4-48

4.7.26 MPMC Static Wait Wr [0,1,2,3] register...............................................4-48

4.7.27 MPMC Static Wait Turn [0,1,2,3] register............................................4-49

4.7.28 Conceptual MPMC Additional Peripheral ID register .........................4-49

4.7.29 MPMC PeriphID4 register, offset FD0h...............................................4-49

4.7.30 MPMC PeriphID5-7 register, offset FD4h, FD8h, FDCh....................4-50

4.7.31 Conceptual MPMC Peripheral ID register ...........................................4-50

4.7.32 MPMC PeriphID0 register, offset FE0h................................................4-50

4.7.33 MPMCPeriphID1 register, offset FE4h.................................................4-50

4.7.34 MPMC PeriphID2 register, offset FE8h................................................4-50

4.7.35 MPMC PeriphID3 register, offset FECh...............................................4-51

4.7.36 MPMC PrimeCellID register, offset 00h...............................................4-51

4.7.37 MPMC PCellID0 register, offset FF0h .................................................4-51

4.7.38 MPMC PCellID1 register, offset FF4h .................................................4-52

4.7.39 MPMCPCellID2 register, offset FF8h ..................................................4-52

4.7.40 MPMCPCellID3 register, offset FFCh..................................................4-52

4.8 UART REGISTERS .............................................................................................. 4-52

4.8.1 Remap and Pause Controller Registers.................................................4-52

4.8.2 UART data register, offset 00h ..............................................................4-52

4.8.3 UART receive status register/error clear register, offset 04h...............4-53

4.8.4 UART line control register, high byte, offset 08h..................................4-53

4.8.5 UART line control register, middle byte, offset 0ch...............................4-54

4.8.6 UART line control register, low byte, offset 10h ...................................4-54

4.8.7 UART control register (UARTCR), offset 14h.......................................4-54

4.8.8 UART flag register (UARTFR), offset 18h.............................................4-55

4.8.9 UARTIIR/UARTICR, offset 1ch .............................................................4-57

CHAPTER 5 ELECTRICAL SPECIFICATION.......................................................5-1

ADM5120 v

5.1 ABSOLUTE MAXIMUM RATINGS ........................................................................... 5-1

ADMtek Inc. V1.13

5.2 DC SPECIFICATIONS ............................................................................................. 5-1

5.3 AC TIMING ................................................................................................................. 5-2

5.3.1 SDRAM interface.....................................................................................5-2

5.3.2 Memory Bus Read Timing........................................................................5-5

5.3.3 Memory Bus Write Timing.......................................................................5-6

CHAPTER 6 PACKAGING.........................................................................................6-1

6.1 BALL GRID ARRAY (BGA) 324-PIN...................................................................... 6-1

ADM5120 vi

6.2 PLASTIC QUAD FLAT PACK (PQFP) 208-PIN ........................................................ 6-2

ADMtek Inc. V1.13

List of Figures

Figure 1-1 ADM5120 Block Diagram............................................................................. 1-3

Figure 3-1 Block Diagram of ADMtek USB 1.1 Host controller.................................. 3-10

Figure 3-2 DMA Operation in Host mode..................................................................... 3-15

Figure 3-3 Interrupt IN/OUT Transactions.................................................................... 3-17

Figure 4-1 System Memory Map..................................................................................... 4-1

Figure 5-1 Precharge Command ...................................................................................... 5-2

Figure 5-2 Active Command ........................................................................................... 5-3

Figure 5-3 Write Command.............................................................................................5-4

Figure 5-4 Read Command.............................................................................................. 5-4

List of Tables

Table 2-1 ADM5120 324 BGA Pin Assignment............................................................. 2-2

Table 2-2 ADM5120 208PQFP Pin Assignments ........................................................... 2-3

Table 2-3 LED Program Table ........................................................................................ 2-6

Table 4-1 MPMC Registers Summary........................................................................... 4-36

Table 4-2 Address map .................................................................................................. 4-44

ADM5120 ii

Table 4-3 Remap and Pause Controller Registers Summary......................................... 4-52

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