ADLINK Technology PCIe-7300A Manual de usuario
Advance Technologies; Automate the World.
Manual Rev. 2.50
Revision Date: July 1, 2008
Part No: 50-11106-1030
PCI/PCIe/cPCI-7300A
80 MB Ultra-High Speed 32-CH
Digital I/O Boards
User’s Manual
Copyright 2008 ADLINK TECHNOLOGY INC.
All Rights Reserved.
The information in this document is subject to change without prior
notice in order to improve reliability, design, and function and does
not represent a commitment on the part of the manufacturer.
In no event will the manufacturer be liable for direct, indirect, spe-
cial, incidental, or consequential damages arising out of the use or
inability to use the product or documentation, even if advised of
the possibility of such damages.
This document contains proprietary information protected by copy-
right. All rights are reserved. No part of this manual may be repro-
duced by any mechanical, electronic, or other means in any form
without prior written permission of the manufacturer.
Trademarks
NuDAQ, NuIPC, DAQBench are registered trademarks of ADLINK
TECHNOLOGY INC.
Product names mentioned herein are used for identification pur-
poses only and may be trademarks and/or registered trademarks
of their respective companies.
Getting Service from ADLINK
Customer Satisfaction is top priority for ADLINK Technology Inc.
Please contact us should you require any service or assistance.
ADLINK TECHNOLOGY INC.
Web Site: http://www.adlinktech.com
TEL: +886-2-82265877
FAX: +886-2-82265717
Address: 9F, No. 166, Jian Yi Road, Chungho City,
Taipei, 235 Taiwan
Please email or FAX this completed service form for prompt and
satisfactory service.
Company Information
Company/Organization
Contact Person
E-mail Address
Address
Country
TEL FAX:
Web Site Product Information
Product Model
Environment OS:
M/B: CPU:
Chipset: BIOS:
Please give a detailed description of the problem(s):
i
Table of Contents
List of Tables.......................................................................... iv
List of Figures......................................................................... v
1 Introduction ........................................................................ 1
1.1 Applications ......................................................................... 2
1.2 Features............................................................................... 2
1.3 Specifications....................................................................... 3
1.4 Software Support................................................................. 6
Programming Library ......................................................6
DAQ-LVIEW PnP: LabVIEW® Driver .............................6
PCIS-VEE: HP-VEE Driver .............................................7
DAQBenchTM: ActiveX Controls ....................................7
2 Installation .......................................................................... 9
2.1 What You Have.................................................................... 9
2.2 Unpacking.......................................................................... 10
2.3 Device Installation for Windows Systems.......................... 10
2.4 cPCI/PCI/PCIe-7300A Layout............................................ 11
2.5 Hardware Installation Outline............................................. 13
2.6 Connector Pin Assignment ................................................ 14
2.7 Wiring and Termination..................................................... 17
2.8 Termination Board Support................................................ 18
Connect with DIN-100S ................................................18
Connect with DIN-502S ................................................18
3 Registers........................................................................... 19
3.1 I/O Port Base Address....................................................... 20
3.2 DI_CSR: DI Control & Status Register .............................. 22
3.3 DO_CSR: DO Control & Status Register........................... 24
3.4 Auxiliary Digital I/O Register.............................................. 26
3.5 INT_CSR: Interrupt Control and Status Register............... 27
3.6 DI_FIFO: DI FIFO direct access port................................. 28
3.7 DO_FIFO: DO external data FIFO direct access port........ 29
3.8 FIFO_CR: FIFO almost empty/full register........................ 30
3.9 POL_CNTRL: Control Signal Polarity Control Register..... 31
3.10 PLX PCI-9080 DMA Control Registers.............................. 32
ii
4 Operation Theory.............................................................. 33
4.1 I/O Configuration................................................................ 34
4.2 Block Diagram.................................................................... 35
4.3 Digital I/O Data Flow.......................................................... 36
4.4 Input FIFO and Output FIFO.............................................. 37
4.5 Bus-mastering DMA........................................................... 38
4.6 Scatter/gather DMA ........................................................... 40
4.7 Clocking Mode................................................................... 41
4.8 Starting Mode..................................................................... 43
4.9 Active Terminator............................................................... 44
4.10 Digital Input Operation Mode............................................. 45
Digital Input DMA in Internal Clock Mode .....................45
Digital Input DMA in External Clock Mode ....................47
Digital Input DMA in Handshaking Mode ......................49
Continuous Digital Input ................................................51
4.11 Digital Output Operation Mode .......................................... 53
Digital Output DMA in Internal Clock Mode ..................53
Digital Output DMA in Handshaking Mode ...................54
Digital Output DMA in Burst Handshaking Mode ..........56
Pattern Generator .........................................................59
4.12 Auxiliary DIO...................................................................... 60
5 C/C++ Libraries ................................................................. 61
5.1 Libraries Installation........................................................... 62
5.2 Programming Guide........................................................... 63
5.3 _7300_Initial ...................................................................... 64
5.4 _7300_Close...................................................................... 66
5.5 _7300_Configure ............................................................... 67
5.6 _7300_DI_Mode ................................................................ 69
5.7 _7300_DO_Mode............................................................... 70
5.8 _7300_AUX_DI.................................................................. 72
5.9 _7300_AUX_DI_Channel................................................... 73
5.10 _7300_AUX_DO................................................................ 74
5.11 _7300_AUX_DO_Channel................................................. 75
5.12 _7300_Alloc_DMA_Mem................................................... 76
5.13 _7300_Free_DMA_Mem.................................................... 77
5.14 _7300_DI_DMA_Start........................................................ 78
5.15 _7300_DI_DMA_Status..................................................... 82
5.16 _7300_DI_DMA_Abort....................................................... 83
5.17 _7300_GetOverrunStatus.................................................. 84
iii
5.18 _7300_DO_DMA_Start...................................................... 85
5.19 _7300_DO_DMA_Status ................................................... 87
5.20 _7300_DO_DMA_Abort..................................................... 88
5.21 _7300_DO_PG_Start......................................................... 89
5.22 _7300_DO_PG_Stop......................................................... 91
5.23 _7300_DI_Timer................................................................ 92
5.24 _7300_DO_Timer.............................................................. 93
5.25 _7300_Int_Timer................................................................ 94
5.26 _7300_Get_Sample........................................................... 95
5.27 _7300_Set_Sample........................................................... 96
5.28 _7300_GetUnderrunStatus................................................ 97
Appendix................................................................................ 99
The Intel (NEC) 8254 ....................................................99
The Control Byte ...........................................................99
Mode Definition ...........................................................101
iv List of Tables
List of Tables
Table 2-1: Connector Pin Assignment ..................................... 14
Table 3-1: I/O Port Base Address ............................................ 20
Table 4-1: I/O Configuration ..................................................... 34
Table 5-1: Data Types ............................................................. 63
List of Figures v
List of Figures
Figure 2-1: PCI-7300A Layout Diagram..................................... 11
Figure 2-2: cPCI-7300A Layout Diagram................................... 12
Figure 2-3: PCIe-7300A Layout Diagram................................... 12
Figure 2-4: CN1 Pin Assignment ............................................... 16
Figure 4-1: Block diagram.......................................................... 35
Figure 4-2: Data flow of digital input .......................................... 36
Figure 4-3: Data flow of digital output........................................ 36
Figure 4-4: Maximum data throughput....................................... 38
Figure 4-5: Scatter/gather DMA for digital output ...................... 40
Figure 4-6: Timer configuration.................................................. 41
Figure 4-7: DIREQ as input data strobe (Rising Edge Active)... 48
Figure 4-8: DIREQ as input data strobe (Falling Edge Active) .. 49
Figure 4-9: DIREQ & DIACK Handshaking................................ 51
Figure 4-10: DOREQ as output data strobe................................. 54
Figure 4-11: DOREQ & DOACK Handshaking............................ 56
vi List of Figures
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