AVME9440/9443/9447 ISOLATED DIGITAL I/O BOARDS
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TABLE OF CONTENTS
CHAPTER
Page
1.0 GENERAL INFORMATION...................................................................................................... 4
1.1 INTRODUCTION...................................................................................................................... 4
1.2 DIGITAL INPUT FEATURES ( 9440-I & 9447-I )...................................................................... 4
1.3 DIGITAL OUTPUT FEATURES ( 9440-I & 9443-I ).................................................................. 4
1.4 VMEbus INTERFACE FEATURES........................................................................................... 5
1.5 FIELD COMPATIBILITY........................................................................................................... 5
1.5.1 Digital Inputs..................................................................................................................... 5
1.5.2 Digital Outputs.................................................................................................................. 5
2.0 PREPARATION FOR USE....................................................................................................... 5
2.1 UNPACKING AND INSPECTION............................................................................................. 5
2.2 CARD CAGE CONSIDERATIONS........................................................................................... 6
2.3 BOARD CONFIGURATION...................................................................................................... 6
2.3.1 Default Jumper Configuration........................................................................................... 6
2.3.1.1 Digital Input Default Configuration.......................................................................... 6
2.3.1.2 Digital Output Default Configuration....................................................................... 6
2.4 VMEbus CONFIGURATION.................................................................................................... 7
2.4.1 Address Decode Jumper Configuration........................................................................... 7
2.4.2 Address Modifier Jumper Configuration........................................................................... 8
2.4.3 Interrupt Level Select Jumper Configuration.................................................................... 8
2.5 DIGITAL INPUT CONFIGURATION ( 9440-I & 9447-I ) ......................................................... 8
2.5.1 Digital Input Threshold Detection..................................................................................... 9
2.5.2 Sensing Contact Closures and Switches......................................................................... 9
2.5.3 Debounce Delay Selection............................................................................................... 9
2.6 DIGITAL OUTPUT CONFIGURATION ( 9440-I & 9443-I ) ..................................................... 9
2.6.1 Relay Coils and Other Inductive Loads............................................................................ 9
2.7 DIGITAL INPUT/OUTPUT INTERFACE TO TTL AND CMOS SIGNALS................................ 10
2.8 CONNECTORS........................................................................................................................ 10
2.8.1 Digital Input Connector..................................................................................................... 10
2.8.2 Digital Output Connector.................................................................................................. 11
2.8.3 VMEbus Connections....................................................................................................... 11
2.9 POWER-UP TIMING AND LOADING...................................................................................... 12
2.10 DATA TRANSFER TIMING..................................................................................................... 13
2.11 FIELD GROUNDING CONSIDERATIONS.............................................................................. 13
3.0 PROGRAMMING INFORMATION........................................................................................... 13
3.1 MEMORY MAP......................................................................................................................... 13
3.1.1 Board Identification PROM............................................................................................... 15
3.1.2 Board Status Register....................................................................................................... 16
3.1.2.1 Status Bits Usage.................................................................................................... 16
3.1.3 Interrupt Vector Registers................................................................................................. 17
3.1.4 Digital Input Channel Interrupt Status Register................................................................. 17
3.1.5 Digital Input Channel Interrupt Enable Register................................................................ 18
3.1.6 Digital Input Channel Interrupt Polarity Register............................................................... 18
3.1.7 Digital Input Channel Interrupt Type Select Register........................................................ 18
3.1.8 Digital Input Channel Interrupt Pattern Enable Register................................................... 19
3.1.9 Digital Input Channel Data Register.................................................................................. 19
3.1.10 Digital Output Channel Data Register.............................................................................. 19
3.2 GENERAL PROGRAMMING CONSIDERATIONS.................................................................. 20
3.2.1 Board Diagnostics............................................................................................................. 20
