Xilinx MultiLINX Series Manual de instalación
Hardware User Guide
Hardware User Guide
Xilinx Development System
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The Xilinx logo shown above is a registered trademark of Xilinx, Inc.
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TRACE, XACT, XILINX, XC2064, XC3090, XC4005, XC5210, and XC-DS501 are registered trademarks of Xilinx,
Inc.
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All XC-prefix product designations, A.K.A Speed, Alliance Series, AllianceCORE, BITA, CLC, Configurable Logic
Cell, CoolRunner, CORE Generator, CoreLINX, Dual Block, EZTag, FastCLK, FastCONNECT, FastFLASH,
FastMap, Fast Zero Power, Foundation, HardWire, IRL, LCA, LogiBLOX, Logic Cell, LogiCORE, LogicProfessor,
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service marks of Xilinx, Inc.
All other trademarks are the property of their respective owners.
Xilinx, Inc. does not assume any liability arising out of the application or use of any product described or shown
herein; nor does it convey any license under its patents, copyrights, or maskwork rights or any rights of others.
Xilinx, Inc. reserves the right to make changes, at any time, in order to improve reliability, function or design and
to supply the best product possible. Xilinx, Inc. will not assume responsibility for the use of any circuitry described
herein other than circuitry entirely embodied in its products. Xilinx, Inc. devices and products are protected under
one or more of the following U.S. Patents: 4,642,487; 4,695,740; 4,706,216; 4,713,557; 4,746,822; 4,750,155;
4,758,985; 4,820,937; 4,821,233; 4,835,418; 4,855,619; 4,855,669; 4,902,910; 4,940,909; 4,967,107; 5,012,135;
5,023,606; 5,028,821; 5,047,710; 5,068,603; 5,140,193; 5,148,390; 5,155,432; 5,166,858; 5,224,056; 5,243,238;
5,245,277; 5,267,187; 5,291,079; 5,295,090; 5,302,866; 5,319,252; 5,319,254; 5,321,704; 5,329,174; 5,329,181;
5,331,220; 5,331,226; 5,332,929; 5,337,255; 5,343,406; 5,349,248; 5,349,249; 5,349,250; 5,349,691; 5,357,153;
5,360,747; 5,361,229; 5,362,999; 5,365,125; 5,367,207; 5,386,154; 5,394,104; 5,399,924; 5,399,925; 5,410,189;
5,410,194; 5,414,377; 5,422,833; 5,426,378; 5,426,379; 5,430,687; 5,432,719; 5,448,181; 5,448,493; 5,450,021;
5,450,022; 5,453,706; 5,455,525; 5,466,117; 5,469,003; 5,475,253; 5,477,414; 5,481,206; 5,483,478; 5,486,707;
5,486,776; 5,488,316; 5,489,858; 5,489,866; 5,491,353; 5,495,196; 5,498,979; 5,498,989; 5,499,192; 5,500,608;
5,500,609; 5,502,000; 5,502,440; 5,504,439; 5,506,518; 5,506,523; 5,506,878; 5,513,124; 5,517,135; 5,521,835;
5,521,837; 5,523,963; 5,523,971; 5,524,097; 5,526,322; 5,528,169; 5,528,176; 5,530,378; 5,530,384; 5,546,018;
5,550,839; 5,550,843; 5,552,722; 5,553,001; 5,559,751; 5,561,367; 5,561,629; 5,561,631; 5,563,527; 5,563,528;
5,563,529; 5,563,827; 5,565,792; 5,566,123; 5,570,051; 5,574,634; 5,574,655; 5,578,946; 5,581,198; 5,581,199;
5,581,738; 5,583,450; 5,583,452; 5,592,105; 5,594,367; 5,598,424; 5,600,263; 5,600,264; 5,600,271; 5,600,597;
5,608,342; 5,610,536; 5,610,790; 5,610,829; 5,612,633; 5,617,021; 5,617,041; 5,617,327; 5,617,573; 5,623,387;
5,627,480; 5,629,637; 5,629,886; 5,631,577; 5,631,583; 5,635,851; 5,636,368; 5,640,106; 5,642,058; 5,646,545;
5,646,547; 5,646,564; 5,646,903; 5,648,732; 5,648,913; 5,650,672; 5,650,946; 5,652,904; 5,654,631; 5,656,950;
5,657,290; 5,659,484; 5,661,660; 5,661,685; 5,670,896; 5,670,897; 5,672,966; 5,673,198; 5,675,262; 5,675,270;
5,675,589; 5,677,638; 5,682,107; 5,689,133; 5,689,516; 5,691,907; 5,691,912; 5,694,047; 5,694,056; 5,724,276;
5,694,399; 5,696,454; 5,701,091; 5,701,441; 5,703,759; 5,705,932; 5,705,938; 5,708,597; 5,712,579; 5,715,197;
5,717,340; 5,719,506; 5,719,507; 5,724,276; 5,726,484; 5,726,584; 5,734,866; 5,734,868; 5,737,234; 5,737,235;
Hardware User Guide
Xilinx Development System
5,737,631; 5,742,178; 5,742,531; 5,744,974; 5,744,979; 5,744,995; 5,748,942; 5,748,979; 5,752,006; 5,752,035;
5,754,459; 5,758,192; 5,760,603; 5,760,604; 5,760,607; 5,761,483; 5,764,076; 5,764,534; 5,764,564; 5,768,179;
5,770,951; 5,773,993; 5,778,439; 5,781,756; 5,784,313; 5,784,577; 5,786,240; 5,787,007; 5,789,938; 5,790,479;
5,790,882; 5,795,068; 5,796,269; 5,798,656; 5,801,546; 5,801,547; 5,801,548; 5,811,985; 5,815,004; 5,815,016;
5,815,404; 5,815,405; 5,818,255; 5,818,730; 5,821,772; 5,821,774; 5,825,202; 5,825,662; 5,825,787; 5,828,230;
5,828,231; 5,828,236; 5,828,608; 5,831,448; 5,831,460; 5,831,845; 5,831,907; 5,835,402; 5,838,167; 5,838,901;
5,838,954; 5,841,296; 5,841,867; 5,844,422; 5,844,424; 5,844,829; 5,844,844; 5,847,577; 5,847,579; 5,847,580;
5,847,993; 5,852,323; 5,861,761; 5,862,082; 5,867,396; 5,870,309; 5,870,327; 5,870,586; 5,874,834; 5,875,111;
5,877,632; 5,877,979; 5,880,492; 5,880,598; 5,880,620; 5,883,525; 5,886,538; 5,889,411; 5,889,413; 5,889,701;
5,892,681; 5,892,961; 5,894,420; 5,896,047; 5,896,329; 5,898,319; 5,898,320; 5,898,602; 5,898,618; 5,898,893;
5,907,245; 5,907,248; 5,909,125; 5,909,453; 5,910,732; 5,912,937; 5,914,514; 5,914,616; 5,920,201; 5,920,202;
5,920,223; 5,923,185; 5,923,602; 5,923,614; 5,928,338; 5,931,962; 5,933,023; 5,933,025; 5,933,369; 5,936,415;
5,936,424; 5,939,930; 5,942,913; 5,944,813; 5,945,837; 5,946,478; 5,949,690; 5,949,712; 5,949,983; 5,949,987;
5,952,839; 5,952,846; 5,955,888; 5,956,748; 5,958,026; 5,959,821; 5,959,881; 5,959,885; 5,961,576; 5,962,881;
5,963,048; 5,963,050; 5,969,539; 5,969,543; 5,970,142; 5,970,372; 5,971,595; 5,973,506; 5,978,260; 5,986,958;
5,990,704; 5,991,523; 5,991,788; 5,991,880; 5,991,908; 5,995,419; 5,995,744; 5,995,988; 5,999,014; 5,999,025;
6,002,282; and 6,002,991; Re. 34,363, Re. 34,444, and Re. 34,808. Other U.S. and foreign patents pending.
Xilinx, Inc. does not represent that devices shown or products described herein are free from patent infringement
or from any other third party right. Xilinx, Inc. assumes no obligation to correct any errors contained herein or to
advise any user of this text of any correction if such be made. Xilinx, Inc. will not assume any liability for the
accuracy or correctness of any engineering or software support or assistance provided to a user.
Xilinx products are not intended for use in life support appliances, devices, or systems. Use of a Xilinx product in
such applications without the written consent of the appropriate Xilinx officer is prohibited.
Copyright 1991-2000 Xilinx, Inc. All Rights Reserved.
Hardware User Guide — 3.1i i
About This Manual
This manual describes the function and operation of Xilinx hardware
devices, which include the following.
•Cables for downloading designs
•MultiLINX™ Cable specific information
•FPGA Design Demonstration board for design verification
•CPLD Design Demonstration board for design verification
Before using this manual, you should be familiar with the operations
that are common to all Xilinx software tools: how to bring up the
system, select a tool for use, specify operations, and manage design
data. These topics are covered in the 2.1i Quick Start Guide.Other
publications you can consult for related information are the Hardware
Debugger Guide and the JTAG Programmer Guide.
Manual Contents
This manual covers the following topics.
•Chapter 1, “Cable Hardware”provides specific information about
using the MultiLINX™ Cable, Parallel Cable III and XChecker™
cables to configure CPLDs and FPGAs.
•Chapter 2, “MutliLINX™Cable”provides detailed information
about the MultiLINX Cable, Flying Wires and Operation Modes.
•Chapter 3, “FPGA Design Demonstration Board”describes the
function and operation of the FPGA Demonstration Board.
Hardware User Guide
ii Xilinx Development System
•Chapter 4, “CPLD Design Demonstration Board”describes the
function and operation of this board, which is used for demon-
strating the In-system Programming (ISP) capabilities of the
XC9500 CPLD family.
•“Glossary”defines all the terms you should understand to use
Xilinx Hardware.
Additional Resources
For additional information, go to http://support.xilinx.com.
The following table lists some of the resources you can access from
this Web site. You can also directly access these resources using the
provided URLs.
Resource Description/URL
Tutorials Tutorials covering Xilinx design flows, from design entry to verification
and debugging
http://support.xilinx.com/support/techsup/tutorials/
index.htm
Answers
Database Current listing of solution records for the Xilinx software tools
Search this database using the search function at
http://support.xilinx.com/support/searchtd.htm
Application
Notes Descriptions of device-specific design techniques and approaches
http://support.xilinx.com/apps/appsweb.htm
Data Book Pages from The Programmable Logic Data Book, which contain device-
specific information on Xilinx device characteristics, including readback,
boundary scan, configuration, length count, and debugging
http://support.xilinx.com/partinfo/databook.htm
Xcell Journals Quarterly journals for Xilinx programmable logic users
http://support.xilinx.com/xcell/xcell.htm
Technical Tips Latest news, design tips, and patch information for the Xilinx design
environment
http://support.xilinx.com/support/techsup/journals/
index.htm
Hardware User Guide — 3.1i iii
Conventions
This manual uses the following conventions. An example illustrates
each convention.
Typographical
The following conventions are used for all documents.
•Courier font indicates messages, prompts, and program files
that the system displays.
speed grade: - 100
•Courier bold indicates literal commands that you enter in a
syntactical statement. However, braces “{ }” in Courier bold are
not literal and square brackets “[ ]” in Courier bold are literal
only in the case of bus specifications, such as bus [7:0].
rpt_del_net=
Courier bold alsoindicatescommandsthatyouselectfroma
menu.
File →Open
•Italic font denotes the following items.
♦Variables in a syntax statement for which you must supply
values
edif2ngd design_name
♦References to other manuals
Hardware User Guide
iv Xilinx Development System
See the Development System Reference Guide for more informa-
tion.
♦Emphasis in text
If a wire is drawn so that it overlaps the pin of a symbol, the
two nets are not connected.
•Square brackets “[ ]” indicate an optional entry or parameter.
However, in bus specifications, such as bus [7:0], they are
required.
edif2ngd [option_name] design_name
•Braces “{ }” enclose a list of items from which you must choose
one or more.
lowpwr ={on|off}
•A vertical bar “|” separates items in a list of choices.
lowpwr ={on|off}
•A vertical ellipsis indicates repetitive material that has been
omitted.
IOB #1: Name = QOUT’
IOB #2: Name = CLKIN’
.
.
.
•A horizontal ellipsis “….” indicates that an item can be repeated
one or more times.
allow block block_name loc1 loc2locn;
Online Document
The following conventions are used for online documents.
•Red-underlined text indicates an interbook link, which is a cross-
reference to another book. Click the red-underlined text to open
the specified cross-reference.
Hardware User Guide v
•Blue-underlined text indicates an intrabook link, which is a cross-
reference within a book. Click the blue-underlined text to open
the specified cross-reference.
Hardware User Guide
vi Xilinx Development System
Este manual sirve para los siguientes modelos
3
Tabla de contenidos
Otros manuales de Cables y conectores de Xilinx
