LIST OF FIGURES
FIGURE NO. TITLE
1.1-1 TS 2068 Block Diagram
1.1-2 Memory Configuration
1.1-3 RAM Mapping
1.1-4 System Initialization Flowchart
2.1.3-1 CPU Timing
2.1.3-2 Op Code Fetch Timing
2.1.3-3 Memory Read/Write Timing
2.1.3-4 I/O Read/Write Timing
2.1.3-5 Interrupt Request/Ack. Cycle
2.1.4-1 Rework for EPROM's
2.1.6-1 PSG Register Block Diagram
2.1.6-2 Tone Period Registers
2.1.6-3 Noise Period Register
2.1.6-4 Mixer Control -I/O Enable Reg.
2.1.6-5 D/A Converter Signal Generation
2.1.6-6 Amplitude Control Registers
2.1.6-7 Variable Amplitude Control
2.1.6-8 Envelope Period Registers
2.1.6-9 Envelope Shape/Cycle Control Reg.
2.1.6-10 Envelope Generator Output
2.1.6-11 Envelope Generator Output Detail
2.1 .7-1 Joystick Port Operation
2.1.8-1 Bank Selection Logic
2.1.8-2 Video RAM Address Generation
2.1.9-1 Keyboard Schematic
2.1.10-1 Video RAM Data Organization
2.1.11-1 Composite Video Signal
2.4.1-1 PI Mating Connector Mechanical
Requi rements
2.4.1-2 PI Signal Layout
2.4.1-3 RGB Monitor Connection Schematic
2.4.2-1 J4 Mating Connector Mechanical
Requirements
2.4.2-2 J4 Signal Layout
2.4.4-1 Joystick Connector
2.4.8-1 AC Adapter Plug
3.2.2-1 Ext. ROM Interruption Fielder
3.2.2-2 Ext. ROM Interface Routine
4.1.1-1 Keyboard Mode Control
4.1.1-2 Keyboard Support Routines
Flowcharts
4.1.2-1 Standard Character Table Locations
4.1.2-2 Screen Row/Column Designations
4.2-1 Tape Header Formats
4.3-1 Joystick Data Format
