THine CEL THCV231 Manual de usuario

THCV231_THCV236_Rev.2.30_E

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THCV231 and THCV236

SerDes transmitter and receiver with bi-directional transceiver

General Description

The THCV231 and THCV236 are designed to

support video data transmission between the host and

display.

THCV231

One high-speed lane can carry up to 14bits data at a

pixel clock frequency from 12MHz to 160MHz.

THCV236

One high-speed lane can carry up to 32bit data and

3bits of synchronizing signals at a pixel clock

frequency from 6MHz to 160MHz by converting

RGB444 to YCbCr422.

The chipset, which has one high-speed data lane,

can transmit video data up to 1080p/60Hz.

The maximum serial data rate is 4.00Gbps/lane.

Features

Data width selectable

Wide frequency range

AC coupling for high-speed lanes

CDR requires no external frequency reference

Wide range supply voltage from 1.7V to 3.6V

Additional spread spectrum on data stream

2-wire serial interface bridge function(400kbps)

Remote side GPIO control and monitoring

THCV231

QFN32 (5mm x 5mm) with exposed pad ground

THCV236

QFN64 (9mm x 9mm) with exposed pad ground

EU RoHS compliant

Block Diagram

THCV236

CDR

Controls

Formatter

YCbCr to RGB

D31-D0

HSYNC

VSYNC

CLKOUT

Settings

2-wire I/F

SDA/SCL

RXP

RXN

Deserializer

RCMP

RCMN

LVCMOS output

THCV231

LVCMOS input

PLL

Controls

Formatter

D11-D0

HSYNC

VSYNC

CLKIN

Settings

2-wire I/F

SDA/SCL

TXP

TXN

Serializer

OSC

TCMP

TCMN

LDO

OSC

LDO

CAPOUT

CAPINA

CAPINP

CAPOUT

CAPINA

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Contents Page

General Description .............................................................................................................................................. 1

Features .................................................................................................................................................................. 1

Block Diagram ....................................................................................................................................................... 1

Pin Configuration .................................................................................................................................................. 3

Pin Description ...................................................................................................................................................... 4

Functional Overview ............................................................................................................................................. 9

Functional Description .......................................................................................................................................... 9

Internal Reference Output/Input Function (CAPOUT, CAPINA, CAPINP) .............................................. 9

Power Down (PDN1, PDN0, PDN) ................................................................................................................. 10

Pre-emphasis and Drive Select Function (THCV231 only) ......................................................................... 10

Permanent Clock Output (THCV236 only) .................................................................................................. 10

Spread Spectrum Clock Generator (SSCG) .................................................................................................. 11

Hot-Plug Function ........................................................................................................................................... 13

Lock Detect Function ...................................................................................................................................... 13

Field BET Operation ....................................................................................................................................... 14

Data Width and Frequency Range Select Function ..................................................................................... 16

Data Mapping .................................................................................................................................................. 16

2-wire serial I/F Mode ..................................................................................................................................... 17

2-wire serial I/F Device ID setting ................................................................................................................ 17

2-wire serial I/F Clock Stretching ................................................................................................................. 17

Read/Write access to Sub-Link Master Register ........................................................................................... 19

Read/Write access to Sub-Link Slave Register ............................................................................................. 20

Read/Write access to remote side 2-wire serial slave devices connected to Sub-Link Slave Device ............ 22

GPIO .............................................................................................................................................................. 26

Interruption .................................................................................................................................................... 28

Register Map ........................................................................................................................................................ 29

Absolute Maximum Ratings ............................................................................................................................... 38

Recommended Operating Conditions ................................................................................................................ 38

Electrical Specification ........................................................................................................................................ 38

AC Timing Diagrams and Test Circuits ............................................................................................................ 44

PCB Layout Guideline regarding VDD andAVDD for THCV236 ................................................................. 53

Package ................................................................................................................................................................. 54

Notices and Requests ........................................................................................................................................... 56

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Pin Configuration

THCV236 (QFN 64pin)

PDN0

D27

PDN1

LFSEL

TEST1

TEST2

RF/BETOUT

COL0/INT/GPIO2

COL1/SD0

OUTSEL/SD1

TTLDRV/SD2/AIN0/GPIO1

LATEN/SD3/AIN1/GPIO0

D31

D30

D29

D28

VDD

D26

D25/GPIO4

D24/GPIO3

D23

D22

D21

D20

VDD

CLKOUT

D19

D18

D17

D16

D15

VDD

D14

D11

D12

D10

AVDD

VDD

VSYNC

HSYNC

VDD

CAPOUT

LOCKN/MSSEL

HTPDN/SUBMODE

MAINMODE/RCMN

CAPINA

RXP

RXN

BET

HFSEL/RCMP

(TOP VIEW)

65 EXPGND

D13

RXDEFSEL

PDN

TEST1

TEST2

RF/BETOUT

SDA

SCL

GPIO3

GPIO4

CLKIN

VDD

D10

VSYNC

D11

TCMN

TCMP

CAPOUT

HSYNC

CAPINA

TXP

THCV231 (QFN 32pin)

(TOP VIEW)

33 EXPGND

TXN

CAPINP

AVDD

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Pin Description

Pin Description for THCV231

Pin Name

Pin No.

Type

Description

TXP

High-Speed CML Signal Output (Main-Link)

TXN

High-Speed CML Signal Output (Main-Link)

TCMP

CML Signal Bidirectional Input/Output (Sub-Link)

TCMN

CML Signal Bidirectional Input/Output (Sub-Link)

GPIO4

GPIO4 : General Purpose Input/Output.

When GPIO4 is used as Open-Drain Output, it must be

connected with a pull-up resistor to VDD.

When GPIO4 is used as push pull output, no external

component is required.

LATEN : Latch select input under Field BET (Sub-Link)

0 : Forbidden

1 : Latched result

GPIO3

GPIO3 : General Purpose Input/Output.

When GPIO3 is used as Open-Drain Output, it must be

connected with a pull-up resistor to VDD.

When GPIO3 is used as push pull output, no external

component is required.

SCL

SCL input/output for 2-wire serial I/F.

SDA

SDA input/output for 2-wire serial I/F.

CLKIN

Clock Input

D11-D0

23,22,20-17,15,14,12-9

Pixel Data Input

HSYNC

HSYNC Input

VSYNC

VSYNC Input

RF/BETOUT

RF : Input Clock Triggering edge select. See Figure 15.

0 : Falling Edge

1 : Rising Edge

BETOUT : Field BET Result Output when Field BET

mode.

PDN

Power Down

0 : Power Down

1 : Normal Operation

TEST2

Test pin. Must be tied to Ground for normal operation.

TEST1

Test pin. Must be tied to Ground for normal operation.

CAPOUT

PWR

Decoupling Capacitor Pin, 1.2V output.

CAPINA

PWR

Reference Input for Analog Circuit. Must be tied to

CAPOUT.

CAPINP

PWR

Reference Input for Analog Circuit. Must be tied to

CAPOUT.

VDD

PWR

1.7-3.6V Digital Power Supply Pin for LVCMOS I/O

AVDD

PWR

1.7-3.6V Analog Power Supply Pin for LDO

EXPGND

GND

Exposed Pad Ground. Must be tied to the PCB ground

plane through an array of vias.

CO : CML Output buffer , CB : CML Bi-directional buffer

I : LVCMOS Input buffer , IL : Low Speed LVCMOS Input buffer , B : LVCMOS Bi-directional buffer

PWR : Power supply , GND : Ground

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Pin Description for THCV236

Pin Name

Pin No.

Type

Description

RXP

High-Speed CML Signal Input(Main-Link)

RXN

High-Speed CML Signal Input(Main-Link)

HFSEL/RCMP

CB/I

HFSEL : High Frequency Mode select when PDN1=0.

0 : High Frequency Mode Disable

1 : High Frequency Mode Enable

RCMP : CML Signal Bi-directional Input/Output(Sub-Link) when

PDN1=1.

MAINMODE/

RCMN

CB/I

MAINMODE : Setting V-by-One® HS Mode or Sync Free Mode

when PDN1=0

0 : V-by-One® HS Mode

1 : Sync Free Mode

RCMN : CML Signal Bi-directional Input/Output(Sub-Link)

when PDN1=1.

HTPDN/

SUBMODE

HTPDN : Hot Plug Detect Output when PDN1=0. Must be

connected to Tx HTPDN with 10kΩ pull-up resistor.

SUBMODE : Sub-Link Mode Select when PDN1=1.

0 : 2-wire serial I/F Mode (default No Clock Stretching mode)

1 : Low Speed Data Bridge Mode

Forbid setting 1 when connecting with THCV231.

LOCKN/

MSSEL

LOCKN : Lock Detect Output when PDN1=0. Must be connected

to Tx LOCKN with 10kΩ pull-up resistor.

MSSEL : Sub-Link Master/Slave Select when PDN1=1.

0 : Sub-Link Master side(inside 2-wire serial I/F is slave)

1 : Sub-Link Slave side(inside 2-wire serial I/F is master)

Sub-Link Master is connected to HOST MPU.

Forbid setting 1 when connecting with THCV231.

LATEN/SD3/

AIN1/GPIO0

LATEN : Latch select input under Field BET(Main-Link or

Sub-Link).

0 : NOT Latched result

1 : Latched result

SD3 : Sub-Link Data Input/Output when PDN1=1 and

SUBMODE=1.

When Sub-Link is Master (MSSEL=0), SD3 is output.

When Sub-Link is Slave (MSSEL=1), SD3 is input.

AIN1 : Device ID setting for 2-wire serial I/F when

SUBMODE=0 and MSSEL=0. See Table 18.

GPIO0 : General Purpose Input/Output when SUBMODE=0 and

MSSEL=1.

When GPIO0 is used as Open-Drain Output, it must be connected

with a pull-up resistor to VDD.

When GPIO0 is used as push pull output or input, no external

component is required.

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TTLDRV/SD2/

AIN0/GPIO1

TTLDRV : LVCMOS Output Drive Strength Select when

PDN1=0.

0 : Weak Drive Strength

1 : Normal Drive Strength

SD2 : Sub-Link Data Input/Output when PDN1=1 and

SUBMODE=1.

When Sub-Link is Master (MSSEL=0), SD2 is input.

When Sub-Link is Slave (MSSEL=1), SD2 is output.

AIN0 : Device ID setting for 2-wire serial I/F when

SUBMODE=0 and MSSEL=0. See Table 18.

GPIO1 : General Purpose Input/Output when SUBMODE=0 and

MSSEL=1.

When GPIO1 is used as Open-Drain Output, it must be connected

with a pull-up resistor to VDD.

When GPIO1 is used as push pull output or input, no external

component is required.

OUTSEL/SD1

OUTSEL : Permanent Clock Output Enable when PDN1=0.

0 : Permanent Clock Output Disable

1 : Permanent Clock Output Enable

SD1 : Sub-Link Data Input/Output when PDN1=1.

When SUBMODE=0, SD1 is used as SCL input/output for 2-wire

serial I/F, requires pull-up resistor to VDD.

When SUBMODE=1 and MSSEL=0, SD1 is input.

When SUBMODE=1 and MSSEL=1, SD1 is output.

COL1/SD0

COL1 : Color Space Converter Enable when PDN1=0 and

MAINMODE=0.

0 : Color Space Converter Disable

1 : Color Space Converter Enable

Data Width Setting when PDN1=0 and MAINMODE=1. See

Table 15.

SD0 : Sub-Link Data Input/Output when PDN1=1.

When SUBMODE=0, SD0 is used as SDA input/output for 2-wire

serial I/F, requires pull-up resistor to VDD.

When SUBMODE=1 and MSSEL=0, SD0 is input.

When SUBMODE=1 and MSSEL=1, SD0 is output.

COL0/INT/

GPIO2

COL0 : Data Width Setting when PDN1=0. See Table 15.

INT : Interrupt signal output for Sub-Link when SUBMODE=0

and MSSEL=0. It must be connected with a pull-up resistor to

VDD.

L : Interrupt occurred

H : Steady state

GPIO2 : General Purpose Input/Output when SUBMODE=0 and

MSSEL=1.

When GPIO2 is used as Open-Drain Output, it must be connected

with a pull-up resistor to VDD.

When GPIO2 is used as push pull output or input, no external

component is required.

CLKOUT

Clock Output

D31-D26

12-15,17,18

Pixel Data Output

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D25/GPIO4

D25 : Pixel Data Output

GPIO4 : General Purpose Input/Output when SUBMODE=0,

MSSEL=1 and RXDEFSEL=0.

When GPIO4 is used as Open-Drain Output, it must be connected

with a pull-up resistor to VDD. When GPIO4 is used as push pull

output or input, no external component is required.

D24/GPIO3

D24 : Pixel Data Output

GPIO3 : General Purpose Input/Output when SUBMODE=0,

MSSEL=1 and RXDEFSEL=0.

When GPIO3 is used as Open-Drain Output, it must be connected

with a pull-up resistor to VDD. When GPIO3 is used as push pull

output or input, no external component is required.

D23-D0

21-24,27-31,33-39,

42-47,52,53

Pixel Data Output

DE Output

HSYNC

HSYNC Output

VSYNC

VSYNC Output

Output Enable

0 : LVCMOS Output Disable (Hi-Z) except for HTPDN,

LOCKN when PDN1=0 and except for BETOUT when BET=1

1 : LVCMOS Output Enable

BET

Field BET entry

0 : Normal Operation

1 : Field BET Operation

RF/BETOUT

RF : Output Clock Triggering edge select. See Figure 16.

0 : Falling Edge

1 : Rising Edge

BETOUT : Field BET Result Output

RXDEFSEL

Internal Register Default Setting Select. See Table 35, Table 36

0 : for THCV231

1 : for THCV235

LFSEL

Low Frequency mode select

0 : Low Frequency mode Disable

1 : Low Frequency mode Enable

Forbid setting 1 when connecting with THCV231.

PDN1

Sub-Link Power Down

0 : Power Down. Main-Link setting by external pin

1 : Normal Operation. Main-Link Setting by 2-wire serial I/F

PDN0

Main-Link Power Down

0 : Power Down

1 : Normal Operation

TEST2

Test pin. Must be tied to Ground for normal operation.

TEST1

Test pin. Must be tied to Ground for normal operation.

CAPOUT

PWR

Decoupling Capacitor Pin, 1.2V output.

CAPINA

PWR

Reference Input for Analog Circuit. Must be tied to CAPOUT.

VDD

49,41,32,25,16

PWR

1.7-3.6V Digital Power Supply Pin for LVCMOS I/O

AVDD

PWR

1.7-3.6V Analog Power Supply Pin for LDO

EXPGND

GND

Exposed Pad Ground. Must be tied to the PCB ground plane

through an array of vias.

CI : CML Input buffer , CB : CML Bi-directional buffer

I : LVCMOS Input buffer , IL : Low Speed LVCMOS Input buffer , O: LVCMOS Output buffer

B : LVCMOS Bi-directional buffer , BO : Open-Drain LVCMOS Bi-directional buffer

PWR : Power supply , GND : Ground

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Table 1. Pin Sharing Description (THCV231-THCV236 usage)

Sub-Link State →

2-wire serial

I/F Mode

Sub-Link

Master/Slave →

Master

PDN1

HTPDN/SUBMODE

LOCKN/MSSEL

BET

RXDEFSEL

RF/BETOUT

BETOUT(*1)

COL0/INT/GPIO2

INT

COL1/SD0

SD0(SDA)

OUTSEL/SD1

SD1(SCL)

TTLDRV/SD2/AIN0/GPIO1

AIN0

LATEN/SD3/AIN1/GPIO0

AIN1

LATEN(*2)

D24/GPIO3

GPIO3(*3)

D25/GPIO4

GPIO4(*3)

HTPDN/SUBMODE

SUBMODE

LOCKN/MSSEL

MSSEL

MAINMODE/RCMN

RCMN

HFSEL/RCMP

RCMP

*1 When Field BET mode (Main-Link or Sub-Link), it functions as BETOUT output.

*2 When Field BET mode (Main-Link or Sub-Link), it functions as LATEN input.

*3 Through GPIO input is default on register setting

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Functional Overview

With High Speed CML SerDes, proprietary encoding scheme and CDR (Clock and Data Recovery)

architecture, the THCV231 and THCV236 enable transmission of 14bit data through Main-Link by single

differential pair cable with minimal external components. In addition, the THCV231 and THCV236 have

Sub-Link which enables bi-directional transmission of 2-wire serial interface signals, GPIO signals and also

HTPDN/LOCKN signals for Main-Link through the other 1-pair of CML-Line. It does not need any external

frequency reference such as a crystal oscillator. The THCV231 - THCV236 system is able to watch peripheral

devices and to control them via 2-wire serial interface or GPIOs. They also can report interrupt events caused by

change of GPIO inputs and internal statuses.

Functional Description

Internal Reference Output/Input Function (CAPOUT, CAPINA, CAPINP)

An internal regulator produces the 1.2V (CAPOUT). This 1.2V linear regulator can’t supply any other

external loads. Bypass CAPOUT to GND with 10uF.

CAPINP (THCV231 only) supplies reference voltage for internal PLL, and CAPINA supplies reference

voltage for any internal analog circuit. Bypass CAPINP/CAPINA to GND with 0.1uF to remove high frequency

noise. CAPOUT, CAPINA and CAPINP must be tied together.

Power supply AVDD is supposed to be stabilized with de-coupling capacitor and series noise filter (for example,

ferrite bead).

CAPOUT

CAPINA

CAPINP

THCV231

10uF

0.1uF

AVDD

Power

Supply

CAPOUT

CAPINA

THCV236

10uF

0.1uF

AVDD

Power

Supply

Figure 1. Connection of CAPOUT, CAPINA, CAPINP and Decoupling Capacitor

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Power Down (PDN1, PDN0, PDN)

PDN1, PDN0 and PDN turn off internal circuitry of Main-Link and Sub-Link separately.

Table 2. Power Down Setting(THCV231)

PDN

Operation

Both Main-Link and Sub-Link power down

Both Main-Link and Sub-Link active

Table 3. Power Down Setting(THCV236)

PDN1

PDN0

Operation

Both Main-Link and Sub-Link power down

Only Main-Link is active

Only Sub-Link is active

Both Main-Link and Sub-Link active

Pre-emphasis and Drive Select Function (THCV231 only)

Pre-emphasis can equalize severe signal degradation caused by long-distance or high-speed transmission. PRE

See Table 4.

Table 4. Pre-emphasis and Drive Select function table

CMLDRV[1:0]

(register)

PRE

(register)

Condition

Swing Level

Pre-emphasis Level

400mV diff p-p

0dB

6dB

600mV diff p-p

0dB

3.5dB

800mV diff p-p

0dB

Forbidden

Permanent Clock Output (THCV236 only)

When there is no input from Main-Link, the THCV236 will output internal oscillator clock from CLKOUT pin.

This function is controlled by OUTSEL pin or OUTSEL_ENABLE register and OUTSEL_SETTING register.

See Table 5.

Table 5. Permanent Clock Output function table (PDN1=1)

OUTSEL_

ENABLE

(register)

OUTSEL_

SETTING

(register)

Output Clock

Frequency(*1)

80MHz

40MHz(default)

20MHz

10MHz

*1 typical value

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