Texas Instruments UCC2351 Series Manual de usuario
UCC2351x Evaluation Module
User's Guide
Literature Number: SLUUBW3B
October 2018–Revised June 2020
2SLUUBW3B–October 2018–Revised June 2020
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UCC2351x Evaluation Module User’s Guide
User's Guide
SLUUBW3B–October 2018–Revised June 2020
UCC2351x Evaluation Module User’s Guide
1 Introduction
The UCC23513EVM-014 evaluation module is designed for evaluation of TI's 3.75- and 5-kVRMS isolated
single-channel gate drivers with opto-compatible inputs including UCC23513, UCC23513B, UCC23513-
Q1, UCC23511, UCC23511-Q1, UCC23313-Q1, and UCC23313B. The input is current driven, requiring
between 7 mA and 16 mA for device turn-on, and can be reverse biased for turn-off. This family of devices
provides high source and sink current drivers for driving Si MOSFETs, IGBTs, and SiC transistors. This
user's guide covers the UCC23513EVM-014, which is used for evaluation of the entire family of pin-to-pin
compatible devices.
Developed for high voltage applications where isolation and reliability are required, the UCC23XXX family
of devices deliver reinforced isolation of 3.75 and 5 kVRMS and a surge immunity of up to 8 kV along with a
common-mode transient immunity (CMTI) greater than 150 V/ns. They offer lower propagation delay,
lower-part to-part delay skew, higher CMTI, smaller Pulse Width Distortion, and higher operating
temperature, which provides a significant performance upgrade over opto-isolated gate drivers, while still
maintaining pin-to-pin compatibility.
The input current and voltage characteristics of the e-diode functionally mimics the primary side of an
opto-isolator. The output side VCC has a wide recommended operating range from 14-V to 33-V and
allows the device to be used in a low-side or high-side configuration along with bipolar supplies for IGBTs
and SiC Power FETs. The pin-to-pin compatibility enables designers to use the devices in both existing
and new designs for motor drives, industrial power supplies, solar inverters, and UPSes.
2 Description
The UCC23513EVM-014 evaluation board utilizes a SN74LVC2G17DBVR (dual Schmitt-Trigger buffer) to
drive the signal current on the primary side of the device. The board is populated with test points and 2-
position headers for flexibility in connecting power and signal inputs, along with signal test points and large
GND vias to enable installation of ground springs. The PCB layout is optimized with minimal loop area in
the input and output paths and showcases design for high voltage between the primary side and
secondary side with >8.5 mm creepage. For detailed device information, refer to the individual datasheets
and TI's Isolated gate driver solutions.
Table 1. EVM Compatible Devices
Part Number Description Package
UCC23513 4-A source / 5-A sink output current, 12-V
UVLO, 5 kVRMS
Stretched SO-6 package with >8.5-mm
creepage and clearance
UCC23513B 4-A source / 5-A sink output current, 8-V
UVLO, 5 kVRMS
Stretched SO-6 package with >8.5-mm
creepage and clearance
UCC23513-Q1 Automotive, 4-A source / 5-A sink output
current, 12-V UVLO, 5 kVRMS
Stretched SO-6 package with >8.5-mm
creepage and clearance
UCC23511 1-A source / 2-A sink output current, 12-V
UVLO, 5 kVRMS
Stretched SO-6 package with >8.5-mm
creepage and clearance
UCC23511-Q1 Automotive, 1-A source / 2-A sink output
current, 12-V UVLO, 5 kVRMS
Stretched SO-6 package with >8.5-mm
creepage and clearance
UCC23313-Q1 Automotive, 4-A source / 5-A sink output
current, 12-V UVLO, 3.75 kVRMS
Stretched SO-6 package with >8.5-mm
creepage and clearance
UCC23313B 4-A source / 5-A sink output current, 8-V
UVLO, 3.75 kVRMS
Stretched SO-6 package with >8.5-mm
creepage and clearance
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Description
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2.1 Features
• Evaluation module for the UCC23XXX family in stretched SO-6 package
• 5-V input buffer, and 14-V to 33-V VCC power supply range
• 1-A source / 2-A sink or 4-A source / 5-A source/sink current capabilities
• 3.75-kVRMS or 5-kVRMS Isolation rated for 1 minute per UL 1577
• Buffer disconnect headers for custom input drive solution
• PCB layout showcases high voltage isolation design between primary side and secondary side
• Unpopulated pads for bootstrap supply, split supply, and turn on/turn off resistance
Description
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2.2 I/O Description
Table 2. Jumpers Setting
PINS DESCRIPTION
J1–1 Anode Buffer Input
J1–2 GND Input
J2–1 Cathode Buffer Input
J2–2 GND Input
J3–1 Anode Buffer Jumper
J3–2 Anode Buffer Jumper
J4–1 Cathode Buffer Jumper
J4–2 Cathode Buffer Jumper
J5–1 Cathode Resistor to GND Jumper
J5–2 Cathode Resistor to GND Jumper
J6–1 VG to 1 nF Load Jumper
J6–2 VG to 1 nF Load Jumper
J7–1 VG to 180 nF Load Jumper
J7–2 VG to 180 nF Load Jumper
P1–1 +5 V Buffer Supply
P1-2 GND
P2-1 +14 V–33 V Output-Side Supply
P2-2 VSS
2.3 Jumpers (Shunt) Options
Table 3. Jumpers Setting
JACK Jumper Setting Options FACTORY SETTING
J1 Option A: Jumper not installed, IN/PWM signal provided by external signal Option A
Option B: Jumper on J1-1 and J1-2 set Anode Buffer Input low
J2 Option A: Jumper on J2-1 and J2-2 set Cathode Buffer Input low Option A
Option B: Jumper not installed, IN/PWM signal provided by external signal
J3 Option A: Jumper on J3-1 and J3-2, pass signal to Anode Resistor Option A
Option B: Jumper not installed, Anode_R left floating for external drive
J4 Option A: Jumper on J4-1 and J4-2, pass signal to Cathode Resistor Option A
Option B: Jumper not installed, Cathode_R left floating for external drive
J5 Option A: Jumper not installed, Cathode_R left floating from GND Option A
Option B: Jumper on J5-1 and J5-2, ties Cathode_R to GND
J6 Option A: Jumper installed, VG tied to 1nF test load Option A
Option B: Jumper not installed, VG floating
J7 Option A: Jumper not installed, VG floating Option A
Option B: Jumper installed, VG tied to 180nF test load
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Electrical Specifications
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3 Electrical Specifications
Table 4. UCC23513EVM-014 Electrical Specifications
DESCRIPTION MIN TYP MAX UNIT
VDD Primary-side power supply 4.5 5.5 V
VCC Driver output power supply 14 33 V
FSSwitching frequency 0 1 MHz
TJOperating junction temperature range -40 150 °C
4 Test Summary
In this section, the UCC23513EVM-014 is tested in its default configuration. Different jumper settings,
PWM signal input options, and voltage source settings can be found in Section 3 Electrical Specifications.
4.1 Definitions
This procedure details how to configure the UCC23XXX evaluation board. Within this test procedure, the
following naming conventions are followed. Refer to the UCC23513EVM-014 schematic, Section 8, for
details.
VXX:External voltage supply name
V(TPxx):Voltage at test point TPxx. For example, V(TP12) means the voltage at TP12.
V(Jxx):Voltage at jack terminal Jxx
Jxx(yy):Terminal or pin yy of jack xx
DMM: Digital multi-meters
UUT: Unit under test
EVM: Evaluation module assembly. In this case, the UUT assembly drawings have location for jumpers,
test points, and individual components.
4.2 Equipment
4.2.1 Power Supplies
Two DC power supplies with voltage/current above 5-V/0.1-A and 35-V/0.5-A (for example: Agilent
E3634A)
4.2.2 Function Generator
One function generator over 1 MHz (for example: Tektronics AFG3252)
4.3 Equipment Setup
4.3.1 DC Power Supply Settings
• DC power supply #1
– Voltage setting: 5-V
– Current limit: 0.05-A
• DC power supply #2
– Voltage setting: 15-V or 12-V depending on IC mounted
– Current limit: 0.1 A
Shunt #1 Shunt #3
Shunt #2
Shunt #4
Test Summary
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4.3.2 Digital Multi-Meter Settings
• Digital multi-meter #1
– DC current measurement, auto-range
• Digital multi-meter #2
– DC current measurement, auto-range
4.3.3 Function Generator Settings
Table 5. Function Generator Settings
MODE FREQUENCY DUTY DELAY HIGH LOW OUTPUT
IMPEDANCE
Channel
Output Pulse DC ~ 100 kHz 50% 0 ns 5 V 0 V High Z
4.3.4 Oscilloscope Setting
Table 6. Oscilloscope Settings
BANDWIDTH COUPLING TERMINATION SCALE SETTINGS INVERTING
Channel A 500 MHz or above DC 1 MΩor automatic 10× or automatic OFF
Channel B 500 MHz or above DC 1 MΩor automatic 10× or automatic OFF
4.3.5 Jumper (Shunt) Settings
Default shunt configuration is used for this test.
Figure 1. Default Jumper Settings
+
s
Power
Supply #1
(5V/0.05A)
+
s
Power
Supply #2
(15V/0.1A)
+
s
DMM #2
DC Current
CH1
EVM
Function
Generator
Oscilloscope
DMM #1
DC Current
+
s
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Test Summary
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4.3.6 Bench Setup Diagram
The current bench setup diagram includes the function generator and oscilloscope connections.
Follow the connection procedure below. Figure 2 can be used as a reference.
• Make sure the output of the function generator and voltage sources are disabled before connecting.
• Function generator channel applied on J1-1 ←→ J1-2 (see in Figure 2)
• Power supply #1: positive node connected to input of DMM #1 with DMM #1 output connected to P1-1
(or VDD), and negative node applied on P1-2 (or GND).
• Power supply #2: positive node connected to input of DMM #2 with DMM #2 output connected to P2-1
(or VCC), negative node connected directly to P2-2 (or VSS).
• Oscilloscope channel-A probes Anode_R ←→ GND, smaller measurement loop is preferred.
• Oscilloscope channel-B probes VG (or J7-1) ←→ VSS, smaller measurement loop is preferred.
Figure 2. Bench Setup Diagram and Configuration
Power Up and Power Down Procedure
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5 Power Up and Power Down Procedure
5.1 Power Up (CL= 1000 pF)
1. Before proceeding to the power up procedure, make sure that Section 4.3.6 is implemented for setting
up all the equipment. Figure 3 can be used as reference.
2. Enable supply #1.
3. Enable supply #2.The quiescent current on DMM1 and DMM2 ranges in 1 mA to 3 mA if everything is
set correctly.
4. Enable function generator output.
5. Afterward, the following occurs:
1. Stable pulse output on the channel-A and channel-B in the oscilloscope. See Figure 3.
2. Scope frequency measurement is the same as function generator output.
3. DMM #1 and #2 should read measurement results around 5 mA–10 mA under no load conditions.
For more information about operating current, refer to the corresponding datasheet.
Figure 3. Example Input and Output Waveforms (Ch1 is PWM Input, Ch2 is Output)
5.2 Power Down
1. Disable function generator.
2. Disable power supply #2.
3. Disable power supply #1.
4. Disconnect cables and probes.
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Test Waveforms with Different Input/Output Configurations
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6 Test Waveforms with Different Input/Output Configurations
6.1 Input Side Reverse Bias
The default configuration grounds the input to cathode buffer. The cathode buffer can alternatively be
driven with a function generator to reverse bias the input diode on turn-off. With J2 jumper (shunt)
removed, cathode and anode buffers are driven 180º out-of-phase, which showcases the reverse blocking
capability of the devices.
Figure 4. Input e-Diode driven +/-5 V
(Ch1 is PWM Input, Ch2 is Output)
6.2 Output Split Supply
The output can be configured to provide split supply operation through two unique methods.
Single supply: Remove R9 and install C6 = C7 = 1 µF, R7 = 7.5 kohm, D2 = 5.1 V Zener, and R8 jumper.
Dual supply: Remove R9 and install C12 = 0.1 µF, C13 = 2.2 µF, apply V+ from VCC to VSS, and V- from
VSS to Phase.
These configurations allow output operation from -5 V off, to VCC-5V on which is commonly found in SiC
power stage configurations. Figure 5 shows operation with the latter method.
Test Waveforms with Different Input/Output Configurations
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Figure 5. Output Split Supply Operation
(Ch1 is PWM Input, Ch2 is Output)
6.3 Peak Output Current Measurement Using 180nF Load
The output can be configured to measure peak output current by moving the jumper from J6 to J7. This
jumpers in a 180 nF load capacitor, C15, which can be used to indirectly measure the output current as
seen in the Understanding Peak Source and Sink Current Parameters Application Note (SLLA387). Input
PWM is set to 200 Hz to avoid excessive power dissipation in the driver.
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