Texas Instruments TPS65680 Manual de usuario

SLVUBB1–November 2017

How to Use the TPS65680 Evaluation Module

ADVANCE INFORMATION

User's Guide

SLVUBB1–November 2017

How to Use the TPS65680 Evaluation Module

The TPS65680EVM is an evaluation tool for the TPS65680 18-Channel Pattern-Programmable Level

Shifter with Overcurrent Protection for use in large format liquid-crystal display (LCD) display applications

such as TVs and monitors. The TPS65680 supports up to twelve high-voltage clock (GCK) outputs in

charge-sharing or gate-voltage shaping configuration, six high-voltage control outputs for generating start,

clear and reset, and low frequency signals and panel discharge. The evaluation module with its graphical

user interface (GUI) enables the programming of the device from a Microsoft®Windows ®7 or 10 PC and

provides easy access to all 18 outputs, 3 supplies and logic inputs.

This user's guide describes the characteristics, operation and use of the TPS65680 evaluation module

(EVM) and its drive software. This EVM contains TI's 18-channel pattern-programmable level shifter with

overcurrent protection IC TPS65680. The user's guide includes EVM specifications, the recommended test

setup (hardware and software), the schematic diagram, the bill of materials, and the board layouts.

All typical characteristics measurements in the TPS65680 data sheet were done with this evaluation

module.

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Contents

1 Introduction ................................................................................................................... 3

1.1 Requirements ....................................................................................................... 3

1.2 Applications.......................................................................................................... 3

1.3 Features.............................................................................................................. 4

2 TPS65680 EVM Electrical and Performance Specifications........................................................... 4

3 TPS65680 EVM Schematic ................................................................................................ 5

4 Connector and Test Point Descriptions................................................................................... 6

4.1 Supply Connectors ................................................................................................. 6

4.2 Input Connectors.................................................................................................... 7

4.3 Level-Shifter Output Connectors.................................................................................. 7

4.4 Additional Jumpers and Connectors ............................................................................. 8

5 Test Setup .................................................................................................................... 8

5.1 EVM Operation...................................................................................................... 8

5.2 Software Setup to Change the Output Voltages and Configuration.......................................... 9

5.3 Hardware Setup..................................................................................................... 9

5.4 Software Operation................................................................................................. 9

6 TPS65680 EVM Assembly Drawings and Layout...................................................................... 11

7 Bill of Materials ............................................................................................................. 14

List of Figures

1 TPS65680 EVM Schematic ................................................................................................ 5

2 Two- and Four-Terminal Connection...................................................................................... 6

3 TPS65680 Software Window............................................................................................. 10

4 TPS65680 EVM Top Composite ......................................................................................... 11

5 TPS65680 EVM Top Layer ............................................................................................... 12

6 TPS65680 EVM Bottom Layer (Bottom View).......................................................................... 13

List of Tables

1 TPS65680 EVM Electrical and Performance Specifications........................................................... 4

2 TPS65680 EVM Bill of Materials ......................................................................................... 14

Trademarks

Microsoft, Windows are registered trademarks of Microsoft Corporation.

All other trademarks are the property of their respective owners.

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Introduction

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How to Use the TPS65680 Evaluation Module

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1 Introduction

The TPS65680 EVM uses the TPS65680 device to deliver 18 high-voltage level-shifter output channels to

support the high-voltage gate signals of gate-in-array (GOA) or gate-in-panel (GIP) LCD displays. The

EVM makes it easy to examine the programmability and performance of the TPS65680 device.

1.1 Requirements

The IC on the EVM is not programmed and the outputs will only toggle after a pattern is loaded. The EVM

comes with the USB2ANY interface adapter and the connectors. For programming the device, you

additionally must have a host computer, and a DC power supply. To operate the level shifters, 2 square

wave outputs of a frequency generator or microcontroller are necessary.

1.1.1 Power Supplies

In order to operate this EVM, 3 DC power supplies, PS1, PS2, and PS3, with the following requirements

are needed:

• PS1 to supply VIN: 2.7 V to 5.5 V capable of 0.5 A

• PS2 to supply VGL: –18 V to –4 V capable of 1 A

• PS3 to supply VGH: 9 V to 40 V capable of 1 A

1.1.2 Digital Inputs

The output signals of a gate signal level shifter on an LCD TFT need to be synchronized to the timing

controller that delivers the image content. To keep TPS65680 synchronised to the timing controller

signals, just 2 digital input signals are necessary:

• LN_CLK is the input signal for the TPS65680 internal PLL. This fixed frequency signal is often set to

the line frequency.

• A rising edge on LS_START starts the programmed pattern from the programmed start address. This

fixed frequency signal is normally set to the frame frequency, for example; 60 Hz, 120 Hz, 240 Hz, and

so forth.

1.1.3 Host Computer

A computer with a USB port is required program the TPS65680 on the EVM. The TPS65680 software runs

on a personal computer (PC) and communicates with the EVM through a USB port.

The minimum requirements for the PC are:

• Microsoft Windows 7 or 10 operating system

• 1 USB port

• A minimum of 280MB of free hard disk space (610MB recommended)

• A minimum of 512MB of RAM

1.1.4 Software

Texas Instruments provides the software necessary to program the TPS65680 and evaluate the IC

functionality. After you are approved, download the software and install it on your computer.

In addition to ease the first start with the device, TI provides some standard patterns and a How-To-Start

Video. All of these are included in your 'mySecure Software' folder which included this user's guide.

1.2 Applications

• LCD and OLED panels using GIP and GOA technology

• TV, monitor, notebook, and tablet PC

Introduction

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1.3 Features

• Eases design by providing a simple way to evaluate TPS65680

• Includes pattern examples to ease first evaluation

• How-to video available for the first programming steps

• The added interface board (USB2ANY) connects the EVM to a Microsoft Windows 7 or 10 PC

• This tool is tested and includes the graphical user interface (GUI) as well as the hardware and software

user's guide

• Power and sense connections available on power supply inputs

• GUI enables programmability

• Double-sided, two-active-layer printed-circuit board (PCB) with all components on the top side

2 TPS65680 EVM Electrical and Performance Specifications

Table 1 lists the EVM electrical and performance specifications.

Table 1. TPS65680 EVM Electrical and Performance Specifications

Parameter Test Conditions MIN TYP MAX Unit

Supply

VIOperating input voltage on VIN pin 2.7 5.5 V

V(VGL) Operating input voltage on VGL1 and

VGL2 pins –18 –4 V

V(VGH) Operating input voltage on VGH pin 9 40 V

Undervoltage lockout threshold (VI)VIrising 2.55 2.6 2.7 V

VIfalling 2.45 2.5 2.55 V

Undervoltage lockout threshold

(V(VGL))V(VGL) rising –3 –2.5 –2 V

V(VGL) falling –4 –3.5 –3 V

Undervoltage lockout threshold

(V(VGH))V(VGH) rising 6 7 8 V

V(VGH) falling 3.8 4 4.2 V

Logic Signal Requirements (LS_CNTRL, LS_START, LN_CLK, SCL, SDA)

VIH High-level input voltage 1.25 V

VIL Low-level input voltage 0.55 V

VIN

GND

S+

VGH

GND

S+

VGL

GND

S+

S-

TP1

TP2

SCL

SDA

OTP_LDO

GND

LS_CNTRL

GND

LS_START

GND

LN_CLK

GND

J49

10µF

2.2µF

J48

CS1

CS2

GVS

1.00k

GND

GNDGND

GND GND

2.2µF

GND

J27

RC 1000pFC26

1000pFC25

GND

G12AP

J52

GND

VIN

LS_CNTRL_SW

1 2

J50

GCK9

GND

GCK9

J25

RC 1000pFC24

1000pFC23

GND

GCK8

GND

J23

RC 1000pFC22

1000pFC21

GND

GCK7

GND

J29

RC 1000pFC28

1000pFC27

GND

GCK10

GND

J31

RC 1000pFC30

1000pFC29

GND

GCK11

GND

J33

RC 1000pFC32

1000pFC31

GND

GCK12

GND

J35

RC 1000pFC34

1000pFC33

GND

GSP1

GND

J11

R C

100

1000pF

C10

1000pF

GND

G C K 1

G ND

GND

J13

R C

1000pF

C12

1000pF

C11

GND

G C K 2

G ND

GND

J15

R C

1000pF

C14

1000pF

C13

GND

G C K 3

G ND

GND

J17

R C

1000pF

C16

1000pF

C15

GND

G C K 4

G ND

GND

J19

R C

1000pF

C18

1000pF

C17

GND

G C K 5

G ND

GND

J21

R C

1000pF

C20

1000pF

C19

GND

G C K 6

G ND

GND

GCK1

GCK2

GCK3

GCK4

GCK5

GCK6

GCK7

GCK8

GCK10

GCK11

GCK12

GSP1

J39

R C

1000pF

C38

1000pF

C37

GC P

G ND

GND

J41

R C

1000pF

C40

1000pF

C39

G P P 1

G ND

GND

J43

R C

1000pF

C42

1000pF

C41

G P P 2

G ND

GND

J45

R C

1000pF

C44

1000pF

C43

VS S

G ND

GND

J37

RC 1000pFC36

1000pFC35

GND

GSP2

GND

GSP2

GCP

GGP1

GGP2

VSS

0.01 µF

C45

J12

J14

J16

J18

J20

J22

J24

J26

J28

J30

J32

J34

J36

J38

J40

J42

J44

J46

220 µF

C46

GND

220 µF

C47

GND

220 µF

C48

GND

VGL

VGH

VIN

10k

R24

10k

R25

VIN

J54

J55

J56

J57

J58

J59

J60

J61

J62

J63

J64

J65

R27

R26

GNDGND

G C K 1

G C K 2

G C K 3

G C K 4

G C K 5

G C K 6

G C K 7

G C K 8

G C K 9

G C K 10

G C K 11

G C K 12

100

R10

100

R11

100

R12

100

R13

100

R14

100

R15

100

R16

100

R17

100

R18

100

R19

100

R20

100

R21

100

R22

100

R23

1000pF

C50

1000pF

C49

2.2µF

GND

VG L

1NC 3

4OUT 5

GND

TPS71533DCKRG4

0.1µF

C51

0.47 µF

C52

3V3 LDO

EXT_3V3

VIN

GND

EXT_3V3 3.3V

EXT_3V3

J10

GND

3V3

I2C_SEL

GND

I2C_SEL

3.3V

SCL

SDA

LN_CLK

LS_CNTRL

LS_START

I2C_SEL

OTP_LDO

VIN

VGL1

GGP2 10

GGP1 11

VSS 12

GCP 13

GCK12 14

GCK11 15

GCK10 16

GCK9 17

GCK8 18

GCK7 19

CS2

20 CS1

GCK6 22

GCK5 23

GCK4 24

GCK3 25

GCK2 26

GCK1 27

GSP2 28

GSP1 29

VGH

GND 31

PLLC

PAD 33

TPS65680RSMR

910

J53

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TPS65680 EVM Schematic

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3 TPS65680 EVM Schematic

Figure 1 is for reference only; see the bill of materials in Table 2 for specific values.

Figure 1. TPS65680 EVM Schematic

Power

Supply EVM

SNS +

SNS -

S +

S -

VIN

GND

Power

Supply EVM

SNS +

SNS -

S +

S -

VIN

GND

2-wire connection

4-wire connection

Connector and Test Point Descriptions

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4 Connector and Test Point Descriptions

4.1 Supply Connectors

4.1.1 J1 – VIN, Input Sense, and GND Connector

This header is the connection of the input power supply, VI, and its sense connections. The power supply

must be connected between pins 1 and 2 (VIN) and pins 5 and 6 (GND). Twist the leads to the input

supply and keep them as short as possible. The input voltage must be between 2.7 V and 5.5 V.

4.1.2 J2 – VGH, Input Sense, and GND Connector

This header is the connection of the power supply, V(VGH), and its sense connections. The power supply

must be connected between pins 1 and 2 (VGH) and pins 5 and 6 (GND). Twist the leads to the input

supply and keep them as short as possible. The input voltage must be between 9 V and 40 V.

4.1.3 J3 – VGL, Input Sense, and GND Connector

This header is the connection of the power supply, V(VGL) and its sense connections. The power supply

must be connected between pins 1 and 2 (VGL) and pins 5 and 6 (GND). Twist the leads to the input

supply and keep them as short as possible. The input voltage must be between –18 V and –4 V.

Use the middle two pins of the input connectors to sense the input voltage and make a four-terminal

connection. Four-terminal connections are more accurate than two-terminal connections. Figure 2 shows

the setup for two-terminal and four-terminal connections.

Figure 2. Two- and Four-Terminal Connection

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Connector and Test Point Descriptions

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4.2 Input Connectors

4.2.1 J4 – LN_CLK - Input and GND Connector

This header is the connection for the LN_CLK input square wave signal. Connect a frequency generator or

microcontroller output between pins 1 and 2 (LN_CLK) and pins 3 and 4 (GND) to supply the device with

the input signal for the internal PLL. The square wave needs to have a frequency from 40 kHz to 500 kHz

and a duty cycle of 40% to 60%.

4.2.2 J5 – LS_START - Input and GND Connector

This header is the connection for the LS_START input signal. Connect a frequency generator or

microcontroller output between pins 1 and 2 (LS_START) and pins 3 and 4 (GND) to supply the device

with the input signal starting the programmed output pattern from the programmed start address. The

LS_START pulse needs to have a pulse width of 15 µs to 500 µs.

4.2.3 J6, J52, and S2 – LS_CNTRL - Input and GND Connectors

The header J6 is the connection for the LS_CNTRL input signal. For programming the TPS65680 this

signal needs to be low, if this signal is set high, the IC is in active mode and the device can be controlled

via the LN_CLK and LS_START signals.

This signal can be driven from an external source, via header J52 or from the GUI.

• GUI: Set switch S2 to SW side

• J52: Set switch S2 to J52 side and use the jumper on J52 to drive the signal high (connect middle pin

to pin 1 (VIN)) or low (connect middle pin to pin 3 (GND))

• External source: Remove the jumper from header J52 and set switch S2 to J52.

4.3 Level-Shifter Output Connectors

4.3.1 J36, J38, J12, J14, J16, J18, J20, J22, J24, J6, J28, J30, J32, J34, J40, J46, J42, and J44 – GSP1,

GSP2, GCK1 to GCK12, GCP, VSS, GGP1 and GGP2 - Output and GND Connectors

These headers are the connection of the 18 level-shifter outputs. Connect a scope probe between pins 1

and 2 (GND) and pins 3 and 4 (output) to measure this specific level shifter output.

4.3.2 J35, J37, J11, J13, J15, J17, J19, J21, J23, J25, J29, J31, J33, J39, J45, J41, and J43 –

Connectors to add load to the level shifter outputs

These headers can be used to add capacitive or RC load to the respective one of the 18 level shifter

outputs. Connect a jumper between pins 1 and 2 (C) to add a capacitive load to the respective level shifter

output or connect a jumper between pins 2 and 3 (RC) to add an RC load to the respective level shifter

output.

4.3.3 J54, J55, J56, J57, J59, J60, J61, J62, J63, J64, and J65 – Connectors to add identical loads to 2

level shifter outputs to measure charge sharing

These headers can be used to add identical RC loads to the respective 2 of the 12 level shifter clock

outputs that are used during charge sharing. Connect a jumper on one of the headers J54 to J59 to add a

load to one of the channels GCK1 to GCK6 and another jumper on one of the headers J60 to J65 to add

an RC load to one of the channels GCK7 to GCK12. If the 2 resistors R26 and R27 and the 2 capacitors

C49 and C50 have the identical values, the output voltages of the channels that are sharing their charge

should meet at the voltage V(VGL) + ((V(VGH) - V(VGL))/2)

NOTE: Be aware that capacitors with the identical theoretical value do not match in reality. For

identical capacitance values you need to measure the capacitors and select two that have

identical values before applying them to the EVM.

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4.4 Additional Jumpers and Connectors

4.4.1 J49 and J43 – CS1 and CS2 - Enable Gate Voltage Shaping (GVS) or Charge Sharing (CS)

These headers are used to decide if CS or GVS is used when a channel is connected to the CSx pins.

CS1 and CS2 need to be connected to the same value, either both to GVS (CS1 and CS2 pins are then

connected through the resistors R1 and R3 to GND) or both to CS (CS1 and CS2 pins are connected

together through the resistor R2).

If GVS is selected, a clock output can be discharged to GND through resistor R1 or R3 before it changes

its state from high to low or vice versa.

If CS is selected, 2 clock outputs can share their charge before changing their opposite states (one needs

to be high, the other one needs to be low at the beginning of the CS phase).

4.4.2 J10 – I2C_SEL- Select Between I2C Address 0x42 or 0x43

The I2C_SEL input defines the last bit of the I2C address of TPS65680. This makes it possible to easily

use 2 TPS65680 on one I2C bus in high-resolution panels. Connect this pin to GND by shorting pins 2

and 3 to set the I2C address to 0x42. Connect this pin to 3V3 by connecting pins 1 and 2 to set the I2C

address to 0x43.

4.4.3 J53 – USB2ANY

With the 10-pin header J53 the EVM connects through the USB2ANY interface box to a PC. The installed

GUI communicates through the I2C pins 9 and 10 of J53 with the TPS65680 on the EVM. Pin 1 of J53 can

drive LS_CNTRL via S2, pin 2 of J53 connects I2C_SEL to the GUI. The GUI reads this voltage before

any communication with the IC.

4.4.4 J7 – 3.3V - Voltage Limitation for USB2ANY

The GUI is able to read the voltage on the I2C_SEL pin through pin 2 of J53. As USB2ANY allows a

maximum voltage of 3.6 V on the pins of J53, it is necessary to limit the voltage on I2C_SEL. The 3.3-V

LDO U2 creates a logic voltage out of VIN that does not exceed 3.3 V.

4.4.5 J50 – Connect C8 to the OTP_LDO pin

This header connects a capacitor (C8) to the OTP_LDO pin. A jumper on this header is necessary if the

content of the registers is stored in the OTP non-volatile memory. The voltage on this pin is observed on

the header J9. While the OTP is written, the voltage on this pin is created via an internal LDO from VGH.

To keep the voltage during the write process stable, the capacitor needs to be connected via a jumper on

header J50.

5 Test Setup

5.1 EVM Operation

Three different voltage supplies are necessary to operate the EVM. These can be delivered by three

power supplies or by an LCD bias device, like TPS65175, TPS65640, or alike. The digital input signals

LN_CLK and LS_START are delivered by the timing controller in the final application, but for evaluation

purposes, frequency generator or microcontroller outputs can be used as well.

The TPS65680 on the EVM is not pre-programmed, so it needs to be programmed before the outputs can

deliver a pattern. TI delivers some pre-defined patterns for the first tests. Download these patterns from

your 'mySecure Software' page in your myTI account on the web.

To ease the first setup of the EVM, review the video in your 'mySecure Software' page in your myTI

account on the web.

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Test Setup

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5.2 Software Setup to Change the Output Voltages and Configuration

Download the software (see Section 1.1.4) and the installation instructions (zipped file), unpack it, and

execute the setup.exe file. This installs the up-to-date software version. TI recommends removing older

versions before installing the updated one.

5.3 Hardware Setup

Connect the three power supplies to the following headers:

• J1: Connect the power supply for VIN (2.7 V to 5.5 V) to this header. The absolute maximum voltage

for VIN is 6 V.

• J2: Connect the power supply for VGH (9 V to 40 V) to this header. The absolute maximum voltage for

VGH is 42 V.

• J3: Connect the power supply for VGL (–18 V to –4 V) to this header. The absolute maximum voltage

for VGL is –20 V.

CAUTION

Make sure that the voltage delta from VGH to VGL never exceeds 55 V!

Connect the outputs of the frequency generator or microcontroller to J4 (LN_CLLK) and J5 (LS_START).

Connect the 10-pin ribbon cable out of the HPA-665 bag to J53, the other end to the USB2ANY box and

with the USB-cable the other side of the USB2ANY box to the PC.

For the first startup, set the switch S2 to SW (for software), and the two jumpers on J43 and J49 to GVS.

5.4 Software Operation

After the installation of the software, an icon with the name TPS65680 appears on the desktop (if checked

within the installation) of the host computer. If it does not, browse the program files in the Start menu for

the software. The default location is All Programs →Texas Instruments →TPS65680 EVM.

After connecting the USB interface adapter to the host computer, the software can be started. At the first

start-up, the system asks to update the firmware of the adapter (follow the firmware update instructions

given). After confirmation of this update, the software window shown in Figure 3 appears.

Please go to Help →User Manual for a detailed description of all GUI functions.

Test Setup

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Figure 3. TPS65680 Software Window

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