Texas Instruments TPS6507xEVM Manual de usuario

User's Guide

SLVU291B–April 2010–Revised September 2011

TPS6507xEVM

This user’s guide describes the characteristics, operation, and use of the TPS6507xEVM-430 evaluation

module (EVM). The TPS6507xEVM-430 is a fully assembled and tested platform for evaluating the

performance of the TPS6507x single-chip power management devices. This document includes schematic

diagrams, a printed circuit board (PCB) layout, bill of materials, and test data. Throughout this document,

the abbreviations EVM,TPS6507xEVM, and the term evaluation module are synonymous with the

TPS6507xEVM-430 unless otherwise noted.

Contents

1 Introduction .................................................................................................................. 2

2 TPS6507xEVM Electrical Performance Specifications ................................................................. 4

3 TPS6507xEVM Schematic ................................................................................................. 6

4 Connector and Test Point Descriptions .................................................................................. 8

5 Setup ........................................................................................................................ 12

6 EVM Assembly Drawings and Layout .................................................................................. 13

7 Bill of Materials ............................................................................................................. 19

List of Figures

1 TPS6507xEVM Schematic (Sheet 1)..................................................................................... 6

2 TPS6507xEVM Schematic (Sheet 2)..................................................................................... 7

3 TPS6507xEVM Hardware Connection.................................................................................. 12

4 TPS6507xEVM Component Placement (Viewed from Top) ......................................................... 13

5 TPS6507xEVM Silkscreen (Viewed from Top) ........................................................................ 14

6 TPS6507xEVM Top Copper (Viewed from Top) ...................................................................... 15

7 TPS6507xEVM Bottom Copper (X-Ray View from Top) ............................................................. 16

8 TPS6507xEVM Internal 1 (X-Ray View from Top).................................................................... 17

9 TPS6507xEVM Internal 2 (X-Ray View from Top).................................................................... 18

List of Tables

1 TPS6507xEVM Ordering Information .................................................................................... 3

2 TPS6507xEVM Performance Characteristics ........................................................................... 4

3 TPS65070EVM-430 Bill of Materials ................................................................................... 19

OMAP is a trademark of Texas Instruments.

Microsoft, Windows are registered trademarks of Microsoft Corporation.

I2C is a trademark of NXP Semiconductors.

All other trademarks are the property of their respective owners.

SLVU291B–April 2010–Revised September 2011 TPS6507xEVM

Introduction

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1 Introduction

The TPS6507x are a series of single-chip power management ICs for portable applications consisting of a

battery charger with Power Path management for a single lithium-ion (Li-Ion) or lithium-polymer

(Li-Polymer) cell. The charger can be supplied either by a USB port on the device USB pin or by a dc

voltage from a wall adapter connected to the device AC pin. Three highly-efficient, 2.25-MHz step-down

converters provide the core voltage, memory, and input/output (I/O) voltage in a processor-based system.

The step-down converters enter a low-power mode under light loads for maximum efficiency across the

widest possible range of load currents. In addition, there are two 200-mA low-dropout regulators (LDOs).

For low-noise applications, these devices can be forced into fixed-frequency PWM using the I2C™

interface. The I2C interface allows the user to adjust various settings of the charger, the Power Path, the

dc-to-dc converters, and the LDOs. The step-down converters allow the use of small inductors and

capacitors in order to achieve a small total solution size.

1.1 Features

•Battery charger with Power Path management

•Up to 2.0-A output current on the Power Path

•Three step-down converters

•Two LDOs (200-mA output current)

•wLED boost converter

•Up to 25 mA per string with internal current sink

•10-Bit analog-to-digital converter (ADC)/Touch screen interface

•I2C-compatible interface

1.2 Applications

•Portable navigation systems

•PDAs, pocket PCs

•OMAP™and low-power DSP supply

2TPS6507xEVM SLVU291B–April 2010–Revised September 2011

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Introduction

1.3 Requirements

In order to operate this EVM properly, the related software and hardware must be connected and properly

configured. All components and connectors are installed on the EVM as shipped, except for the host

computer and the dc power supply.

The most current version of the software must be downloaded from the TI website at www.ti.com.

1.3.1 Software

To download the software that is necessary to operate the TPS6507xEVM, check the TPS6507x product

folder on the TI Web site.

1.3.2 Host Computer

A computer with an available USB port is required to operate this EVM. The TPS6507xEVM software runs

on the personal computer and communicates with the EVM via the PC USB port and the USB to GPIO

interface. The PC must meet these minimum system requirements:

•Microsoft®Windows®2000 or XP operating system

•Available USB port

•Minimum of 30 MB of free hard disk space (100 MB recommended)

•Minimum of 256 MB of RAM

1.3.3 Power Supply

A dc power supply capable of delivering 5 V at 3 A is required to operate this EVM.

1.3.4 Ordering Options

Table 1 provides the ordering information for the various EVM options.

Table 1. TPS6507xEVM Ordering Information

Output Voltage Output Voltage Output Current

Device Part DCDC1 / DCDC2 DCDC1 / DCDC2 / Supported

LDO1 / LDO2

Orderable EVM Number Number / DCDC3 DCDC3 Processor

TPS65070EVM-430 TPS65070 3.3 V 1.8 V / 1.2 V 0.6 A / 1.5 A / 1.5 A OMAP-L1x8

1.8 V / 3.3 V

1.0 V / 1.2 V

TPS65072EVM-430 TPS65072 1.8 V / 1.2 V 1.2 V / 1.2 V 0.6 A / 0.6 A / 0.6 A Atlas IV

TPS65073EVM-430 TPS65073 1.8 V 1.8 V / 1.8 V 0.6 A / 0.6 A / 1.5 A OMAP35xx

1.2 V / 1.8 V

1.2 V / 1.35 V

TPS650731EVM-430 TPS650731 1.8 V 1.8 V / 1.8 V 0.6 A / 0.6 A / 1.5 A OMAP35xx

1.2 V / 1.8 V

1.2 V / 1.35 V

TPS650732EVM-430 TPS650732 1.8 V 1.8 V / 1.8 V 0.6 A / 0.6 A / 1.5 A OMAP3505

1.8 V / 3.3 V

1.2 V / 1.35 V

SLVU291B–April 2010–Revised September 2011 TPS6507xEVM

TPS6507xEVM Electrical Performance Specifications

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2 TPS6507xEVM Electrical Performance Specifications

Table 2 summarizes the TPS65070EVM-430 performance specifications.

Table 2. TPS6507xEVM Performance Characteristics

Parameter Symbol Notes and Conditions Min Nom Max Units

Input Characteristics

Input Voltage, AC VAC 4.3 17 V

Input Voltage, USB VUSB 4.3 5.8 V

Input Voltage, AC, USB 4.3 5.8 V

charging

Input Voltage, DCDC1, VIN_DCDC 2.8 6.3(1) V

DCDC2, DCDC3

Input Voltage, LDO1, LDO2 VIN_LDO 1.8 6.3(1) V

Output Characteristics

DCDC1

Default Output Voltage VOUT_DCDC1 TPS65070, TPS65072 3.3 V

DCDC1

Default Output Voltage VOUT_DCDC1 TPS65073, TPS650731, TPS650732 1.8 V

DCDC1

Output Voltage Range 3.3V or VIN_DCDC

0.725 V

Adjustable with I2C

DCDC1 (whichever is less)

Output Current DCDC1 VIN = Min to max 600 mA

DCDC2

DEFDCDC2 = Low 1.8 V

TPS65070,

VOUT_DCDC2 DEFDCDC2 =

TPS650732 3.3 V

High

DEFDCDC2 = Low 1.8 V

Default Output Voltage VOUT_DCDC2 TPS65072 DEFDCDC2 =

DCDC2 2.5 V

High

DEFDCDC2 = Low 1.2 V

TPS65073,

VOUT_DCDC2 DEFDCDC2 =

TPS650731 1.8 V

High

Output Voltage Range 3.3V or VIN_DCDC

0.725 V

Adjustable with I2C

DCDC2 (whichever is less)

TPS65072, TPS65073, TPS650731, 600 mA

TPS650732

Output Current DCDC2 TPS65070 1500 mA

DCDC3

DEFDCDC3 = Low 1 V

VOUT_DCDC3 TPS65070 DEFDCDC3 = 1.2 V

High

DEFDCDC3 = Low 1.2 V

Default Output Voltage VOUT_DCDC3 TPS65072 DEFDCDC3 =

DCDC3 1.4 V

High

DEFDCDC3 = Low 1.2 V

TPS65073,

VOUT_DCDC3 TPS650731, DEFDCDC3 = 1.35 V

TPS650732 High

TPS65072 600 mA

Output Current DCDC2 TPS65070, TPS65073, TPS650731, 1500 mA

TPS650732

(1) 6.3 V or VSYS, whichever is less.

4TPS6507xEVM SLVU291B–April 2010–Revised September 2011

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TPS6507xEVM Electrical Performance Specifications

Table 2. TPS6507xEVM Performance Characteristics (continued)

Parameter Symbol Notes and Conditions Min Nom Max Units

LDO1, LDO2

TPS65070 1.8 mA

Default Output Voltage LDO1, TPS65072 1.2 mA

LDO2 TPS65073, TPS650731, TPS650732 1.8 mA

TPS65070 1.2 mA

Default Output Voltage LDO2, TPS65072 1.2 mA

LDO2 TPS65073, TPS650731, TPS650732 1.8 mA

Output Current LDO1, LDO2 200 mA

wLED Boost Converter and Current Sinks

Switching frequency wLED 1125 kHz

boost

Input voltage at ISINK1 , ISINK2 16 V

Internal overvoltage 35 37 39 V

protection

Maximum boost factor 9 10 V

(VIN/VOUT)

PWM dimming resolution 1 %

Tolerance between current sinks ISINK1, ISINK2 5 %

ADC Converter

Input voltage range AD_IN1 0 2.25 V

to AD_IN4

ADC resolution 10 Bits

Differential linearity error ±1 LSB

Offset error 1 5 LSB

Gain error ±8 LSB

Sampling rime 220 µs

Conversion time 19 µs

Reference voltage on –1 2.26 +1 %

BYPASS

Power Path

Minimum battery voltage VBATMIN 2.75 V

Input overvoltage protection V(OVP) 5.8 6.0 6.3 V

Switching from AC to BAT TSW(ACBAT) 200 µs

Switching from USB to BAT TSW(USBBAT) 200 µs

Switching from AC to USB TSW(ACUSB) 200 µs

From power applied to start of power-up

SYS power-up delay 11 ms

sequence

Dropout voltage AC to SYS ILIMITAC = 2500 mA, ISYS = 1000 mA 150 mV

Dropout voltage USB to SYS ILIMITUSB = 13000 mA, ISYS = 800 mA 160 mV

Dropout voltage USB to SYS VBAT = 3.0 V, ISYS = 1000 mA 85 100 mV

Charger

Battery discharge current 2 A

Battery charge voltage Set in internal register 4.1 4.25 V

Battery fast-charge current Set with external resistor 100 1500 mA

range

Pre-charge current IPRECHG 0.08 ×ICHG 0.10 ×ICHG 0.12 ×ICHG

Charge termination current ITERM 0.08 ×ICHG 0.10 ×ICHG 0.12 ×ICHG

Switching frequency fSW 1950 2250 2550 kHz

SLVU291B–April 2010–Revised September 2011 TPS6507xEVM

TPS6507xEVM Schematic

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3 TPS6507xEVM Schematic

Figure 1 and Figure 2 show the two sheets of the TPS65070EVM-430 schematic.

NOTE: These diagrams are provided for reference only. See Table 3, the Bill of Materials, for

specific component values.

Figure 1. TPS6507xEVM Schematic (Sheet 1)

6TPS6507xEVM SLVU291B–April 2010–Revised September 2011

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TPS6507xEVM Schematic

Figure 2. TPS6507xEVM Schematic (Sheet 2)

SLVU291B–April 2010–Revised September 2011 TPS6507xEVM

Connector and Test Point Descriptions

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4 Connector and Test Point Descriptions

4.1 Input / Output Connector Descriptions

4.1.1 J1: VINLDO1, 2, GND

J1 pin 1 is the input supply for LDO1 and LDO2. In the default configuration, VINLDO1,2 is connected to

SYS with R1. To connect VINLDO1,2 to any other voltage source, remove R1 and connect the

VINLDO1,2 supply between J1 pin 1 (positive connection) and J1 pin 2 (GND connection).

4.1.2 J2: AC, GND

A power supply can be connected between J2 pin 1 (AC) and J2 pin 2 (GND). The AC pin is one of the

EVM inputs. Note that the voltage rating on the AC pin ranges from 4.3 V up to 17 V. The allowable

voltage range on both the AC and USB pins for charging is from 4.3 V up to 5.8 V. If the voltage on the

AC pin exceeds 5.8 V, the charger goes into overvoltage lockout.

The input current on the Power Path input AC pin is current-limited. The current limit can be changed in

User Register PPATH1 (01h). The default input current limit is set to 2500 mA. For more information, refer

to the respective device data sheet, available for download at www.ti.com.

4.1.3 J3: USB, GND

Connect your power supply positive terminal to J3 pin 1. Connect your power supply negative terminal to

J3 pin 2. Note that the voltage rating on the USB input ranges from 4.3 V up to 17 V. The allowable

voltage range on both the AC and USB pins for charging is from 4.3 V up to 5.8 V. If the voltage on the

AC pin exceeds 5.8 V, the charger goes into overvoltage lockout.

The input current on the Power Path input USB pin is current-limited. The current limit can be changed in

User Register PPATH1 (01h). The default input current limit is set to 500 mA. For more information, refer

to the respective device data sheet, available for download at www.ti.com.

4.1.4 J4: SYS

J4 is connected to the output of the Power Path (SYS). When the TPS6507x device is turned off and there

is no voltage source applied at either the AC or USB pins, the SYS output is disconnected internally from

the battery. When the TPS6507x is turned on by pulling PB_IN low, the voltage at SYS ramps up. If there

is no voltage applied at either the AC or USB pin, SYS remains connected to VBAT internally. If there is a

voltage applied at either the AC or USB pin, SYS is connected to this input. If both input supplies are

connected, the AC input has priority. The voltage at SYS is not regulated.

4.1.5 J5: GND

J5 is connected to GND.

4.1.6 J6: VBAT, GND, TS

Connect your single-cell Li-Ion or Li-Polymer cell positive connection to J6 pins 1 and 2. Connect your

battery negative connection between J6 pins 3 and 4. If your battery provides a thermistor (NTC)

connection, you can connect the thermistor to J6 pin 5. Note that the factory default EVM configuration

includes a 10-kΩresistor connected from TS to GND (R5). If you wish to use the battery internal resistor,

R5 must first be removed. The thermistor type is defined in User Register CHGCONFIG1 with the bit

SENSOR TYPE. Two different thermistor types can be selected: 100 kΩand 10 kΩ; the default selection

is 10 kΩ.

A resistor in parallel to the thermistor (NTC) is required for linearization (see the TPS6507x data sheet for

details). Note that the factory default EVM configuration uses a 75-kΩresistor for linearization (R6).

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Connector and Test Point Descriptions

4.1.7 J7: VLDO1, GND

J7 pins 1 and 2 are connected to the positive output of linear regulator LDO1. J7 pins 2 and 4 are the

GND connection for LDO1. A load can be connected between J7 pins 1 and 2 (VLDO1) and J13 pins 3

and 4 (GND).

LDO1 is able to supply a load current up to 200 mA.

4.1.8 J8: VLDO2, GND

J8 pins 1 and 2 are connected to the positive output of linear regulator LDO2. J8 pins 2 and 4 are the

GND connection for LDO2. A load can be connected between J8 pins 1 and 2 (VLDO2) and J8 pins 3 and

4 (GND).

LDO2 is able to supply a load current up to 200 mA.

4.1.9 J9: VDCDC1, GND

J9 pins 3 and 4 are connected to the positive output of the step-down converter DCDC1. J9 pins 1 and 2

are the GND connection of DCDC1. A load can be connected between J9 pins 3 and 4 (VDCDC1) and J9

pins 1 and 2 (GND).

Refer to Table 2 for information on the maximum output current and default output voltage of DCDC1.

4.1.10 J10: VDCDC2, GND

J10 pins 3 and 4 are connected to the positive output of the step-down converter DCDC2. J10 pins 1 and

2 are the GND connection of DCDC2. A load can be connected between J10 pins 3 and 4 (VDCDC2) and

J10 pins 1 and 2 (GND).

Refer to Table 2 for information on the maximum output current and default output voltage of DCDC2.

4.1.11 J11: VDCDC3, GND

J11 pins 3 and 4 are the positive output of the step-down converter DCDC3. J11 pins 1 and 2 are the

GND connection of DCDC3. A load can be connected between J11 pins 3 and 4 (VDCDC3) and J11 pins

1 and 2 (GND).

Refer to Table 2 for information on the maximum output current and default output voltage of DCDC3.

4.1.12 J12: I2C Interface

J12 is a 10-pin interface connector to connect to the I2C interface.

4.1.13 J13: I2C Interface

J13 is a 14-pin interface connector to connect to the I2C interface. This connector is not assembled in the

factory default EVM setup.

4.1.14 J14: AD_IN1–4, BYPASS, INT_LDO, GND

AD_IN1, AD_IN2, AD_IN3, and AD_IN4 are the external inputs of the 10-bit ADC. Connect an external

voltage source or touch screen (If configured as touch screen controller) to these pins. See the respective

device data sheet for additional information on the touch screen interface and ADC input configuration.

J14 pin 5 is connected to BYPASS. BYPASS can be used as an internal reference for the ADC. A 10-µF

capacitor is connected from BYPASS to GND (C10).

J14 pin 6 is connected to the output of the internal LDO, INT_LDO. This LDO provides power for the touch

screen controller (TSREF). A 2.2-µF capacitor is connected from INT_LDO to GND (C13).

SLVU291B–April 2010–Revised September 2011 TPS6507xEVM

Connector and Test Point Descriptions

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4.1.15 J15: PB_IN, PB_OUT, POWER_ON, PGOOD, RESET/EN_EXTLDO, INT

J15, pin 1: PB_IN

J15 pin 1 is connected to PB_IN. Pulling PB_IN low starts up all dc-dc converters and LDOs according

to the internal power-up sequence. Refer to Table 9 in the data sheet (SLVS950) for information on the

internal power-up sequence. Note that if PB_IN is released high, all dc-dc converters and LDOs shut

down if the POWER_ON input is low. If POWER_ON is pulled high before PB_IN is released high

again, the dc-dc converters and LDOs remain on. Note that PB_IN is also connected to S1. PB_IN is

pulled up to AVDD6 with an internal 50-kΩpull-up resistor. Pressing the Push-Button S1 pulls PB_IN

low.

J15, pin 2: PB_OUT

J15 pin 2 is connected to the open drain output PB_OUT. PB_OUT is driven by the status of PB_IN. If

PB_IN is low, PB_OUT is also low. If PB_IN is high, PB_OUT is driven to a high impedance state.

PB_OUT is pulled up to a pull-up voltage with resistor R37. In the factory default configuration, VSYS

is selected as the pull-up voltage. In addition, VOUT_DCDC1 and VOUT_DCDC2 can be configured as

pull-up voltages with R22 and R23, respectively.

J15, pin 3: POWER_ON

The POWER_ON pin must be pulled high before PB_IN is released high again to keep the dc-dc

converters and LDOs enabled once PB_IN is released high. Pulling POWER_ON low disables all dc-dc

converters and LDOs. POWER_ON is pulled up to a pull-up voltage with R32. In the factory default

configuration, VSYS is selected as the pull-up voltage. In addition, VOUT_DCDC1 and VOUT_DCDC2

can be configured as pull-up voltages with R22 and R23, respectively.

J15, pin 4: PGOOD

J15 pin 4 is connected to the open drain output PGOOD. PGOOD goes low depending on the setting

in the PGOODMASK register. In this register, different PGOOD bits of each dc-dc converter and LDO

can be connected to the PGOOD open drain output. PGOOD is connected to a pull-up voltage with

resistor R34. In the factory default EVM configuration, VSYS is selected as the pull-up voltage with

R21. In addition, VOUT_DCDC1 and VOUT_DCDC2 can be configured as pull-up voltages with R22

and R23, respectively.

J15, pin 6: RESET/EN_EXTLDO

J15 pin 5 is connected to the open drain output RESET. The TPS65070, TPS65073, TPS650731, and

TPS650732 each contain circuitry that can generate a reset pulse for a processor. The voltage at the

THRESHOLD pin is sensed; if this voltage goes above the threshold voltage of 1.0 V (typ), the RESET

output goes to a high impedance state after a delay time defined in the PGOOD register. If the voltage

at the THRESHOLD pin is below the threshold voltage, the PGOOD output is pulled low.

In the TPS65072, this pin is an active high push-pull output called EN_EXTLDO. This pin is controlled

internally and only used for sequencing the Sirf Prima or Atlas IV processors.

J15, pin 6: INT

J15 pin 6 is connected to the open drain output INT. The INT output indicates if there is an interrupt

active. The interrupts can be configured in the INT register. Different events can be masked as an

interrupt (for example, AC pin or USB pin power removed or applied), or as a touch screen Interface,

PB_IN.

INT is connected to a pull-up voltage with resistor R38. In the factory default EVM configuration, VSYS

is selected as the pull-up voltage with R21. In addition, VOUT_DCDC1 and VOUT_DCDC2 can be

configured as pull-up voltages with R22 and R23, respectively.

10 TPS6507xEVM SLVU291B–April 2010–Revised September 2011

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