Texas Instruments TLV62080 Manual de usuario

User's Guide

SLVU640A–December 2011–Revised February 2014

TLV62080, 1.2-A, High-Efficiency, Step-Down Converter in

2-mm × 2-mm SON Package

This user’s guide describes the TLV62080 evaluation module (EVM) and explains how to perform a stand-

alone evaluation or interface with a host or system. The converter is designed to deliver up to 1200 mA of

continuous current to the output. The TLV62084 shares the same EVM by swapping the IC. The

TLV62084 delivers up to 2-A continuous output current.

Contents

1 Introduction .................................................................................................................. 1

2 Considerations for Evaluating the TLV62080 ........................................................................... 1

3 Test Summary ............................................................................................................... 1

4 Schematic, Physical Layout and Bill of Materials ....................................................................... 7

1 Introduction

The TLV62080 focuses on high-efficiency, step-down conversion over a wide output current range. At

medium-to-heavy loads, the converter operates in PWM mode and automatically enters the PFM or

power-save mode of operation at light-load currents to maintain high efficiency over the entire load current

range. To address the requirements of powering supply rails, the internal compensation circuit allows a

large selection of external output capacitor values, ranging from 10 µF up to 100 µF. The TLV62080

operates at a nominal frequency of 3 MHz. With its DCS-Control™ architecture, excellent load transient

performance, and output voltage regulation, accuracy is achieved. The robust architecture and safety

features allow perfect system integration. The device is available in a 2-mm × 2-mm package with thermal

pad.

2 Considerations for Evaluating the TLV62080

This integrated circuit (IC) has two modes of operation. The PWM/PFM mode is selected when the load

current is greater than half the ripple current (in continuous conduction mode). At light loads, when the

inductor current is discontinuous, the IC automatically goes into PFM mode and delivers fewer pulses,

trying to keep a tight regulation with low ripple.

3 Test Summary

The TLV62080EVM-641 board requires an adjustable dc power supply with up to a 6-V output and ≥600

mA for powering the input to the EVM, and a resistive output load between 825 Ωand 5 Ω. Choose the

proper power rating for the load resistor, P = V2/R. Use at least 2× the calculated power dissipation. The

test setup connections and jumper settings selections are configured for a stand-alone evaluation, but can

be changed to interface with external hardware such as a system load and microcontroller.

SLVU640A–December 2011–Revised February 2014 TLV62080, 1.2-A, High-Efficiency, Step-Down Converter in 2-mm × 2-mm

SON Package

S001

EVM Assembly

Test Summary

www.ti.com

3.1 Equipment

• Adjustable dc power supply between 2.7 V and 6 V with adjustable current limit set to ~550 mA

• Load: System load or load resistors 5 Ω, 3 W; 100 Ω, 0.25 W; and 825 Ω, 0.25 W

• Three Fluke 77 digital multimeters (DMM) (equivalent or better)

• Oscilloscope, Tektronix model TDS222 (equivalent or better)

3.2 Equipment and EVM Setup

Table 1 shows the setup input/output connections and configuration of the TLV62080 evaluation module.

The silk screen labels are shown in parentheses.

Table 1. Setup I/O Connections and Configuration for TLV62080EVM Evaluation

Jack/Component (Silk Screen) Connect or Adjustment to:

J1-1/2 (Vin) P/S positive lead, preset to 4 Vdc; 550-mA current limit

J2-1 (+ SNS); input Positive lead of DMM #1

J2-2 (– SNS); input Negative lead of DMM #1

J3-1/2 (GND) P/S negative lead.

J5-1/2 (Vout) Positive lead to system load or load resistance

J6-1 (+ SNS); output Positive lead of DMM #2

J6-2 (– SNS); output Negative lead of DMM #2

J7-1/2 (GND) Negative lead to system load or load resistance

J4-1 (PG) Positive lead of DMM #3

J4-2 (GND) Negative lead of DMM #3

JP1-1/2 (ON) Apply shunt to ON for converter operation

Connect the meters, scope probes, output load, shunt, and input power supply as listed in Table 1; set the

oscilloscope to 200 ns/div, positive trigger, dc-coupled on CH2, CH1; ac-coupled and 20 mV/div on CH3;

and ac-coupled and 10 mV/div on CH4. Users may want to replace the load resistors with a system load

or decade load box to vary load (1-kΩto 5-Ωload).

Figure 1. EVM Schematic and Evaluation Setup

2TLV62080, 1.2-A, High-Efficiency, Step-Down Converter in 2-mm × 2-mm SLVU640A–December 2011–Revised February 2014

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Test Summary

3.3 Test Procedure

1. Ensure that the EVM is set up according to Table 1 and Figure 1, and that the power supply is preset

to 4 Vdc at ~550-mA current limit.

2. Turn on input supply, and verify that the input voltage is ~4 Vdc (DMM#1) and the output voltage is at

~2.5 Vdc (DMM#2).

3. Look at CH2 and CH3, and verify that the duty cycle is near 67% and the output ripple is less than 10

mV; see Figure 2 for typical waveforms. Note that the output inductance used on the test board used

to take the photographs is a 2.2-µH inductor and the one on the factory EVM is a 1-µH inductor;

therefore, the output ripple is approximately twice the amplitude shown. These waveforms were taken

with high-frequency probes (meaning that the ground lead was very short (~1 cm). This greatly

reduces the high-frequency spikes that the ground loop on the probe picks up.

4. Change the load to from 5 Ωto 100 Ω, 0.25 W. Observe the change in the switching waveforms. As

the load is reduced, the inductor current becomes discontinuous, and the control automatically

switches to PFM mode. Users may need to change the time scale on the oscilloscope to 1 µs/div for

light loads (see Figure 3). Set the load back to approximately 5 Ω.

5. Vary input voltage between 2.5 V and 5 V, and observe the change in duty cycle and ripple

waveforms.

6. Disconnect positive lead of input supply. Set CH1 to 2 Vdc/div, CH3 to 1 Vdc/div, and time to 50

µs/div. Set trigger to CH1, trigger level to 2 V, and arm single-sequence trigger. Hot-plug input supply.

See Figure 4 for a typical power up. Figure 5 shows the timing of the PG pin applying the input hot

plug.

7. Set the single-sequence trigger for negative slope and time for 100 µs/div; arm scope and unplug

power supply. See Figure 6 for an example of power down by removing input supply.

8. Remove the enable shunt, JP2, and connect CH1 to JP2-2 (EN) and plug in the input supply. Arm the

oscilloscope, and short between JP2-2 and JP2-1 (OFF). The captured waveform shows output power

down by pulling EN low (Figure 7).

9. Set scope to positive trigger, arm scope and remove short between JP2-1/2. The captured waveform

shows output power up by pulling EN high (Figure 8)

10. With an understanding of the basic functions of the EVM, users may want to connect the EVM into

their system using short, twisted wires to minimize impedance.

SLVU640A–December 2011–Revised February 2014 TLV62080, 1.2-A, High-Efficiency, Step-Down Converter in 2-mm × 2-mm

SON Package

Vinput_ripple

Vphase

Vout_ripple

Vinput_ripple

Vphase

Vout_ripple

Test Summary

www.ti.com

Figure 2. PWM Mode. Vin = 4 V, Vout = 2.5 V, Iout = 0.5 A. CCM Operation, Therefore PWM Mode CH1 =

Input Ripple; CH2 = Phase; CH3 = Output Ripple

Figure 3. PFM Mode. Vin = 4 V, Vout = 2.5 V, Iout = 25 mA. DCM Operation, Therefore PFM Mode CH1 =

Input Ripple; CH2 = Phase; CH3 = Output Ripple

4TLV62080, 1.2-A, High-Efficiency, Step-Down Converter in 2-mm × 2-mm SLVU640A–December 2011–Revised February 2014

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Vpg

Vout_Start-up_50 _loadW

Vphase

Vinput

Vphase

Vout

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Test Summary

Figure 4. Start-Up in PWM/PFM Mode. Vin = 4 V, Vout = 2.5 V, Iout = 0.5 A; CH1 = Input Voltage; CH2 =

Phase; CH3 = Output Voltage

Figure 5. Start-Up in PWM/PFM Mode. Vin = 5 V, Vout = 2.5 V, Iout = 0.5 A; CH4 = Input Voltage; CH1 =

Phase; CH2 = Output Voltage; CH3 = PG

SLVU640A–December 2011–Revised February 2014 TLV62080, 1.2-A, High-Efficiency, Step-Down Converter in 2-mm × 2-mm

SON Package

Ven

Vphase

Vout

Vinput

Vphase

Vout

Test Summary

www.ti.com

Figure 6. Power Down in PWM/PFM Mode, Vin = 4 V, Vout = 2.5 V, Iout = 0.5 A; CH1 = Input Voltage; CH2

= Phase; CH3 = Output Voltage

Figure 7. Shutdown Output With EN Pin. Vin = 4 V, Vout = 2.5 V, Iout = 0.5 A; CH1 = Input Voltage; CH2 =

Phase; CH3 = Output Voltage

6TLV62080, 1.2-A, High-Efficiency, Step-Down Converter in 2-mm × 2-mm SLVU640A–December 2011–Revised February 2014

SON Package Submit Documentation Feedback

S002

Ven

Vphase

Vout

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Schematic, Physical Layout and Bill of Materials

Figure 8. Power-Up Output With EN pin. Vin = 4 V, Vout = 2.5 V, Iout = 0.5 A; CH1 = Input Voltage; CH2 =

Phase; CH3 = Output Voltage

4 Schematic, Physical Layout and Bill of Materials

Schematic

Figure 9. Schematic

SLVU640A–December 2011–Revised February 2014 TLV62080, 1.2-A, High-Efficiency, Step-Down Converter in 2-mm × 2-mm

SON Package

K002

K001

Schematic, Physical Layout and Bill of Materials

www.ti.com

Physical Layouts

Figure 10. Assembly Layer

Figure 11. Top Layer

8TLV62080, 1.2-A, High-Efficiency, Step-Down Converter in 2-mm × 2-mm SLVU640A–December 2011–Revised February 2014

SON Package Submit Documentation Feedback

K003

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Schematic, Physical Layout and Bill of Materials

Figure 12. Bottom Layer

SLVU640A–December 2011–Revised February 2014 TLV62080, 1.2-A, High-Efficiency, Step-Down Converter in 2-mm × 2-mm

SON Package

Schematic, Physical Layout and Bill of Materials

www.ti.com

4.1 Bill of Materials

Table 2. Bill of Materials

Count RefDes Value Description Size Part Number MFR

1 C1 10 µF Capacitor, ceramic, 6.3-V, X5R, 20% 0603 Std Std

1 C2 22 µF Capacitor, ceramic, 6.3-V, X5R, 20% 0805 GRM21BR60J226ME39L Murata

1 C3 47 µF Capacitor, tantalum, 8-V, 35-mΩ, 20% 3528(B) T520B476M008ATE035 Kemet

0 C4 Open Capacitor, ceramic 0805 Std Std

0 C5, C6 Open Capacitor, ceramic 1210 Std Std

7 J1, J2, J3, J4, PEC02SAAN Header, male 2-pin, 100-mil (2,54-mm) 0.100 inch (2,54 mm) PEC02SAAN Sullins

J5, J6, J7 spacing spacing

1 JP1 PEC03SAAN Header, 3 pin, 100-mil (2,54-mm) 0.100 inch (2,54 mm) PEC03SAAN Sullins

spacing spacing

1 L1 1 µH Inductor, power, 2.2-A, ±20% 0.120 inch (3.05 mm) × XFL3012-102MEB Coilcraft

0.120 inch (3.05 mm)

2 R1, R3 178 kΩResistor, chip, 1/16W, 1% 0603 Std Std

1 R2 39.2 kΩResistor, chip, 1/16W, 1% 0603 Std Std

1 R4 1 MΩResistor, chip, 1/16W, 1% 0603 Std Std

1 U1 TLV62080DSG IC, 1.2-A sync. step-down converter SON-8 TLV62080DSG TI

1 — Shunt, 100-mil (2,54-mm), black 0.1 929950-00 3M

1 — Label (see note 5) 1.25 inch (31,8 mm) × 0.25 THT-13-457-10 Brady

inch (6,35 mm)

1 — PCB, 1.8-inch (4,57-cm) × 1.8-inch HPA641 Any

(4,57-cm) × 0.031-inch (0.787-mm)

Notes: 1. These assemblies are ESD sensitive; ESD precautions must be observed.

2. These assemblies must be clean and free from flux and all contaminants. Use of no-clean flux is not acceptable.

3. These assemblies must comply with workmanship standards IPC-A-610 Class 2.

4. Place shunt on JP1-1/2 (ON)

5. Install label after final wash. Text shall be 8 pt font. Text shall be per Table 1.

Table 1

Assembly Text

Number

HPA756-001 TLV62080EVM-756

10 TLV62080, 1.2-A, High-Efficiency, Step-Down Converter in 2-mm × 2-mm SLVU640A–December 2011–Revised February 2014

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