Texas Instruments PCM4202EVM Manual de usuario

User's GuideSBAU103 – August 2004

PCM4202EVM User's Guide

This document provides the information needed to set up and operate thePCM4202EVM evaluation module (EVM). For a more detailed description of thePCM4202, please refer to the product datasheet available from the Texas Instrumentsweb site at http://www.ti.com. Additional support documents are listed in the sections ofthis guide entitled Related Documentation from Texas Instruments and AdditionalDocumentation. Throughout this document, the acronym EVM and the phraseevaluation module are synonymous with the PCM4202EVM. This user's guide includessetup and configuration instructions, information regarding absolute operating con-ditions for power supplies and input/output connections, an electrical schematic, PCBlayout drawings, and a bill of materials (BOM) for the EVM.

Contents1 Introduction ........................................................................................ 32 Getting Started ..................................................................................... 73 Hardware Description and Configuration .................................................... 84 Schematic, PCB Layout, and Bill of Materials ............................................. 13

List of Figures

1PCM4202 Functional Block Diagram .......................................................... 32PCM4202EVM Functional Block Diagram .................................................... 53DIT (Transmitter) Reset Circuitry ............................................................. 134PCM4202EVM Schematic Diagram ........................................................... 145Top Side Silkscreen ............................................................................. 166Bottom Side Silkscreen ........................................................................ 177Top Layer (Component Side) .................................................................. 188Ground Plane Layer ............................................................................. 199Power Plane Layer .............................................................................. 2010 Bottom Layer (Solder Side) .................................................................... 21

List of Tables

1Absolute Operating Conditions ................................................................ 82Audio Data Format Selection ................................................................... 93System Clock Source Selection .............................................................. 104Sampling Mode Selection: PCM Slave Mode Audio Formats .......................... 115Sampling Mode Selection: PCM Master Mode Audio Formats ......................... 116Sampling Mode Selection: DSD Output Mode ............................................. 117Digital High-Pass Filter Configuration ...................................................... 11

PCM4202EVM User's GuideSBAU103 – August 2004 1

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8Digital Interface Transmitter Configuration ................................................ 12

9Transmitter Master Clock Configuration.................................................... 12

10 Transmitter Output Mode Configuration.................................................... 12

11 PCM4202EVM Bill of Materials ................................................................ 22

PCM4202EVM User's Guide2 SBAU103– August 2004

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1 Introduction

Delta−Sigma

Modulator

Audio

Serial

Port

Clock

Control

VINR+

VINR−LRCK

or DSDBCK

BCK

or DSDL

DATA

or DSDR

CLIPR

CLIPL

Decimation

Filter

Voltage

Reference

NDR

VREFR

COMR

VCOML

Voltage

Reference

VREFL

GNDL

Delta−Sigma

Modulator

VINL−

VINL+

Power

VCC AGND VDD DGND

HPF

Decimation

Filter HPF

Reset

Logic

S/M

FMT0

FMT1

HPFD

FS0

FS1

FS2

SCKI

RST

Introduction

The PCM4202 is a high-performance, two-channel stereo audio analog-to-digital (A/D) converterdesigned for use in professional and broadcast audio applications. The PCM4202 featuressimultaneous 24-bit linear PCM or 1-bit Direct Stream Digital (DSD) data output for both channels.Sampling rates up to 216kHz are supported for PCM output formats, while 64x or 128xoversampled 1-bit data is supported for the DSD output mode. Native support for both PCM andDSD data formats makes the PCM4202 ideal for use in a variety of audio recording and processingapplications.

The PCM4202 features 1-bit delta-sigma (∆Σ) modulators employing a novel density modulateddithering scheme, yielding improved dynamic performance. Differential voltage inputs are utilizedfor the modulators, providing excellent common-mode rejection. On-chip voltage references areprovided for the modulators, in addition to generating DC common-mode bias voltage outputs foruse with external input circuitry. Linear phase digital decimation filtering is provided for the 24-bitPCM output, with a minimum stop band attenuation of -100dB for all sampling modes.

The PCM output mode features clipping flag outputs for each channel, as well as a digital high-passfilter for DC removal. The PCM4202 is configured using dedicated input pins for sampling modeand audio data format selection, high-pass filter enable/disable, and reset/power-down operation.

A +5V power supply is required for the analog section of the device, while a +3.3V power supply isrequired for the digital circuitry. Figure 1 shows the functional block diagram of the PCM4202.

Figure 1. PCM4202 Functional Block Diagram

PCM4202EVM User's GuideSBAU103 – August 2004 3

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1.1 PCM4204EVM Features

1.2 PCM4202EVM General Description and Functional Block Diagram

Introduction

The PCM4202EVM provides a convenient platform for evaluating the performance and functionalityof the PCM4202 product. The primary EVM features include:•Simple configuration using onboard DIP switches•Two differential voltage inputs supporting either 3-pin XLR or Balanced TRS connections•Low-noise input buffer circuits utilizing the OPA1632 fully differential audio amplifier•Two 75ΩAES3-encoded outputs, supporting operation up to 216kHz sampling rates•Buffered Audio Serial Port supports a two-channel, 24-bit linear PCM data interface for externalhardware and signal processors. Sampling rates up to 216kHz are supported.•Two onboard system clock oscillators, operating at 22.5792MHz and 24.576MHz respectively,supporting standard PCM sampling rates, including 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz,and 192kHz.•External system clock inputs supporting alternative sampling rates up to 216kHz.

The PCM4202EVM requires +15V, -15V, and +5V analog power supplies. Additionally, a +5V digitalpower supply is required, with a +3.3V digital supply being derived onboard using a linear voltageregulator IC.

The PCM4202EVM provides a complete platform for evaluating the performance and features ofthe PCM4202 stereo audio A/D converter. Figure 2 illustrates the functional block diagram for theevaluation module.

PCM4202EVM User's Guide4 SBAU103 – August 2004

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Left Channel

Input

Right Channel

Input

Analog

Input Buffers

OPA1632 x 2

PCM4202 BUF

S/M

PCM Data

Switch

SW1

Switch

SW3

GND

DIT Circuitry

+5VA

−15V+15V

BUF

DIT

U12

DIT4192

AES3 Out #1

Stereo: L + R

Mono: L

HDR J4

Audio

Serial Port

REG1117

+3.3V

+15

GND

−15

GND

+5VA

U13

DIT4192

AES3 Out #2

Stereo: L + R

Mono: R

22.5792M

EXT CLOCK INPUT

Switch

SW5

System

Clock

Clock Enables

24.576M

+5VD

GND

+3.3VD

+3.3V

JMP3

Introduction

Figure 2. PCM4202EVM Functional Block Diagram

Two differential analog inputs are supported at connectors J1 and J2, corresponding to Left andRight analog input channels, respectively. These connectors support either 3-pin male XLR orbalanced TRS input plugs. Each of the analog inputs is buffered and filtered using a low noise inputcircuit, utilizing a Texas Instruments OPA1632 fully differential amplifier. The output of each buffercircuit is connected to a corresponding differential input of the PCM4202. The PCM4202 is thenused to convert the analog signal to either a 24-bit linear PCM or 1-bit DSD representation in thedigital domain.

The 24-bit PCM or 1-bit DSD data output is made available at header J4. The 24-bit PCM audiodata is also made available at the AES3 encoded data outputs provided at RCA jacks J5 and J6.The buffered header is convenient for interfacing to external development hardware or digital signalprocessors, while the AES3 encoded outputs may be connected to audio test systems orcommercial audio equipment.

Power is connected to the board at either terminal block J3 for the analog supplies, or at terminalblock J8 for the digital supplies.

PCM4202EVM User's GuideSBAU103 – August 2004 5

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1.3 Related Documentation from Texas Instruments

1.4 Additional Documentation

Introduction

Manual reset circuits are provided for both the PCM4202 (U1) and the AES3 transmitters (U12 and

U13). The ADC RESET switch (SW2) is utilized for resetting the A/D converter, while the DIT

RESET switch (SW4) is utilized for resetting the AES3 transmitters.

The system or master clock for the evaluation module may be generated onboard or by an external

clock source. Oscillators X1 and X2 operate at fixed clock frequencies of 22.5792MHz and

24.576MHz, respectively. The oscillators provide low jitter clock sources for measuring the

performance of the PCM4202 in Master mode operation. Alternatively, an external clock source

may be connected at J7 for Master mode operation, supporting alternate system clock and

sampling frequencies. For Slave mode operation, the system clock is provided from an external

source through header J4 and buffer U9. Switch SW5 provides clock configuration control for the

oscillators and the external clock input at connector J7.

The following documents provide information regarding Texas Instrument integrated circuits used in

the assembly of the PCM4202EVM. The latest revisions of these documents are available from the

TI web site at http://www.ti.com.

Data Sheet Literature Number

PCM4202 Datasheet SBAS290

DIT4192 Datasheet SBOS229

OPA227 Datasheet SBOS110

OPA1632 Datasheet SBOS286

REG1117 Datasheet SBVS001

SN74AHC08 Datasheet SCLS236

SN74AHC14 Datasheet SCLS238

SN74ALVC245 Datasheet SCES271

SN74LVC1G125 Datasheet SCES223

The following documents or references provide information regarding selected non-TI components

used in the assembly of the PCM4202EVM. These documents are available from the corresponding

manufacturer.

Document/Reference Manufacturer

SM7745H Series CMOS Oscillators Pletronics ( http://www.pletronics.com )

6 SBAU103– August 2004PCM4202EVM User's Guide

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2 Getting Started

2.1 Electrostatic Discharge Warning

2.2 EVM Package Contents

2.3 Absolute Operating Conditions

Getting Started

This section provides information regarding handling and unpacking the PCM4202EVM, as well as

absolute operating conditions for the unit.

CAUTION

Failure to observe proper ESD handling precautions may result in damage to

EVM components.

Many of the components on the PCM4202EVM are susceptible to damage by electrostatic

discharge (ESD). Customers are advised to observe proper ESD handling procedure when

unpacking and handling the EVM, including the use of a grounded wrist strap at an approved ESD

workstation. Failure to observe ESD handling procedures may result in damage to EVM

components.

Upon opening the PCM4202EVM package, please check to make sure that the following items are

included:

·One PCM4202EVM

·One printed copy of the PCM4202 product datasheet

·One printed copy of this PCM4202EVM User's Guide

If any of these items are missing, please contact the Texas Instruments Product Information Center

nearest you to inquire about replacements.

CAUTION

Exceeding the absolute operating conditions may result in damage to the

evaluation module and/or the equipment connected to it.

The user should be aware of the absolute operating conditions for the PCM4202EVM. Table 1

summarizes the critical data points.

SBAU103– August 2004 PCM4202EVM User's Guide 7

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3 Hardware Description and Configuration

3.1 Power Supply Configuration

Hardware Description and Configuration

Table 1. Absolute Operating Conditions

Min Max Units

Power Supplies

+15V +5.0 +16.0 V

-15V -5.0 -16.0 V

+5VA +4.5 +5.5 V

+5VD +4.5 +5.5 V

EXT +3.3V +3.0 +3.6 V

Audio Serial Port (J4)

VIH, Input High Voltage (VDD = +3.0V to +3.6V) 0.7 x VDD VDD + 0.3 V

VIL, Input Low Voltage (VDD = +3.0V to +3.6V) -0.3 0.3 x VDD V

Analog Inputs (connectors J1 and J2)

Differential Input Voltage, RMS 7.9 V RMS

Differential Input Voltage, Peak-to-Peak 22.3 V PP

This section provides hardware description and configuration information for the PCM4202EVM.

The PCM4202EVM requires three analog power supplies and one digital power supply for

operation. The analog supplies are connected at terminal block J3, while the digital supply is

connected at terminal block J8.

Analog supplies include +15V and -15V DC for powering the input buffer circuits, as well as +5.0V

DC for powering the analog section of the PCM4202. All supplies should be rated for at least

500mA of output current.

The digital supply requires +5.0V DC and should be rated for at least 500mA of output current. The

+5.0V supply is regulated to +3.3V DC by an onboard Texas Instruments REG1117 linear voltage

regulator (U6), which is used to power the digital section of the PCM4202 and the majority of the

support logic circuitry. The core logic and line driver sections of the AES3 transmitters (U12 and

U13) utilize the +5.0V digital supply directly.

An optional external +3.3V DC digital power supply is supported at terminal block J8. Jumper JMP3

is utilized to select either the onboard voltage regulator (U6) or an external +3.3V power source.

Shorting pins 1 and 2 together using the supplied jumper block selects the onboard +3.3V voltage

regulator. Shorting pins 3 and 4 together will select the external +3.3V supply terminal (EXT

+3.3VD) on terminal block J14. Only one source may be selected at any time.

PCM4202EVM User's Guide8 SBAU103– August 2004

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3.2 Analog Inputs

3.3 Audio Data Format Selection

Hardware Description and Configuration

The PCM4202EVM includes two Neutrik combo XLR connectors, which accept either 3-pin male

XLR or ¼-inch TRS phono plugs. The connectors are numbered J1 and J2, corresponding to the

left and right channels, respectively.

The analog inputs can accept up to a 7.9VRMS (or 22.3V PP) differential input signal. This signal is

then attenuated by a factor of 3.7 by the input buffer circuit, which corresponds to the 6.0VPP

full-scale differential input voltage for the PCM4202 analog inputs.

The input buffer circuits are each comprised of a single OPA1632 fully differential audio amplifier

and associated passive components. The input buffer provides active attenuation and low pass

filtering for the analog input signal. The OPA1632 outputs are DC level-shifted by approximately

+2.5V using the amplifiers VCOMIN input (pin 2), which are connected to a buffered version of either

the PCM4202 VCOML (pin 3) or VCOMR outputs (pin 26).

Switch SW1 is used to select the audio data format for the PCM4202. Table 2 summarizes the

available audio data formats for both Slave and Master mode operation and the corresponding

SW1 switch settings.

Table 2. Audio Data Format Selection

FMT1 FMT0 Audio Data Format (Slave or Master Mode)

LO LO 24-Bit Left Justified PCM Data

LO HI 24-Bit I2S PCM Data

HI LO 24-Bit Right Justified PCM Data

HI HI DSD Output Mode (Master Mode only)

PCM4202EVM User's GuideSBAU103– August 2004 9

Master mode may also be configured to support 1-bit DSD-formatted audio output data, as shown

in Table 2. For the DSD mode formats, header J4 provides the output interface. The DATA output

functions as the RIght channel DSD output (DSDR), the BCK output servers as the left channel

DSD output (DSDL), and the LRCK output becomes the DSD bit clock (DSDBCK).

For Slave mode operation, the Audio Serial Port header (connector J4) is utilized to interface to a

Master device, such as a digital signal processor, FPGA, or an audio test system with a

synchronous serial port interface. The system clock (SCKI), bit clock (BCK), and left/right word

clock (LRCK) are generated by the Master device and are used to drive the SCKI (pin 18), BCK

(pin 16), and LRCK (pin 17) inputs of the PCM4202. Serial audio data is output at DATA (pin 15).

Slave mode supports PCM-formatted output data only. DSD output data is available only in

Master mode.

For Master mode, the system clock is provided by one of the sources described in Section 3.4 of

this document. The PCM4202 internally generates the BCK and LRCK clocks, which are then

output to the Audio Serial Port header (connector J4) and the AES3 digital interface transmitters,

which then drive output connectors J5 and J6.

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3.4 System Clock Configuration

3.5 Sampling Mode Selection

Hardware Description and Configuration

Switch SW5 is used to select the system clock source for the PCM4202EVM. Table 3 summarizesthe available clock source options. The onboard oscillators support standard PCM sampling rates inMaster mode, including 44.1kHz, 48kHz, 88.2kHz, 96kHz, 176.4kHz, and 192kHz. The externalclock input (connector J7) may be used to supply alternate system clock frequencies that supportalternative sample rates.

Table 3. System Clock Source Selection

Switch SW5

System Clock Source Used for Master or Slave Mode Operation?EXT OSC1 OSC0

LO LO LO External clock input at J7 MasterHI LO LO External clock input at the SCKI pin of header J4 SlaveHI LO HI Oscillator X1, 22.5792MHz MasterHI HI LO Oscillator X2, 22.576MHz Master

The sampling mode of the PCM4202 is selected using switch SW1. Table 4 through Table 6summarize the available sampling modes for both PCM and DSD output modes.

Single Rate sampling mode is designed for output sampling rates up to 54kHz. The modulatoroversampling rate is set to 128x.

Dual Rate sampling mode is designed for output sampling rates greater than 54kHz and up to108kHz. The modulator oversampling rate is set to 64x.

Quad Rate sampling mode is designed for output sampling rates greater than 108kHz and up to216kHz. The modulator oversampling rate is set to 32x.

10 PCM4202EVM User's Guide SBAU103 – August 2004

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