Texas Instruments PCIE16X-800EVK Manual de usuario

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PCIE16X-800EVK User Guide

PCIe 16X Lane Card Evaluation Kit

General Description:

The PCIE16X-800EVK is a PCIe add-in riser card for PCIe 16x applications. It provides a complete

platform to evaluate 4 - DS80PCI800SQ, 8 channels PCIe repeater for PCIe system protocol and lane

negotiation validation. The card has a 16X PCIe edge fingers at J1 which plugs into a motherboard

that has a PCIe 16X connector. The card also has a PCIe 16X connector at J2 for endpoint connection

(PCIe graphic card or SATA/SAS raid controller card).

Features:

■8 channel PCIe repeater up to 8 Gbps (GEN 3)

■Low power consumption, with option to power down unused channels

■Adjustable receive equalization

■Adjustable transmit VOD and De-emphasis

■IDLE detection — squelch function auto mutes the output

■Programmable via pin selection or SMBus interface

■Single supply operation: VIN = 3.3V±10% or VDD = 2.5V ±5%

■-40°C to +85°C Operation

■>6 kV HBM ESD Rating

■High speed signal flow–thru pin-out package - SQA54A: 54-pin LLP (10 mm x 5.5 mm, 0.5 mm pitch)

Applications:

■Extends FR-4 Backplane Trace for PCIe Applications

PCIE16X-800EVK Demo Kit Contents:

■End User License Agreement

■PCIE16X-800EVK User Guide Rev 1.2

■PCIE16X-800EVK Board

Odering Information:

SMA Evaluation Kit: PCIE16X-800EVK

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Figure 1. PCIE16X-800EVK Evaluation Board

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Table 1. Switches to set the 4-level input control pins

4 – level Input Settings Setting for 3 pin switches (3-2-1)

0 – Tie 249 ohm to GND ON – OFF – OFF

R – Tie 5k ohm to GND OFF – ON – OFF

F – FLOAT (open) OFF – OFF – OFF

1 – Tie 249 ohm to VIH OFF – OFF – ON

The following switches are used to set the input condition for the 4-level inputs:

SW1, SW2, SW3, SW5, SW6, SW10, SW11.

There are 3 switches connected to an input signal pin. Each switch when set to the ON position sets the pin to

one of the 4-level setting. The 6 pin switches are assigned similar to the 3 pin switches. The only difference is 2

signal pins are connected and thus 6-5-4 is for the one signal pin and 3-2-1 is for another signal pin. Please note

only 1 switch at the ON position is allowed.

Table 2. Connection and Control Description

Component Name Function

J1 PCIE TX/RX High speed differential TX/RX from/to Root Complex

J2 PCIE TX/RX High speed differential TX/RX to/from End Point

J3, J5 3.3V to VIN

3.3V DC Power – VIN to DS80PCI800SQ

Jumper ON = 3.3V mode operation

Jumper OFF = 2.5V mode operation

J4, J6 2.5V to VDD

2.5V DC Power – VDD to DS80PCI800SQ

Jumper ON (1-2, 3-4) = 2.5V mode operation

Jumper OFF (1-2, 3-4) = 3.3V mode operation

J7 VIN or VDD Jumper VIH: set 1-2 = VIN (3.3V) or set 2-3 = VDD (2.5V)

J8 SDA, SCL

Optional SMBUS access pins.

See the datasheet for additional information on SMBUS.

J9 EEPROM Optional socket for EEPROM

SW1

EQB[1:0] or

AD[3:2]

PIN MODE – EQ control for channel B inputs

SMBUS MODE – AD[3:2] device address bits

SW2

ENSMB

ENSMB = LOW – PIN MODE

ENSMB = HIGH – SMBUS (slave mode)

ENSMB = FLOAT – SMBUS (master mode – load configuration from EEPROM)

SW3

DEMA[1:0]

PIN MODE – DE control for channel A outputs

SW4 SDA/SCL “ON” position connects SDA and SCL lines to the device pin.

SW5

DEMB[1:0] or

AD[1:0]

PIN MODE – DE control for channel B outputs

SMBUS MODE – AD[1:0] device address bits

SW6 SD_TH and

LPBK - RES

SD_TH – Signal detect threshold level (FLOAT = Default level)

LPBK function for PCI402 and RESERVED for PCI800 (FLOAT = Normal operation)

SW7 VDD_SEL1_2

VDD_SEL3_4

VDD_SEL – Enable or disable the internal 3.3V to 2.5V regulator for U1 and U2.

ON connects to GND to enable the internal LDO regulator for 3.3V mode operation.

SW8

READ_EN,

RD_EN2,

RD_EN3 and

RD_EN4

For manual control of loading the external EEPROM and daisy chain the READ_EN

to the ALL_DONE pins.

Pin1 = ON connects the SW13 push button to the READ_EN of U1.

Pin2,3,4 = OFF

SW9

A_D1 to

RD_EN2 …

A_D3 to

RD_EN4

Pin1 = ON connects the ALL_DONE of U1 to READ_EN of U2.

Pin2 = ON connects the ALL_DONE of U2 to READ_EN of U3.

Pin3 = ON connects the ALL_DONE of U3 to READ_EN of U4.

Pin4 = OFF

SW10 RXDET and

RATE

RXDET – Input internal 50 ohm to VDD terminations

RXDET = F (AUTO RX Detect), RXDET = 1 (50 ohm input termination).

RATE = 0 (GEN1,2) = 2.5G / 5.0G.

RATE = R (GEN3) = 8.0G.

RATE = F (AUTO Detect). The RATE auto detect circuit requires the idle and active

signal which occurs during the link training negotiation.

SW11

EQA[1:0]

PIN MODE – EQ control for channel A inputs

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SW12 SDA/SCL to

SMCLK/SMDAT

“ON” connect the SDA/SCL bus to the PCIe SMCLK and SMDAT bus.

Default is “OFF”.

SW13 READ_EN

ENSMB = FLOAT – SMBUS (master mode – load configuration from EEPROM)

SW6: SD_TH becomes the READ_EN pin.

To start the loading at power up, set SW6 pin 3 to “ON” position (pull to GND).

To manually control the start, set SW6 to “OFF” position and set SW8 pin1 to “ON”

and pin2 to “OFF” position and push the SW13 button for the high to low transition to

start the loading. When the loading is complete the LEDs – D1 thru D4 light should

turn OFF.

SW14 PRSNT

“ON” connects the PCIe PRSNT signal to the device PRSNT pin.

For 16X, set all the switches to the “ON” position.

Quick Start User Guide:

1. Connect J1 – PCIe 16x edge finger to the motherboard (root complex)

2. Connect J2 - PCIe 16x connector to an add-in card (end point).

3. For 3.3V mode operation, set J3 jumper to ON and do not use J4 (leave jumper OFF).

For 2.5V mode operation, set J3 jumper to OFF and set J4 jumper to ON (1-2 and 3-4).

4. Set jumper – J7 for VIH connection to VIN (3.3V) or VDD (2.5V). Default is 1-2 set to ON for VIH = 3.3V.

5. Set SW7 – VDD_SEL1_2 and VDD_SEL3_4 to “ON” position for 3.3V mode operation.

6. Set the control pins for normal operation

SW10 – RXDET = F (continuous receiver detection): set switches (3-2-1) = (OFF-OFF-OFF).

RXDET = 1 (50 ohm input termination): set switches (3-2-1) = (OFF-OFF-ON).

SW10 – RATE = F (enable rate detection): set switches (6-5-4) to (OFF-OFF-OFF).

RATE = R (GEN3 mode): set switches (6-5-4) = (OFF-ON-OFF).

RATE = 0 (GEN1,2 mode): set switches (6-5-4) = (ON-OFF-OFF).

SW6 – SD_TH = F (default signal detect threshold level): set switches (3-2-1) = (OFF-OFF-OFF).

SW6 – LPBK - RES = F (normal operation): set switches (6-5-4) = (OFF-OFF-OFF).

SW8: Set switches to “OFF” position.

SW9: Set switches to “OFF” position.

SW14 – PRSNT = GND (enables the device): set switches to “ON” position.

5. Set the input equalization level.

For external pin mode control of the equalization level:

Set ENSMB = 0 (1kohm to GND) by using the SW2 (3-2-1) = (ON-OFF-OFF).

SW4 pin1,2 must be set to the OFF positions, so the SMBUS signals are disconnected.

Refer to Table 1 for information on the 3 switch settings for the 4 level input.

Example:

Set EQB[1:0] with SW1 for the B bank of inputs (top 2 left inputs of DS80PCI800).

SW1 (6-5-4),(3-2-1) = (OFF-ON-OFF), (OFF-ON-OFF) = EQB[1:0] = R,R = 14.6 dB at 4 GHz (level 6).

Set EQA[1:0] with SW11 for the A bank of inputs (bottom 2 left inputs of DS80PCI800).

SW8 (6-5-4),(3-2-1) = (OFF-ON-OFF), (OFF-ON-OFF) = EQA[1:0] = R,R = 14.6 dB at 4 GHz (level 6).

The table below is the 16 possible EQ settings when in pin mode.

Level EQA/B[1:0]

SW1 - EQB[1:0]

SW11 - EQA[1:0] EQ (dB) at 4 GHz

6 5 4 3 2 1

1 0, 0

ON OFF OFF ON OFF OFF 4.9

2 0, R

ON OFF OFF OFF ON OFF 7.9

3 0, F

ON OFF OFF OFF OFF OFF 9.9

4 0, 1

ON OFF OFF OFF OFF ON 11.0

5 R, 0 OFF

ON OFF ON OFF OFF 14.3

6 R, R OFF

ON OFF OFF ON OFF 14.6

7 R, F OFF

ON OFF OFF OFF OFF 17.0

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8 R ,1 OFF

ON OFF OFF OFF ON 18.5

9 F ,0 OFF OFF OFF

ON OFF OFF 18.0

10 F, R OFF OFF OFF OFF ON OFF 22.0

11 F, F OFF OFF OFF OFF OFF OFF 24.4

12 F, 1 OFF OFF OFF OFF OFF ON 25.8

13 1, 0 OFF OFF

ON ON OFF OFF 27.4

14 1, R OFF OFF

ON OFF ON OFF 29.0

15 1, F OFF OFF

ON OFF OFF OFF 31.4

16 1, 1 OFF OFF

ON OFF OFF ON 32.7

6. Set the output VOD and De-emphasis level.

For external pin mode control for the VOD and De-emphasis level (Gen1&2 only):

Set ENSMB = 0 (1kohm to GND) by using the SW2 (3-2-1) = (ON-OFF-OFF).

SW4 pin1,2 must be set to the OFF positions, so the SMBUS signals are disconnected.

Refer to Table 1 for information on the 3 switch settings for the 4 level input.

Example:

Set DEMB[1:0] with SW5 for the B bank of outputs (top 2 right outputs of DS80PCI800).

SW5 (6-5-4),(3-2-1) = (ON-OFF-OFF), (OFF-OFF-ON) = DEMB[1:0] = 0,1 (VOD=1.0V, DE=0 dB).

Set DEMA[1:0] with SW3 for the A bank of outputs (bottom 2 right outputs of DS80PCI800).

SW3 (6-5-4),(3-2-1) = (ON-OFF-OFF), (OFF-OFF-ON) = DEMA1:0] = 0,1 (VOD=1.0V, DE=0 dB).

The table below is the 16 possible settings of VOD and DE when in pin mode.

In Gen 1/2, the de-emphasis level can be set with the DEMx[1:0] pins, but is not available in Gen 3.

Level DEMA/B[1:0]

SW5 - DEMB[1:0]

SW3 - DEMA[1:0] GEN1,2

6 5 4 3 2 1 VOD (Vp-p) DE (dB)

1 0, 0

ON OFF OFF ON OFF OFF 0.8 0

2 0, R

ON OFF OFF OFF ON OFF 0.9 0

3 0, F

ON OFF OFF OFF OFF OFF 0.9 ‐3.5

4 0, 1

ON OFF OFF OFF OFF ON 1.0 0

5 R, 0 OFF

ON OFF ON OFF OFF 1.0 ‐3.5

6 R, R OFF

ON OFF OFF ON OFF 1.0 ‐6

7 R, F OFF

ON OFF OFF OFF OFF 1.1 0

8 R ,1 OFF

ON OFF OFF OFF ON 1.1 ‐3.5

9 F ,0 OFF OFF OFF ON OFF OFF 1.1 ‐6

10 F, R OFF OFF OFF OFF ON OFF 1.2 0

11 F, F OFF OFF OFF OFF OFF OFF 1.2 ‐3.5

12 F, 1 OFF OFF OFF OFF OFF ON 1.2 ‐6

13 1, 0 OFF OFF

ON ON OFF OFF 1.3 0

14 1, R OFF OFF

ON OFF ON OFF 1.3 ‐3.5

15 1, F OFF OFF

ON OFF OFF OFF 1.3 ‐6

16 1, 1 OFF OFF

ON OFF OFF ON 1.3 ‐9

For SMBUS mode control of the EQ, VOD and De-emphasis level:

Set ENSMB = 1 (1kohm to VIH) by using the SW2 (3-2-1) = (OFF-OFF-ON).

Set SW4 pin1,2 to the ON position so the SMBUS signals are connected.

Set SW3 pin1 thru pin6 switches to the OFF position so they do not connect to the SDA and SCL line.

Set the SW1 and SW5 for the AD[3:0] pins. AD[3:0]=0000 sets device slave address = B0’hex.

Connect SDA, SCL and GND to J17. Please refer to datasheet for register map for EQ, VOD and DEM.

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Document ID: PCIE16X-800EVK User Guide

Date: November, 2011

Rev: 1.2

D D

C C

B B

A A

9 1436415193614 5141

93614 5141 93614 5141

J3 (U1,U2):

1-2 (ON) FOR 3.3V,

1-2 (OFF) FOR 2.5V.

J4 (U1,U2):

1-2, 3-4 (ON) FOR 2.5V,

1-2, 3-4 (OFF) FOR 3.3V.

J5 (U3,U4):

1-2 (ON) FOR 3.3V,

1-2 (OFF) FOR 2.5V.

J6 (U3,U4):

1-2, 3-4 (ON) FOR 2.5V,

1-2, 3-4 (OFF) FOR

3.3V.

PLACE CLOSE TO PIN

PLACE CLOSE TO PIN PLACE CLOSE TO PIN

PLACE CLOSE TO PIN

DS80PCI800 PCIE 16X CARD PAGE 1 A

PCIE16X_800EVK

11Thursday, December 09, 2010

Title

Size Document Number Rev

Date: Sheet of

12V

GND

PETn4

PETp12

PETp5

PETn0

PRSNT2_3

GND

PETn9

GND

PETn3

SMCLK

GND

PETp13

GND

PETn15

GND

PETn8

3_3V

PETp7

GND

PETn11

RSV2

PETn14

GND

SMDAT

GND

RSVD2

GND

12V

GND

PRSNT2_4

PETn7

GND

WAKE

GND

PETp1

GND

PRSNT2_1

PETn10

3_3VAUX

PETp10

PRSNT2_2

PETp14

GND

PETp8

PETn12

GND

PETp6

PETp4

GND

PETp3

GND

PETn2

PETp9

RSVD1

GND

PETn5

GND

PETn1

PETp0

GND

12V

GND

JTAG1

PETp15

PETn6

PETp2

GND

PETn13

PETp11

GND

VDD1

PETp0

PETn0

PETn1

PETp1

PETp3

PETn3

PETn4

PETp4

PETp5

PETn5

PETn6

PETp6

PETn7

PETp7

PETn0_C

PETp0_C

PETn1_C

PETp1_C

PETp3_C

PETn3_C

PETn2_C

PETp2_C

PETn4_C

PETp4_C

PETp5_C

PETn5_C

PETn6_C

PETp6_C

PETp7_C

PETn7_C

EQA1

EQA0

RATE

RXDET

RES

VIN1_2

VDD_SEL1_2

SD_TH

A_D1

DEMA0_SDA

EQB0_AD3

EQB1_AD2

PRSNT

DEMA1_SCL

ENSMB

VDD1

GND

3_3V

GND

3_3V

VIN1_2

GND

VDD1

VDD2

VIN3_4

ENSMB

EQA1

PERn7_C

VDD4

RXDET

PERn0_C

VDD3

PERp5_C

PERn2_C

3_3V

RD_EN3

3_3V

RATE

PERp6_C

PERp0_C

VDD3

PERp4_C

VDD3

GND

PERp2_C

VDD_SEL3_4

EQA0

VOUT3_4

PRSNT

GND

PERn6_C

PERn4_C

VDD4

VIN3_4

PERp1_C

GND

VDD3

PERn5_C

PERn3_C

VDD3

PERp7_C

RES

PERn1_C

VDD3

GND

3_3V

PERp3_C

PETp2

PETn2

PERn0

PERn1

PERp0

PERp1

PERp2

PERp3

PERn3

PERn2

PERp4

PERn4

PERn5

PERp5

PERp6

PERp7

PERn6

PERn7

RXDET

PERn13

RES

VIN3_4

PERp10_C

PERp14_C

PERn8_C

VDD4

PERn9_C

PERp12

RATE

PERp12_C

PERp11_C

PERn12_C

EQA0

RD_EN4

VDD4

PERn13_C

PERn14

VDD4

PERp15_C

PERn11_C

PERn9

PERn14_C

PRSNT

VDD4

PERn11

PERp8_C

PERn12

PERp14

PERp13

PERp9

PERp15

PERp8

PERp10

PERn10

ENSMB

PERn15

VDD4

EQA1

PERn10_C

PERp11

PERn8

PERn15_C

PERp13_C

PERp9_C

VDD_SEL3_4

GND GND

GND

VOUT1_2

VDD1

VDD2

DEMB1_AD0

DEMB0_AD1

DEMA0_SDA

EQB1_AD2

DEMA1_SCL

EQB0_AD3

DEMB1_AD0

DEMB0_AD1

DEMA0_SDA

EQB1_AD2

DEMA1_SCL

EQB0_AD3

DEMB1_AD0

A_D3

GND

PERn8

12V

GND

REFCLKn

PERp2

PERn13

PERn5

3_3V

GND

PERST

PERp13

GND

RSVD3

PERn4

PERp11

GND

JTAG4

PERp0

PERn12

GND

REFCLKp

JTAG5

PERp4

GND

RSVD4

PERn1

PERn9

PERp15

PERn7

PERn3

GND

RSVD

PRSNT1

GND

PERp12

PERn14

PERn2

PERn0

PERp6

JTAG3

PERn15

PERn11

GND

RSVD5

PERp14

PERn10

GND

JTAG2

PERp10

PERp1

GND

PERp5

3_3V

GND

12V

PERn6

PERp3

PERp8

GND

PERp9

3_3VPERp7

PETn0_C

PETp14_C

GND

PRSNT2_1

GND

RSVD5

GND

JTAG4

PRSNT1

PETn5_C

PERn15_C

PETn8_C

RSVD2

GND

12V

GND

PERn9_C

PERn3_C

GND

PERp13_C

PETp5_C

PERn11_C

PERp11_C

PRSNT2_4

GND

3_3V

PERn10_C

PETp12_C

PETp15_C

GND

3_3V

GND

PETn1_C

PETp3_C

PERp3_C

PETn2_C

GND

RSVD1

GND

RSVD

PERp2_C

PETn3_C

PETp0_C

PERn2_C

PETp10_C

PERp1_C

PETp8_C

GND

PETp7_C

PETn12_C

PETp4_C

PERp6_C

PETp11_C

GND

12V

PERp0_C

PERn13_C

PERn12_C

GND

PRSNT2_3

SMCLK

GND

PETn11_C

PERp14_C

PERp10_C

PERp5_C

PERn14_C

GND

PERST

JTAG2

PERn5_C

PETn6_C

PERn1_C

PERn7_C

GND

SMDAT

12V

GND

JTAG3

PETn7_C

PETp9_C

PETn10_C

PERn4_C

JTAG1

12V

GND

RSVD3

REFCLKp

JTAG5

PERp8_C

PERp7_C

GND

PERn8_C

PETn15_C

PETn13_C

GND

RSVD4

GND

PETn4_C

PERp9_C

PERp15_C

GND

WAKE

GND

12V

PETp6_C

PERp12_C

PETp13_C

GND

3_3VAUX

GND

3_3V

PERp4_C

PRSNT2_2

RSV2

GND

REFCLKn

PETp2_C

PETn9_C

PETp1_C

PERn6_C

PETn14_C

GND

PERn0_C

VDD_SEL1_2

VDD2

PETp9

VDD2

PETn12_C

VDD2

DEMA0_SDA

RATE

PETp11

PETp11_C

A_D2

PETn14

PETn13

PETn12

GND

RXDET

PETn13_C

VIN1_2

GND

EQB0_AD3

DEMB1_AD0

VDD2

PETp9_C

RD_EN2

PETn11

DEMB0_AD1

PETn10_C

PETp14_C

PETn11_C

PETp13_C

PETn8_C

PETp8

ENSMB

PETn9_C

PETp12

DEMA1_SCL

VDD2

PETp10_C

PETp8_C

RES

PETn10

PETn9

PETn15_C

EQA0

GND

PRSNT

PETp12_C

PETp15

PETp14

PETp15_C

PETn15

PETp13

PETp10

EQB1_AD2

PETn14_C

EQA1

PETn8

RD_EN3

A_D2

RD_EN2

A_D1

A_D3

SD_TH

SMDAT

RD_EN4

SMCLKPRSNT2_1

PRSNT2_2

PRSNT2_3

PRSNT2_4

VOUT1_2

A_D4

EQA0

EQB1_AD2

VDD_SEL1_2

VDD_SEL3_4

GND

DEMA1_SCL

DEMA0_SDA

EQA1

EQB0_AD3

GND

PRSNT

ENSMB

DEMB0_AD1

RES

GND

RXDET

DEMB1_AD0

RATE

3_3V

SMDAT

RD_EN4

SMCLK

SD_TH

A_D2

A_D1

RD_EN2

A_D3

RD_EN3

PRSNT2_1

PRSNT2_4

PRSNT2_3

PRSNT2_2

VOUT1_2

A_D4

RES

EQB1_AD2

RATE

DEMA0_SDA

ENSMB

RXDET

VDD_SEL1_2

EQA0

EQB0_AD3

DEMA1_SCL

VDD_SEL3_4

DEMB1_AD0

EQA1

PRSNT

DEMB0_AD1

3_3V

4 HEADER

C15

0.1uF

C1010.22uF

C28 10uF

C47 0.22uF

4 HEADER

51k C1080.22uF

C1220.22uF

SML-P12PTT86

C1040.22uF

C84 0.22uF

DS80PCI800

IB_0+

IB_0-

IB_1+

IB_1-

IB_2+

IB_2-

IB_3+

IB_3-

VDD

IA_0+

IA_0-

IA_1+

IA_1-

VDD

IA_2+

IA_2-

IA_3+

IA_3-

EQA1

EQA0

RATE

RXDET

RES

VIN

VDD_SEL

SD_TH/RD_EN

ALL_DONE

OB_0+

OB_0-

OB_1+

OB_1-

VDD

OB_2+

OB_2-

OB_3+

OB_3-

VDD

OA_0+

OA_0-

OA_1+

OA_1-

OA_2+

OA_2-

OA_3+

OA_3-

DEMB1/AD0

DEMB0/AD1

/PRSNT

VDD

DEMA1/SCL

DEMA0/SDA

ENSMB

EQB1/AD2

EQB0/AD3

DAP

C66 0.22uF

C56 0.22uF

0.1uF

C36 0.22uF

C98 0.22uF

C1300.22uF

C1560.22uF

C93 0.22uF

R4 1.5k

C75 0.22uF

C1340.22uF

C1120.22uF

C1520.22uF

C1200.22uF

C57 0.22uF

51k

SML-P12PTT86

C44 0.22uF

C1380.22uF

2 HEADER

C31 0.22uF

LP3878-ADJ

4 5

BYPASS

NC1

GND

INPUT OUTPUT

ADJ

NC2

S_DWN

DAP

C88 0.22uF

C70 0.22uF

C1330.22uF

C45 0.22uF

C33 0.22uF

C10

0.1uF

C79 0.22uF

C1000.22uF

R1 1.5k

DS80PCI800

IB_0+

IB_0-

IB_1+

IB_1-

IB_2+

IB_2-

IB_3+

IB_3-

VDD

IA_0+

IA_0-

IA_1+

IA_1-

VDD

IA_2+

IA_2-

IA_3+

IA_3-

EQA1

EQA0

RATE

RXDET

RES

VIN

VDD_SEL

SD_TH/RD_EN

ALL_DONE

OB_0+

OB_0-

OB_1+

OB_1-

VDD

OB_2+

OB_2-

OB_3+

OB_3-

VDD

OA_0+

OA_0-

OA_1+

OA_1-

OA_2+

OA_2-

OA_3+

OA_3-

DEMB1/AD0

DEMB0/AD1

/PRSNT

VDD

DEMA1/SCL

DEMA0/SDA

ENSMB

EQB1/AD2

EQB0/AD3

DAP

C38 0.22uF

C1070.22uF

C1530.22uF

C54 0.22uF

C161

1uF

C1350.22uF

C1150.22uF

C92 0.22uF

C16

0.1uF

C1450.22uF

C74 0.22uF

C19

0.1uF

C1480.22uF

0.1uF

C55 0.22uF

C1260.22uF

C83 0.22uF

C95 0.22uF

C65 0.22uF

C1440.22uF

C1090.22uF

C1490.22uF

C1360.22uF

C160

1uF

C18

0.1uF

R10

220

C43 0.22uF

C39 0.22uF

C25

0.01uF

C40 0.22uF

C78 0.22uF

220

C1230.22uF

C87 0.22uF

C52 0.22uF

C1470.22uF

C69 0.22uF

C12

0.1uF

C1130.22uF

C21

10uF

C96 0.22uF

C97 0.22uF

220

C13

0.1uF

C53 0.22uF

C1190.22uF

0.1uF

C82 0.22uF

C11

0.1uF

C29 1nF

C35 0.22uF

C1160.22uF

C64 0.22uF

C1020.22uF

PCIE_16X_EDGE_FINGER

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A32

A33

A34

A35

A36

A37

A38

A39

A40

A41

A42

A43

A44

A45

A46

A47

A48

A49

A50

A51

A52

A53

A54

A55

A56

A57

A58

A59

A60

A61

A62

A63

A64

A65

A66

A67

A68

A69

A70

A71

A72

A73

A74

A75

A76

A77

A78

A79

A80

A81

A82

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

B32

B33

B34

B35

B36

B37

B38

B39

B40

B41

B42

B43

B44

B45

B46

B47

B48

B49

B50

B51

B52

B53

B54

B55

B56

B57

B58

B59

B60

B61

B62

B63

B64

B65

B66

B67

B68

B69

B70

B71

B72

B73

B74

B75

B76

B77

B78

B79

B80

B81

B82

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A32

A33

A34

A35

A36

A37

A38

A39

A40

A41

A42

A43

A44

A45

A46

A47

A48

A49

A50

A51

A52

A53

A54

A55

A56

A57

A58

A59

A60

A61

A62

A63

A64

A65

A66

A67

A68

A69

A70

A71

A72

A73

A74

A75

A76

A77

A78

A79

A80

A81

A82

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

B32

B33

B34

B35

B36

B37

B38

B39

B40

B41

B42

B43

B44

B45

B46

B47

B48

B49

B50

B51

B52

B53

B54

B55

B56

B57

B58

B59

B60

B61

B62

B63

B64

B65

B66

B67

B68

B69

B70

B71

B72

B73

B74

B75

B76

B77

B78

B79

B80

B81

B82

C1400.22uF

C91 0.22uF

C1290.22uF

C62 0.22uF

C73 0.22uF

DS80PCI800

IB_0+

IB_0-

IB_1+

IB_1-

IB_2+

IB_2-

IB_3+

IB_3-

VDD

IA_0+

IA_0-

IA_1+

IA_1-

VDD

IA_2+

IA_2-

IA_3+

IA_3-

EQA1

EQA0

RATE

RXDET

RES

VIN

VDD_SEL

SD_TH/RD_EN

ALL_DONE

OB_0+

OB_0-

OB_1+

OB_1-

VDD

OB_2+

OB_2-

OB_3+

OB_3-

VDD

OA_0+

OA_0-

OA_1+

OA_1-

OA_2+

OA_2-

OA_3+

OA_3-

DEMB1/AD0

DEMB0/AD1

/PRSNT

VDD

DEMA1/SCL

DEMA0/SDA

ENSMB

EQB1/AD2

EQB0/AD3

DAP

C1540.22uF

C42 0.22uF

SML-P12PTT86

C20

0.1uF

C50 0.22uF

C1210.22uF

C1240.22uF

C86 0.22uF

C68 0.22uF

C1050.22uF

C37 0.22uF

C77 0.22uF

C99 0.22uF

C27 10uF

C1270.22uF

C51 0.22uF

C1430.22uF

C1570.22uF

C1110.22uF

0.1uF

C1180.22uF

DS80PCI800

IB_0+

IB_0-

IB_1+

IB_1-

IB_2+

IB_2-

IB_3+

IB_3-

VDD

IA_0+

IA_0-

IA_1+

IA_1-

VDD

IA_2+

IA_2-

IA_3+

IA_3-

EQA1

EQA0

RATE

RXDET

RES

VIN

VDD_SEL

SD_TH/RD_EN

ALL_DONE

OB_0+

OB_0-

OB_1+

OB_1-

VDD

OB_2+

OB_2-

OB_3+

OB_3-

VDD

OA_0+

OA_0-

OA_1+

OA_1-

OA_2+

OA_2-

OA_3+

OA_3-

DEMB1/AD0

DEMB0/AD1

/PRSNT

VDD

DEMA1/SCL

DEMA0/SDA

ENSMB

EQB1/AD2

EQB0/AD3

DAP

NWE82DHRN-T9410

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A32

A33

A34

A35

A36

A37

A38

A39

A40

A41

A42

A43

A44

A45

A46

A47

A48

A49

A50

A51

A52

A53

A54

A55

A56

A57

A58

A59

A60

A61

A62

A63

A64

A65

A66

A67

A68

A69

A70

A71

A72

A73

A74

A75

A76

A77

A78

A79

A80

A81

A82

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

B32

B33

B34

B35

B36

B37

B38

B39

B40

B41

B42

B43

B44

B45

B46

B47

B48

B49

B50

B51

B52

B53

B54

B55

B56

B57

B58

B59

B60

B61

B62

B63

B64

B65

B66

B67

B68

B69

B70

B71

B72

B73

B74

B75

B76

B77

B78

B79

B80

B81

B82

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

A21

A22

A23

A24

A25

A26

A27

A28

A29

A30

A31

A32

A33

A34

A35

A36

A37

A38

A39

A40

A41

A42

A43

A44

A45

A46

A47

A48

A49

A50

A51

A52

A53

A54

A55

A56

A57

A58

A59

A60

A61

A62

A63

A64

A65

A66

A67

A68

A69

A70

A71

A72

A73

A74

A75

A76

A77

A78

A79

A80

A81

A82

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

B21

B22

B23

B24

B25

B26

B27

B28

B29

B30

B31

B32

B33

B34

B35

B36

B37

B38

B39

B40

B41

B42

B43

B44

B45

B46

B47

B48

B49

B50

B51

B52

B53

B54

B55

B56

B57

B58

B59

B60

B61

B62

B63

B64

B65

B66

B67

B68

B69

B70

B71

B72

B73

B74

B75

B76

B77

B78

B79

B80

B81

B82

C22

10uF

C26

0.01uF

C17

0.1uF

C60 0.22uF

C90 0.22uF

C1100.22uF

C72 0.22uF

C1140.22uF

C14

0.1uF

C1510.22uF

C1460.22uF

C1250.22uF

C81 0.22uF

C63 0.22uF

C1030.22uF

C61 0.22uF

C48 0.22uF

C24

4.7uF

C1310.22uF

C1370.22uF

C1550.22uF

C23

4.7uF

C94 0.22uF

0.1uF

C1170.22uF

C76 0.22uF

C1320.22uF

C49 0.22uF

C30 1nF

C85 0.22uF

C67 0.22uF

C58 0.22uF

C1580.22uF

C1390.22uF

C32 0.22uF

C1280.22uF

220

C1060.22uF

LP3878-ADJ

4 5

BYPASS

NC1

GND

INPUT OUTPUT

ADJ

NC2

S_DWN

DAP

C34 0.22uF

C1420.22uF

C80 0.22uF

C59 0.22uF

SML-P12PTT86

C1410.22uF

C46 0.22uF

0.1uF

C41 0.22uF

C89 0.22uF

2 HEADER

C71 0.22uF

C1500.22uF

D D

C C

B B

A A

PLACE ALL Rs CLOSE TO SW

SW IN THE OFF POSITION = OPEN

ONOFF

OFF ON

OFF ON OFF ON

OFF ON

PIN MODE SETTINGS:

SW1 - EQB0, EQB1

SW2 - ENSMB = 1K TO GND

SW3 - DEMA0, DEMA1

SW4 - OFF POSITION

SW5 - DEMB0, DEMB1

SW6 - SD_TH, RES

SW7 - ON (GND) FOR 3.3V

SW8 - RD_EN2-4=ON (SD_TH)

SW9 - OFF POSTION

SW10 - RXDET, RATE

SW11 - EQA0, EQA1

SW12 - OFF POSITION

SW13 - OFF POSITION

SW14 - PRSNT2_4=ON

SMBUS SLAVE MODE SETTINGS:

SW1 - AD3, AD2

SW2 - ENSMB = 1K TO VDD

SW3 - OFF POSTION

SW4 - ON POSTION (SDA, SCL)

SW5 - AD1, AD0

SW6 - SD_TH, RES

SW7 - ON (GND) FOR 3.3V

SW8 - RD_EN2-4=ON (SD_TH)

SW9 - OFF POSTION

SW10 - RXDET, RATE

SW11 - EQA0, EQA1

SW12 - OFF POSITION WHEN USING SPA BOARD

SW13 - OFF POSTION

SW14 - PRSNT2_4=ON

PIN 1-2 FOR 3.3V

PIN 2-3 FOR 2.5V

SMBUS MASTER (READ EEPROM) MODE SETTINGS:

SW1 - AD3, AD2

SW2 - ENSMB = FLOAT

SW3 - OFF POSTION

SW4 - ON POSTION (SDA, SCL)

SW5 - AD1, AD0

SW6 - OFF POSITION

SW7 - ON (GND) FOR 3.3V

SW8 - SD_TH=ON, RD_EN2-4=OFF

SW9 - ON POSTION (ALL_DONE TO RD_EN, ALL_DONE4 TO PRSNT)

SW10 - RXDET, RATE

SW11 - EQA0, EQA1

SW12 - OFF POSITION

SW13 - GND TO START THE READ PROCESS

SW14 - OFF POSITION

ONOFF

FOR 16X LANES

SET PRSNT TO PRSNT2_4

ONOFF

DS80PCI800 PCIE 16X CARD PAGE 2 A

PCIE16X_800EVK

11Thursday, January 06, 2011

Title

Size Document Number Rev

Date: Sheet of

GND

VIH

GND

VIH

EQB0_AD3

EQB1_AD2

ENSMB

VIH

GND

DEMA0_SDA

VIH

DEMA1_SCL

VIH

GND

EQA0

VIH

EQA1

RXDET

GND

VIH

GND

RATE

VIH

RES

DEMB1_AD0

GND

VIH

GND

VIH

DEMB0_AD1

SCL

SDA

GND

SDA

GND

SCL

GND

3_3V

VOUT1_2

VIH

GND

VIH

RD_EN2

RD_EN3

RD_EN4

A_D1

A_D2

A_D3

RD_EN2

RD_EN4

RD_EN3

SD_TH

SCL

SDA

SMCLK

SMDAT

PRSNT2_4

PRSNT

PRSNT2_3

PRSNT2_2

PRSNT2_1

DEMA0_SDA

EQB0_AD3

RXDET

PRSNT

DEMA1_SCL

DEMB0_AD1

EQA1

RES

EQA0

ENSMB

DEMB1_AD0

RATE

EQB1_AD2

RD_EN3

SD_TH

A_D2

SMDAT

RD_EN4

A_D3

A_D1

RD_EN2

SMCLK

PRSNT2_1

PRSNT2_3

PRSNT2_4

PRSNT2_2

VDD_SEL1_2

VDD_SEL3_4

VDD_SEL1_2

VDD_SEL3_4

GND

VOUT1_2

A_D4PRSNT

A_D4

SCL

SDA

VIH

3_3V

PRSNT

DEMA0_SDA

RXDET

DEMB0_AD1

EQB0_AD3

EQB1_AD2

RATE

DEMB1_AD0

EQA0

ENSMB

EQA1

RES

DEMA1_SCL

RD_EN4

SMDAT

SMCLK

RD_EN3

A_D2

SD_TH

A_D3

RD_EN2

A_D1

PRSNT2_1

PRSNT2_2

PRSNT2_4

PRSNT2_3

VDD_SEL1_2

VDD_SEL3_4

VOUT1_2

A_D4

3_3V

R56

R27 4.99k

SW4

219-2MST

R20 249

SW5

219-6MST

R49 249

SW14

219-4MST

R19 249

R37 249

R23 249

R35 249

R41 249

4808-3004-CP

R29 249

R44 249

R12 4.99k

SW1

219-6MST

R14 249

R51 1k

SW6

219-6MST

SW7

219-2MST

R40 249

R36 4.99k

R26 249

R28 249

R17 249

SW11

219-6MST

SW3

219-6MST

4 HEADER

R45 4.99k

R54

R46 249

SW13

EVQ-21505R

R34 249

R16 249

R15 4.99k

R47 249

R39 4.99k

3 HEADER

R32 249

R31 249

R24 4.99k

R25 249

R21 4.99k

SW2

219-3MST

R53

R48 4.99k

R55

R22 249

R11 249

R50 1k

R13 249

SW10

219-6MST

R52 1k

R38 249

SW8

219-4MST

R42 4.99k

R18 4.99k

R30 4.99k

SW12

219-2MST

R43 249

SW9

219-4MST

R33 4.99k

Tabla de contenidos

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