Texas Instruments Bq76PL536A Manual de usuario

User's Guide

SLUU437D–October 2010–Revised July 2015

bq76PL536A and bq76PL536A-Q1 EVM Quick Start Guide

1 Scope

This document covers the initial connection and installation of the Texas Instruments bq76PL536A and

bq76PL536A-Q1 Evaluation Module (EVM), supplied in kit form including the EVM board, the Aardvark

USB-SPI adapter, and the connectors to make cells-to-EVM connection. While the EVM includes only

bq76PL536A devices, given the very small difference in features between the bq76PL536A and the

bq76PL536A-Q1, the EVM can also be used to evaluate the bq76PL536A-Q1. The bq76PL536 EVM

Quick Start Guide is not meant as a comprehensive guide to using the bq76PL536A and bq76PL536A-Q1

integrated circuits (ICs) and their features. See the corresponding device data sheets for details

(SLUSAD3 and SLUSAM3).

2 Software Installation

2.1 PC Requirements

1. Pentium®1.66GHz (Core™2 or better recommended)

2. Windows®.NET™ 2.0 or later, with updates

3. Available USB powered-port (hub OK, if wall adapter used)

2.2 Installing the Aardvark Driver

CAUTION

The Aardvark driver must be installed before attaching the adapter for the first

time.

The Aardvark driver should be installed prior to installing the TI supplied bq76PL536A and bq76PL536A-

Q1 Evaluation software.

1. Download the USB Drivers - Windows from the Aardvark web site,

http://www.totalphase.com/downloads#aardvark.

2. Select USB Drivers - Windows.

3. A window will open, then select the USB Drivers - Windows vXXX link under Download Software Here.

A registration may be necessary.

4. Go to the location where the file was downloaded and run the file

"Tools/Aardvark/Drivers/TotalPhaseUSB-v2.xx.exe" to install the drivers.

5. If prompted to do so, plug in the Aardvark to an available USB port using the supplied cable. The port

must be a powered-port, typically directly from a PC. Use of a USB non-powered hub may not provide

sufficient operating current for the Aardvark or the EVM to operate correctly.

Pentium is a registered trademark of Intel Corporation.

.NET is a trademark of Microsoft Corporation.

Windows is a registered trademark of Microsoft Corporation.

All other trademarks are the property of their respective owners.

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Software Installation

www.ti.com

2.3 Installing the bq76PL536A and bq76PL536A-Q1 Evaluation Software

Download the bq76PL536A and bq76PL536A-Q1 Evaluation Software from the tool folder on TI.com

located here: http://www.ti.com/tool/BQ76PL536EVM-3-SW.

Run the file "Software/bq76PL536 Evaluation Software x_x_x.msi" to install, where the "x_x_x" indicates

the current build number. Installation is automatic. This process installs the GUI (Graphical User Interface)

software for Windows. As new versions are released, this process may install over the existing version.

3 EVM Assembly and Configuration

3.1 Configure the Isolated Communications Interface

3.1.1 5-V Versus 3.3-V Selection

In the ISO-COMMS section of the PCB, there are two jumpers. JP5 selects 5-V or 3.3-V I/O operation

across the isolation boundary. The Aardvark adapter supplied with the EVM uses 3.3-V logic, but is 5-V

tolerant. JP5 should be configured for 3.3-V operation with the supplied Aardvark interface adapter,

although either position will work correctly. For connection to a user supplied microcontroller, select the

appropriate voltage.

3.1.2 Use USB Power from Aardvark

JP1 selects power from the USB connection through the Aardvark when installed in the “USB” position.

3.2 Configure the EVM Board

3.2.1 Use with Cells

Remove jumpers JP1-18 (18) located near the black battery connectors P1-P3 to reduce the current draw

of the board. It is OK to leave the jumpers in place; they connect a 1K precision resistor between each

adjacent pair of cell inputs and are supplied to use the EVM with power supplies in place of cells (see Use

with ~12-26-VDC Power Supply).

Connect cells to the supplied mating connectors with screw terminals BEFORE plugging the connector

into the EVM at P1, the large black connector on the left edge of the board. The most negative cell

connects to the most bottom of the black connector (P1).

The bottom-most pin of the battery connector is the most negative connection to the board from the

battery stack. This is the negative terminal of cell 1. The next pin in the connector is the positive terminal

of cell 1 (and the negative terminal of cell 2). The connections proceed in this fashion up the connector to

pin 7, which is the most positive terminal from the battery stack connected to each IC. Pin 7 of P1 (P1.7)

is connected to P2.1 on the board. The same is true of P2.7 and P3.1. P3.7 is connected to the top of the

PCB (most positive voltage), while P1.1 is connected to the bottom of the PCB (most negative voltage).

The battery connections should be made secure. A loose connection may result in device destruction.

Ideally, the cells are connected to one another by secure means such as welding, and only tap points are

brought over to the EVM from each cell-to-cell interconnection.

Although the device is immune to the effects of a random connection sequence, the ideal connection

sequence is from pin P1.1 to pin 3.7 in order.

TI recommends that users unfamiliar with the EVM and/or li-ion cells begin by using power supplies as

outlined in the next section.

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EVM Assembly and Configuration

3.2.2 Use with ~12-26-VDC Power Supply

Important: Install jumpers JP1-18 (18) located near the black battery connectors P1-P3 before connecting

power supplies. These jumpers connect a precision 0.1% resistor divider network between cell

connections.

Connect an appropriate power supply capable of supplying 12-26-VDC to connector P1, then plug P1 into

the EVM connector. Any voltage that meets the IC requirements will work; a voltage of 18-24 V is typical

of most six-cell systems. Plug additional supplies into P2 and P3. The supplies must be isolated from each

other and from earth ground to avoid unintentional short circuits. A separate supply is required for each

IC (each cell-connection plug).

The supply negative connection is made to pin 1 of the mating connector, the pin that will connect to the

bottom-most pin of the mating connector. The positive connection is made to pin 7, the top-most on the

connector. It is not necessary to connect to the intermediate pins due to the resistive divider on the EVM

which was enabled when JP1-18 were installed

CAUTION

Do not remove any of the jumpers JP1-18 while using the EVM in this

configuration. Lethal DC voltages may be present for these configurations.

Contact with these voltages may result in serious injury or death. Use

appropriate safety precautions.

External Power Supply Requirements:

• Nominal Voltage: 18 VDC

• Maximum Current: 50 mA

• Efficiency Level V

NOTE: TI recommends using an external power supply that complies with applicable regional safety

standards such as (by example) UL, CSA, VDE, CCC, PSE, etc.

SLUU437D–October 2010–Revised July 2015 bq76PL536A and bq76PL536A-Q1 EVM Quick Start Guide

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54V

Power Supply

bq76PL536EVM-3

Jumpers

Installed

10

18V

220µF

63V

10

18V

220µF

63V

10

18V

220µF

63V

54V

20V

Power Supply

20V

Power Supply

20V

Power Supply

bq76PL536EVM-3

Jumpers

Installed

(+) and (±) outputs

must remain isolated

from earth ground.

EVM Assembly and Configuration

www.ti.com

Figure 1. Correct Connection of Three ~20-V Power Supplies to bq76PL536EVM-3

Figure 2. Alternate Connection for a Single 54-V Supply

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60V

Power Supply

bq76pl536EVM-3

Jumpers

Installed

Resistor divider

(18K) does not

supply sufficient

current to ICs

60V

Power Supply

bq76PL536EVM-3

Jumpers

Installed

Resistor divider

(18K) does not

supply sufficient

current to ICs

Base IC must be

powered!

www.ti.com

EVM Assembly and Configuration

Figure 3. Incorrect Connections, Base IC Not Powered

Figure 4. Incorrect Connections, Insufficient VBAT Per IC

SLUU437D–October 2010–Revised July 2015 bq76PL536A and bq76PL536A-Q1 EVM Quick Start Guide

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60V

Power Supply

bq76PL536EVM-3

Jumpers

Installed

Resistor divider

(18K) does not

supply sufficient

current to ICs

EVM Assembly and Configuration

www.ti.com

Figure 5. Incorrect Connections, Top IC Not Powered, IC1, 2 Insufficient VBAT

3.3 Non-Critical Hardware Testing or Firmware Development

3.3.1 Stacking EVMs

For casual testing, one or two devices may be powered (in order from negative to positive) in lieu of

powering all three devices. Due to poor termination of the unpowered devices in this configuration,

detailed testing or critical hardware evaluations should not be undertaken. Any odd behavior or

unexpected fault conditions should be ignored until verified with the EVM correctly powered by three

isolated supplies.

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Connecting the EVM

4 Connecting the EVM

4.1 Connection Order

Figure 6. bq76PL536EVM-3

(a) Configure the EVM jumpers per Section 3.1.

(b) Connect the EVM to the Power Supplies or cells, turn on the supplies at ~12-to-24 V is recommended.

The Absolute Maximum voltage per IC is 36 V and should not be exceeded, 30 V is the recommended

maximum continuous voltage.

(d) Connect the Aardvark ribbon cable to the 10-pin header on the EVM board.

(e) Start the WinGUI User Interface software supplied with the EVM and installed earlier.

4.2 Connection Notes

The ISO-COMMS section of the EVM board isolates the EVM side voltages completely from the PC side.

It isolates all power, ground, and signal lines to the EVM. Caution must still be taken when using the EVM

as part of a stack, where lethal voltages may be present. The galvanic isolation provided by the ISO-

COMMS section does not eliminate the need for safe handling procedures, proper High-Voltage

equipment, and protective clothing. Proper safety procedures should always be followed.

Because the ISO-COMMS circuit section fully isolates the PC, Aardvark, and wall adapter from the EVM

“battery” side, the Aardvark is insensitive to the powering of the EVM, which receives its power from the

battery cells or power supply used for evaluation.

The grounds (VSS) are fully isolated; please keep this in mind when using an oscilloscope or meter. Do

not inadvertently connect the EVM VSS to the PC/Aardvark VSS by connecting two probe grounds or

otherwise forming a ground loop through external wiring, including the building wiring.

SLUU437D–October 2010–Revised July 2015 bq76PL536A and bq76PL536A-Q1 EVM Quick Start Guide

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Connecting the EVM

www.ti.com

4.3 Quick Check

The first step in communicating with the bq76PL536A is to set a unique address for each device in a

stack. This is required even if you are only using a single device. This occurs automatically when the

Evaluation software is first started. To do this manually, select COMMAND | AUTO ADDRESS (shortcut

key CTRL + A). This will cause the software to interrogate the stack of bq76PL536A devices, find all

available devices, and assign each a unique address beginning with address 0x01. Address 0x00 is

reserved for un-addressed devices.

After addressing is complete, you should see the number of devices found and the total combined voltage

of all cells being monitoring displayed in the STACK HEIGHT and V STACK windows.

5 Evaluation Software Details

5.1 Main Screen

The main screen is divided into four major areas, plus the menu and status bars. The software is referred

to as the “Windows Graphical User Interface”, or abbreviated to WinGUI.

VBRICK The voltage measured by the bq76PL536A between the BATx and VSS pins

VCELLn The voltage measured between the pair of pins VCn – VCn-1 (that is, VCELL2 =

VC2 – VC1).

ADDR Displays the address of the device being monitored in the measurement result area.

LOG DEVICE Checking this box will add the contents of the device at this address to the log file.

TSn The voltage measured between the TSn+ and TSn- inputs, converted by the WinGUI

to temperature based on the characteristics of the thermistor used in the EVM design.

The EVM and WinGUI are configured to measure this voltage as a ratio of REG50,

which removes any offset or gain errors introduced by drift in the REG50 output.

VIEW AS... Shows the ratio of the measured input voltage to REG50 as a percentage.

Refresh updates the displayed measurements for this device. The conversion is

started by sending the register command CONVERT[CONV]=1, or hardware by

toggling the CONV pin if the HW IO CONTROL box is checked.

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Evaluation Software Details

5.1.1 Volatile RAM Configuration Registers –

The lower half of this area displays the volatile configuration registers shown as bit fields, see the

bq76PL536A or bq76PL536A-Q1 data sheet for details on programming these registers. These registers

display green for logic 0 and orange for logic 1. The two states may be toggled between by left-clicking on

the bit

The STATUS, COV_FAULT, and CUV_FAULT bits are either white (logic 0) or red (logic 1) for asserted.

In most cases, the asserted state indicates an error condition sensed by the bq76PL536A.

To clear a fault, first remove the physical condition causing the fault, then click on the ALERT or FAULT

bit to reset the state of the bit. This writes a 1 to the bit, followed by a 0, which is the device’s method for

clearing the asserted bit state back to logic 0.

5.1.2 Group-3 Protected Registers –

The device is provided with many configuration options set by bits contained in a special set of registers

protected against accidental writing. These RAM registers are initialized from OTP (One-Time

Programmable) EPROM cells. The device is shipped with these EPROM locations un-programmed

(blank). The Windows GUI interface hides the un-programmed nature of the device by setting defaults in

the registers cells when the Evaluation software starts (this can be defeated by setting the TOOLS |

OPTIONS defaults). The last settings are also automatically saved by the GUI and restored upon next

use. These features are provided for ease of use and are implemented solely in the GUI. Users are

responsible for programming OTP bits in parts correctly during manufacturing for correct operation in-

circuit.

Some Group-3 registers are shown as registers at the bottom of the left side of the screen, the others in

the top right section of the screen as listboxes and registers

5.1.3 Quick Access

The Quick Access register(s) provide R/W access to any location in the part. They are named arbitrarily in

the GUI ‘X’, ‘Y’, and ‘Z’ – there are no XYZ registers in the part. Some registers, such as the MASTER

X register address/data with the first unlock key, the Y register with the second unlock key, and finally the

Z register with the target address and data. Then use the “write all” button to send all three address/data

bytes in the correct order and timing to accomplish the multi-byte write. (This is done automatically when

using the Protected Registers window.)

5.1.4 LED Status Indicators

At the top right of the user interface screen are 8 status indicator "LED's". These provide a quick view of

the status of the devices, and the interface, cable connections, etc. Green normally indicates a logic 0

condition, and red a logic one condition. Gray indicates undefined.

ALERT A condition has been sensed that is causing the ALERT hardware pin to be asserted. This

is also indicated by the ALERT bit being set (red) in the [DEVICE] STATUS register. The

source of the ALERT condition is indicated in the ALERT register just below the STATUS

FAULT Similar to the ALERT indicator, this LED indicates the FAULT bit, and FAULT hardware

pin are asserted. The source is indicated in the FAULT register just below the ALERT

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Evaluation Software Details

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LAST CRC The last CRC received by the GUI was incorrect for the contents of the packet. This

usually indicates a communication error caused by improper connection, excessive

cabling, etc. The cause of the communication error should be corrected before continuing.

LOG Green if a log file is being written to. Logging is useful to capture information about cell or

interface behavior over long periods of time

STACK At least one device was found during auto-addressing or rebuild addresses. This indicates

that the bottom device in the stack was found, is powered, not in POR, and the ribbon

cable from the Aardvark to the EVM is connected correctly. This verifies the cabling and

connection all the way to the IC.

INTERFACE The Aardvark USB-SPI interface adapter was successfully found and communicated with.

This verifies the cabling and driver to the adapter.

5.1.5 Global Registers

DEVICE The Address of the device currently being communicated with. Change to access

different devices in the stack. “BROADCAST” mode also available to send a single

command to all devices in the stack. (In BROADCAST mode, no data are shown – the

interface can only display data from one device at a time.

STACK HT. The number of devices found during the last AUTO-ADDRESS or REBUILD-

ADDRESS cycle.

POLL Check or un-check this box to turn polling on or off. Note that many menu items are

unavailable during polling – turn polling off to access them.

RATE This list box allows choosing a polling rate between 100ms and 60s. The LED

illuminates green each time the GUI polls the device stack. Useful as a heartbeat

indicator when polling or logging is active. A setting “Fast” is also available. In this

position, the WinGUI will poll as fast as possible, with only Windows operating system

slowing it down. On most systems, this results in a poll every 10-20ms, but your results

may vary depending on the speed of your CPU and other tasks that are running.

LOG STACK Enables or disables data logging. Logging is to a file in comma-separated-values (.csv)

format. Set up logging in the LOG | SETUP menu. Logging may also be started /

stopped under the LOG menu. Data are captured each poll, set by the polling interval

in TOOLS | INTERFACE.

VIEW PLOT Check this box to view a dynamic plot of data collected during polling. See PLOTTING

for further information on configuring the plotter.

HW I/O Check this box to force the Evaluation software to use the hardware pins CONV and

DRDY to initiate and monitor ADC conversion cycles, instead of sending commands to

the CONVERT_CTRL[CONV] register bit. Similarly, it is monitoring the FAULT and

ALERT hardware pin states to determine a FAULT and/or ALERT condition being

present. Note that in HW I/O mode, the REFRESH button toggles the hardware CONV

line, but the user may optionally use the CONVERT_CTRL[CONV] bit to force software

initiated conversions by clicking on the bit.

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