Texas Instruments TPS3808G01-Q1EVM Manual de usuario

SLVUAY9–November 2016

TPS3808G01-Q1EVM (MSA025) Voltage Supervisor User Guide

User's Guide

SLVUAY9–November 2016

TPS3808G01-Q1EVM (MSA025) Voltage Supervisor User

Guide

This user’s guide describes the TPS3808G01-Q1EVM evaluation module (EVM). This guide contains the

EVM schematic, bill of materials (BOM), assembly drawing, and top and bottom board layouts.

Contents

1 Introduction ................................................................................................................... 2

2 Schematic, Bill of Materials, and Layout ................................................................................. 2

3 EVM Connectors............................................................................................................. 7

4 EVM Setup and Operation ................................................................................................. 7

List of Figures

1 TPS3808G01-Q1EVM Board .............................................................................................. 2

2 TTPS3808G01-Q1EVM Schematic ....................................................................................... 3

3 Component Placement—Top Assembly.................................................................................. 5

4 Component Placement—Bottom Assembly.............................................................................. 5

5 Layout—Top.................................................................................................................. 5

6 Layout—Bottom.............................................................................................................. 5

7 Top Layer..................................................................................................................... 5

8 Bottom Layer................................................................................................................. 5

9 Top Solder Mask............................................................................................................. 6

10 Bottom Solder Mask......................................................................................................... 6

11 TPS3808G01-Q1 RESET Asserted Due to MR Pulled Low ........................................................... 8

12 TPS3808G01-Q1 RESET Deasserted Due to MR Pulled High, With Delay tD, CT- Floating ....................... 8

13 TPS3808G01-Q1 RESET Deasserted Due to MR Pulled High, With Delay tD, CTTied to GND Through

100-pF capacitor............................................................................................................. 8

14 RESET Asserted Due to SENSE Voltage Falling Below VIT ........................................................... 9

15 RESET Deasserting Due to SENSE Voltage Rising Above VIT, CTis floating....................................... 9

16 RESET Deasserting Due to SENSE Voltage Rising Above VIT, CTTied to GND Through 100-pF Capacitor... 9

List of Tables

1 BOM .......................................................................................................................... 3

2 Test Points.................................................................................................................... 7

3 List of Onboard Jumpers ................................................................................................... 7

4 Nominal Supply and Typical Threshold Voltages........................................................................ 7

Trademarks

All trademarks are the property of their respective owners.

Introduction

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TPS3808G01-Q1EVM (MSA025) Voltage Supervisor User Guide

1 Introduction

The TPS3808G01-Q1EVM is an evaluation module (EVM) for the TPS3808G01-Q1 voltage supervisor.

The EVM has a supply voltage range of 1.8 V to 6.5 V, and offers input connections for all device input

and output pins. Test points are provided to give the user access to an extra ground connection if needed

for oscilloscope or multimeter measurements.

Figure 1. TPS3808G01-Q1EVM Board

1.1 Related Documentation

TPS3808Gxx-Q1 Low-Quiescent-Current Programmable-Delay Supervisory Circuit data sheet, SBVS085

1.2 TPS3808G01-Q1 Applications

• Automotive DSPs, Microcontrollers, or Microprocessors

• Safety-Critical Systems

• Automotive Systems

2 Schematic, Bill of Materials, and Layout

This section provides a detailed description of the TPS3808G01-Q1EVM schematic, bill of materials

(BOM), and layout.

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Schematic, Bill of Materials, and Layout

SLVUAY9–November 2016

TPS3808G01-Q1EVM (MSA025) Voltage Supervisor User Guide

2.1 TPS3808G01-Q1EVM Schematic

Figure 2. TTPS3808G01-Q1EVM Schematic

2.2 TPS3808G01-Q1EVM Bill of Materials

Table 1. BOM

DESIGNATOR QUANTITY VALUE DESCRIPTION PACKAGE

REFERENCE PART NUMBER MANUFACTURER

!PCB 1 Printed Circuit Board MSA025 Any

C1 1 0.1 µF CAP, CERM, 0.1 µF, 10 V, ± 10%, X7R, 0603 0603 C0603C104K8RACTU Kemet

C2 1 100 pF CAP, CERM, 100 pF, 50 V, ± 10%, C0G/NP0,

0805 0805 C0805C101K5GACTU Kemet

C3 1 0.01 µF CAP, CERM, 0.01 µF, 10 V, ± 10%, X7R, 0603 0603 0603ZC103KAT2A AVX

H9, H10, H11, H12 4 Bumpon, Hemisphere, 0.44 X 0.20, Clear Transparent Bumpon SJ-5303 (CLEAR) 3M

J1, J2 2 Header, 2.54 mm, 2x1, Gold, R/A, SMT Header, 2.54 mm, 2x1,

R/A, SMT 87898-0204 Molex

Schematic, Bill of Materials, and Layout

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Table 1. BOM (continued)

DESIGNATOR QUANTITY VALUE DESCRIPTION PACKAGE

REFERENCE PART NUMBER MANUFACTURER

J3 1 Header, 2.54 mm, 3x1, Gold, SMT Header, 2.54mm, 3x1,

SMT M20-8770342 Harwin

R1 1 100 k RES, 100 k, 1%, 0.125 W, 0805 0805 CRCW0805100KFKEA Vishay-Dale

R2 1 22.6 k RES, 22.6 k, 1%, 0.125 W, 0805 0805 CRCW080522K6FKEA Vishay-Dale

R3 1 40.2 k RES, 40.2 k, 0.5%, 0.1 W, 0805 0805 RR1220P-4022-D-M Susumu Co Ltd

R4 1 100 k RES, 100 k, 5%, 0.1 W, 0603 0603 CRCW0603100KJNEA Vishay-Dale

S1 1 Switch, Push Button, SMD 2.9x2x3.9mm SMD SKRKAEE010 Alps

TP1, TP2, TP3, TP4 4 Test Point, Miniature, SMT Test Point, Miniature,

SMT 5019 Keystone

U1 1 Low-Quiescent-Current Programmable-Delay

Supervisory Circuit, DBV0006A DBV0006A TPS3808G01QDBVRQ1 Texas Instruments

FID1, FID2, FID3 0 Fiducial mark. There is nothing to buy or mount. Fiducial N/A N/A

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Schematic, Bill of Materials, and Layout

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TPS3808G01-Q1EVM (MSA025) Voltage Supervisor User Guide

2.3 Layout and Component Placement

Figure 3 and Figure 4 top and bottom assemblies of the printed circuit board (PCB) show the component

placement on the EVM.

Figure 5 and Figure 6 show the top and bottom layouts, Figure 7 and Figure 8 show the top and bottom

layers, and Figure 9 and Figure 10 show the top and bottom solder masks of the EVM.

Figure 3. Component Placement—Top Assembly Figure 4. Component Placement—Bottom Assembly

Figure 5. Layout—Top Figure 6. Layout—Bottom

Schematic, Bill of Materials, and Layout

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Figure 7. Top Layer Figure 8. Bottom Layer

Figure 9. Top Solder Mask Figure 10. Bottom Solder Mask

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EVM Connectors

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TPS3808G01-Q1EVM (MSA025) Voltage Supervisor User Guide

3 EVM Connectors

This section describes the connectors, jumpers, and test points on the EVM as well as how to connect, set

up, and properly use the EVM. Each device has an independent supply connection, but all grounds are

connected on the board.

3.1 EVM Test Points

Table 2 lists the test points and functional descriptions. All pins of the device are broken out to test points

on the EVM.

Table 2. Test Points

Test Point

Number

Test Point

Silkscreen

Label

Function Description

TP1 RST Connection to RST pin Allows user to put an external connection and monitor

the RST pin

TP2 GND Ground Common ground connection

TP3 MR Connection to MR pin Allows user to put an external connection or monitor

the MR pin

TP4 SENSE Connection to SENSE pin Allows user to put an external connection or monitor

SENSE pin

3.2 EVM Jumpers

Table 3 lists the jumpers on the TPS3808G01-Q1EVM. As ordered, the EVM will have five jumpers

installed.

Table 3. List of Onboard Jumpers

Jumper Default Connection Description

J2 Open Connect SENSE to VDD through a resistor divider that sets VIT to 1.8V and monitors

VDD to this threshold, or leave open and connect external voltage to be monitored.

J3 Open Connect CTto VDD through a 40-kΩresistor or leave open for fixed delay times, or

connect to GND through a 100-pF capacitor for user-programmable delay time.

4 EVM Setup and Operation

This section describes the functionality and operation of the TPS3808G01-Q1EVM. The user should read

the TPS382x-Q1 datasheet for electrical characteristics of the device.

4.1 Input Power (VDD)

The VDD supply is connected through the J1 header on board. Pin 1 of this jumper is connected to the

VDD pin of the TPS3808G01-Q1 device and pin 2 is connected to the board common GND. Supply

voltage is dependent on what the user wants to monitor, but the range is 1.8 V to 6.5 V. Table 4 details

the nominal supply and typical threshold voltage.

Table 4. Nominal Supply and Typical Threshold Voltages

Device Nominal Supply Voltage (V) Typical Threshold Voltage (V)

TPS3808G01-Q1 Adjustable 0.405

EVM Setup and Operation

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4.1.1 Manual Reset (MR)

The TPS3808G01-Q1 devices offers a manual reset pin. The EVM offers a pushbutton switch that will pull

the MR pin to GND when pressed, then back to floating when released. There is also a test point

connected directly to the MR pin in case the user wants to connect the MR pin to a manual reset source.

When MR is pulled low, the RESET pin is asserted, forcing it into a low state. After MR returns to a logic

high and SENSE is above its reset threshold, RESET is deasserted high after the user-defined delay

expires. See Figure 11 through Figure 13.

Figure 11. TPS3808G01-Q1 RESET Asserted Due to MR

Pulled Low Figure 12. TPS3808G01-Q1 RESET Deasserted Due to

MR Pulled High, With Delay tD, CT- Floating

Figure 13. TPS3808G01-Q1 RESET Deasserted Due to MR Pulled High, With Delay tD, CTTied to GND Through

100-pF capacitor

V 1 0.405

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EVM Setup and Operation

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TPS3808G01-Q1EVM (MSA025) Voltage Supervisor User Guide

4.2 Voltage Sense Input (SENSE)

The TPS3808G01-Q1 device has a SENSE pin that acts as the input for the voltage being supervised.

The EVM offers a two-pin header to monitor VDD through a voltage divider set to 1.8-V threshold voltage,

and also a test point if the user wants to connect an external voltage to be monitored. The SENSE pin

provides an input at which any system voltage can be monitored unless something is supplying the

SENSE pin, RST will be held low indefinitely. If the voltage on this pin drops below VIT, RESET is asserted

low. The SENSE pin is connected internally to a comparator at the negative input and the positive input is

connected to a 0.405-V reference. Using a voltage divider, use Equation 1 to calculate VIT:

(1)

Resistor references can be seen in the EVM schematic to make sure the circuit is connected correctly.

The EVM comes with R1 = 100 kΩ, R2 = 22.6 kΩ, but both resistors can be desoldered from the board

and changed to meet the value the user requires. See data plots Figure 14 through Figure 16.

Figure 14. RESET Asserted Due to SENSE Voltage

Falling Below VIT

Figure 15. RESET Deasserting Due to SENSE Voltage

Rising Above VIT, CTis floating

T D 3

C (nF) t (s) 0.5 10 (s) 175

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EVM Setup and Operation

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Revision History

Figure 16. RESET Deasserting Due to SENSE Voltage Rising Above VIT, CTTied to GND Through 100-pF

Capacitor

4.3 Reset Output (RESET )

All TPS3808G01-Q1 devices offer an active-low RESET signal. The EVM has a test point connected

directly to the RESET pin. The reset signal will be asserted low when MR is pulled low or when the

voltage on the SENSE pin falls below VIT. When the voltage on SENSE is higher than the threshold

voltage, and the MR pin is pulled high or floating, then the reset pins will remain deasserted.

4.4 Reset Period Programming (CT)

The TPS3808G01-Q1 device has three options for setting the RESET delay time: connect to VDD through

a resistor, left floating, or connect to GND through a capacitor. Connecting CTto VDD through a resistor

sets a fixed 300-ms typical delay time and the resistor must be in the range of 40 kΩto 200 Ω. The EVM

offers the J3 jumper to connect CTto VDD through a 40.2-kΩresistor. Leave CTfloating for a fixed 20-ms

delay time. Connect CTto GND through a capacitor for a user-defined delay time from 1.25 ms to 10 s.

The capacitor should be ≥100pF to be recognized. Using Equation 2, the user can set the delay time

between the range previously mentioned:

where

• C = capacitor value

• tD= desired delay time in seconds (2)

Revision History

DATE REVISION NOTES

December 2016 * Initial Release

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